Hi,
this patchset has been tested with the following configurations:
rv64gcv_zvl128b
rv64gcv_zvl256b
rv32imafd_zve32x1p0
rv32gc_zve64f_zvl128b
Will fix the formatting in v3.
Thanks
On Wed, Dec 20, 2023 at 5:28 AM Jeff Law <jeffreya...@gmail.com> wrote:
>
>
> On 12/19/23 02:53, Sergei Lewis wrote:
> > gcc/ChangeLog
> >
> > * config/riscv/riscv.md (movmem<mode>): Use
> riscv_vector::expand_block_move,
> > if and only if we know the entire operation can be performed using
> one vector
> > load followed by one vector store
> >
> > gcc/testsuite/ChangeLog
> >
> > PR target/112109
> > * gcc.target/riscv/rvv/base/movmem-1.c: New test
> So this needs to be regression tested. Given that it only affects RVV,
> I would suggest testing rv64gcv or rv32gcv.
>
>
>
> > +(define_expand "movmem<mode>"
> > + [(parallel [(set (match_operand:BLK 0 "general_operand")
> > + (match_operand:BLK 1 "general_operand"))
> > + (use (match_operand:P 2 "const_int_operand"))
> > + (use (match_operand:SI 3 "const_int_operand"))])]
> > + "TARGET_VECTOR"
> > +{
> > + if ((INTVAL (operands[2]) >= TARGET_MIN_VLEN/8)
> > + && (INTVAL (operands[2]) <= TARGET_MIN_VLEN)
> > + && riscv_vector::expand_block_move (operands[0], operands[1],
> > + operands[2]))
> > + DONE;
> > + else
> > + FAIL;
> > +})
> Just a formatting nit. A space on each side of the '/' operator above.
>
>
> Jeff
>
