[COMMITTED] aarch64: Skip whilele_1.C test for ILP32

The definitions of the integer types for ILP32 newlib make the resolution of some of the bool-related tests ambiguous. Tested on aarch64-linux-gnu and aarch64_be-elf, committed. Richard 2020-01-23 Richard Sandiford gcc/testsuite/ * g++.target/aarch64/sve/acle/general-c++/whilele_1

Re: [PATCH] analyzer: testsuite: introduce analyzer-torture.exp

David Malcolm writes: > Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. > > OK for master? I'm working on various followup bugfixes that could > use this for test coverage. > > gcc/testsuite/ChangeLog: > * gcc.dg/analyzer/data-model-3.c: Remove hardcoded "-O2" and move >

Re: [PATCH] cprop: Don't replace fixed hard regs with pseudos [PR93124]

Jeff Law writes: > On Wed, 2020-01-22 at 12:02 +0000, Richard Sandiford wrote: >> One consequence of r276318 was that cselib now preserves sp-based >> values across function calls. This in turn convinced cprop to >> replace the clobber in: >> >

[COMMITTED] aarch64: Fix -mtrack-speculation for irreversible conditions [PR93341]

condition internally. Tested on aarch64-linux-gnu. Also tested by making sure there were no changes in asm output for fold-const.ii when compiled with -O2 -mtrack-speculation. Committed. Richard 2020-01-23 Richard Sandiford gcc/ PR target/93341 * config/aarch64/

Re: [PATCH][AArch64] ACLE 8-bit integer matrix multiply-accumulate intrinsics

Dennis Zhang writes: > Hi all, > On 16/12/2019 13:53, Dennis Zhang wrote: >> Hi all, >> >> This patch is part of a series adding support for Armv8.6-A features. >> It depends on the Armv8.6-A effective target checking patch, >> https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00857.html. >> >> Thi

Re: [PATCH] simplify-rtx: Punt for modes with precision above MAX_BITSIZE_MODE_ANY_INT [PR93376]

Jakub Jelinek writes: > Hi! > > The following patch makes sure we punt in the 3 spots if precision is above > MAX_BITSIZE_MODE_ANY_INT. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2020-01-23 Jakub Jelinek > > PR target/93376 > * simplify-rtx.c (simpl

Re: [PATCH] cprop: Don't replace fixed hard regs with pseudos [PR93124]

Jeff Law writes: > Finding a way to drop the naked clobbers/uses would be a better way > forward. I'm a bit surprised we need them as much as we apparently do. > We're conflating issues a bit here though. FWIW, I think they're a really useful feature. E.g. they help when modelling the lifetimes

Re: [PATCH] dojump: Fix gcc.dg/torture/pr91323.c for aarch64 targets

Ping Richard Sandiford writes: > PR91323 was fixed for x86 and sparc in target code, but aarch64 > instead relies on the target-independent comparison splitters. > Since LTGT is an unordered-signalling operation, we should split > it into unordered-signalling operations for any inpu

Re: [PATCH] Decrease cortexa57_extra_costs's alu.shift_reg

writes: > From: Andrew Pinski > > Like I mentioned in https://gcc.gnu.org/ml/gcc/2020-01/msg00157.html, > The shift by a register should be just COSTS_N_INSNS (1) rather than > COSTS_N_INSNS (2). This allows lshift_cheap_p to return true now > and converting switches to be using shift and other

Re: [PATCH][AArch64] ACLE 8-bit integer matrix multiply-accumulate intrinsics

Dennis Zhang writes: > [...] > gcc/ChangeLog: > > 2020-01-23 Dennis Zhang > > * config/aarch64/aarch64-builtins.c (TYPES_TERNOP_SSUS): New macro. > * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New. > (simd_ummla, simd_usmmla): New. > * config/aarch64/aarch64-

[COMMITTED] aarch64: Fix failure in cmpimm_branch_1.c

x-gnu & pushed. Richard 2020-01-27 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match jump conditions for *compare_condjump. --- gcc/config/aarch64/aarch64.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/g

[COMMITTED] aarch64: Add vector/vector vec_extract patterns [PR92822]

scan-assembler-times fmul\\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.d\\[[0-9]+\\] 3 The 2s failures need target-independent changes, after which they rely on these patterns too. Tested on aarch64-linux-gnu & pushed. Richard 2020-01-27 Richard Sandiford gcc/ PR target/92822

[PATCH] forwprop: Tweak choice of VEC_PERM_EXPR filler [PR92822]

ixing this PR. Tested on aarch64-linux-gnu and x86_64-linux-gnu. Richard mentioned in the PR that he had a different fix in mind, but since I'd tested this overnight, I thought I might as well post it anyway as a possible belt-and-braces fix. OK to install? Richard 2020-01-27 Richard S

[COMMITTED] aarch64: Fix pr71727.c failure

1-27 Richard Sandiford gcc/testsuite/ PR testsuite/71727 * gcc.target/aarch64/pr71727.c: Add -fcommon. --- gcc/testsuite/gcc.target/aarch64/pr71727.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/aarch64/pr71727.c b/gcc/testsuite/gcc.ta

[PATCH] simplify-rtx: Extend (truncate (*extract ...)) fold [PR87763]

e QI case would trigger in practice, since the zero_extract mode was restricted to HI and above. I checked the other x86 patterns and couldn't see any other instances of this. Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu, OK to install? Richard 2020-01-27 Richa

[PATCH] vect: Pattern-matched calls in reduction chains

fully" approach. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2020-01-27 Richard Sandiford gcc/ * tree-vect-loop.c (vectorizable_reduction): Fail gracefully for reduction chains that (now) include a call. --- gcc/tree-vect-loop.c | 14 ++

[PATCH] predcom: Fix invalid store-store commoning [PR93434]

ll stores in a component. But (a) we can't AFAIK use pcom_stmt_dominates_stmt_p here and (b) the handling for that case would probably need to be removed again if we handled more exotic cases in future. 2020-01-28 Richard Sandiford gcc/ PR tree-optimization/93434 * tree-predcom.c (split_data_ref

Re: [PATCH] predcom: Fix invalid store-store commoning [PR93434]

Richard Sandiford writes: > predcom has the following code to stop one rogue load from > interfering with other store-load opportunities: > > /* If A is read and B write or vice versa and there is unsuitable >dependence, instead of merging both components i

[COMMITTED] testsuite: Add -Wpsabi to gcc.dg/torture/pr93170.c [PR93460]

Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu. Pushed as obvious. Richard 2020-01-28 Richard Sandiford gcc/testsuite/ PR testsuite/93460 * gcc.dg/torture/pr93170.c: Add -Wpsabi. --- gcc/testsuite/gcc.dg/torture/pr93170.c | 1 + 1 file changed, 1

[PATCH] testsuite: XFAIL gcc.dg/torture/pr93133.c for powerpc*-*-* [PR93393]

Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu. OK to install? Richard 2020-01-28 Richard Sandiford gcc/testsuite/ PR testsuite/93393 * gcc.dg/torture/pr93133.c: XFAIL for powerpc*-*-*. --- gcc/testsuite/gcc.dg/torture/pr93133.c | 2 +- 1 file

Re: [PATCH] simplify-rtx: Extend (truncate (*extract ...)) fold [PR87763]

Jeff Law writes: > On Mon, 2020-01-27 at 16:41 +0000, Richard Sandiford wrote: >> In the gcc.target/aarch64/lsl_asr_sbfiz.c part of this PR, we have: >> >> Failed to match this instruction: >> (set (reg:SI 95) >> (ashift:SI (subreg:SI (sign_ex

Re: [GCC][BUG][Aarch64][ARM] (PR93300) Fix ICE due to BFmode placement in GET_MODES_WIDER chain.

Stam Markianos-Wright writes: > Hi all, > > This fixes: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93300 > > Genmodes.c was generating the "wider_mode" chain as follows: > > HF -> BF -> SF - > DF -> TF -> VOID > > This caused issues in some rare cases where conversion between modes > was nee

Re: [PATCH] simplify-rtx: Extend (truncate (*extract ...)) fold [PR87763]

Andreas Schwab writes: > On Jan 27 2020, Richard Sandiford wrote: > >> * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract >> simplification to handle subregs as well as bare regs. > > That breaks gcc.target/m68k/pr39726.c Gah. Jeff pointed out off

Re: [GCC][BUG][Aarch64][ARM] (PR93300) Fix ICE due to BFmode placement in GET_MODES_WIDER chain.

Stam Markianos-Wright writes: > On 1/29/20 12:42 PM, Richard Sandiford wrote: >> Stam Markianos-Wright writes: >>> Hi all, >>> >>> This fixes: >>> >>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93300 >>> >>> Genmodes.c

Re: [PATCH] arm: Fix uaddvdi4 expander [PR93494]

Jakub Jelinek writes: > Hi! > > uaddvdi4 expander has an optimization for the low 32-bits of the 2nd input > operand known to be 0. Unfortunately, in that case it only emits copying of > the low 32 bits to the low 32 bits of the destination, but doesn't emit the > addition with overflow detection

Re: [PATCH] simplify-rtx: Extend (truncate (*extract ...)) fold [PR87763]

Jeff Law writes: > On Wed, 2020-01-29 at 19:18 +0000, Richard Sandiford wrote: >> Andreas Schwab writes: >> > On Jan 27 2020, Richard Sandiford wrote: >> > >> > > * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract >> > > si

Re: [GCC][BUG][Aarch64][ARM] (PR93300) Fix ICE due to BFmode placement in GET_MODES_WIDER chain.

Stam Markianos-Wright writes: > On 1/30/20 10:01 AM, Richard Sandiford wrote: >> Stam Markianos-Wright writes: >>> On 1/29/20 12:42 PM, Richard Sandiford wrote: >>>> Stam Markianos-Wright writes: >>>>> Hi all, >>>>> >>>&g

Re: [GCC][PATCH][AArch64] ACLE intrinsics bfmmla and bfmlal for AArch64 AdvSIMD

Delia Burduv writes: > Thank you, Richard! > > Here is the updated patch. The test that checks for errors when bf16 is > disabled is in the bfcvt patch. Looks good. Just a couple of very minor things... > > Cheers, > Delia > > gcc/ChangeLog: > > 2019-11-06 Delia Burduv > > * config

Re: [GCC][PATCH][AArch64] ACLE intrinsics for BFCVTN, BFCVTN2 (AArch64 AdvSIMD) and BFCVT (AArch64 FP)

Delia Burduv writes: > [...] > diff --git a/gcc/config/aarch64/arm_bf16.h b/gcc/config/aarch64/arm_bf16.h > index > 3759c0d1cb449a7f0125cc2a1433127564d66622..fb2150e1d60a590046e2c034422021aafc721e23 > 100644 > --- a/gcc/config/aarch64/arm_bf16.h > +++ b/gcc/config/aarch64/arm_bf16.h > @@ -28,5 +

[COMMITTED] aarch64: Fix SVE PCS failures for BE & ILP32

-linux-gnu and aarch64_be-elf, pushed. Richard 2020-01-31 Richard Sandiford gcc/testsuite/ * gcc.target/aarch64/sve/pcs/args_1.c: Require lp64 for check-function-bodies tests. * gcc.target/aarch64/sve/pcs/args_2.c: Likewise. * gcc.target/aarch64/sve/pcs/args_3

[COMMITTED] aarch64: Add Armv8.6 SVE bfloat16 support

during stage 4. It should be very low risk for parts unrelated to the SVE ACLE though, so shouldn't affect anything that also existed in GCC 9. Richard 2020-01-31 Richard Sandiford gcc/ * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro. * config/aarch64/aarch64-sve-bui

Re: [PATCH] simplify-rtx: Extend (truncate (*extract ...)) fold [PR87763]

you, > > -- > Maxim Kuvyrkov > https://www.linaro.org > >> On Jan 27, 2020, at 7:41 PM, Richard Sandiford >> wrote: >> >> In the gcc.target/aarch64/lsl_asr_sbfiz.c part of this PR, we have: >> >> Failed to match this instruction: &g

Re: [PATCH][AArch64] Improve clz patterns

Wilco Dijkstra writes: > Although GCC should understand the limited range of clz/ctz/cls results, > Combine sometimes behaves oddly and duplicates ctz to remove a > sign extension. Avoid this by adding an explicit AND with 127 in the > patterns. Deepsjeng performance improves by ~0.6%. Could you

Re: [GCC][BUG][Aarch64][ARM] (PR93300) Fix ICE due to BFmode placement in GET_MODES_WIDER chain.

Stam Markianos-Wright writes: > On 1/31/20 1:45 PM, Richard Sandiford wrote: >> Stam Markianos-Wright writes: >>> On 1/30/20 10:01 AM, Richard Sandiford wrote: >>>> Stam Markianos-Wright writes: >>>>> On 1/29/20 12:42 PM, Richard Sandiford wrote: >

Re: [PATCH] i386: Omit clobbers from vzeroupper until final [PR92190]

Uros Bizjak writes: > On Tue, Feb 4, 2020 at 12:13 PM Uros Bizjak wrote: >> >> On Tue, Feb 4, 2020 at 12:05 PM Jakub Jelinek wrote: >> > >> > On Tue, Feb 04, 2020 at 11:16:06AM +0100, Uros Bizjak wrote: >> > > If it works OK, I'd rather see this functionality implemented as an >> > > epilogue_co

[PATCH] alias: Fix offset checks involving section anchors [PR92294]

Richard Sandiford writes: > [...] >> I'm not sure given the issues you've introduced if I could actually >> fill out the matrix of answers without more underlying information. >> ie, when can we get symbols without source level decls, >> anchors+interpositi

Re: [RFA] [PR rtl-optimization/90275] Handle nop reg->reg copies in cse

Jeff Law writes: > Richard & Segher, if y'all could check my analysis here, it'd be > appreciated. > > pr90275 is a P2 regression that is only triggering on ARM. David's > testcase in c#1 is the best for this problem as it doesn't require > magic flags like -fno-dce to trigger. > > The block in q

Re: [Patch][Testsuite][libgomp] – Fix check_effective_target_offload_target_nvptx for remote execution

Tobias Burnus writes: > diff --git a/libgomp/testsuite/lib/libgomp.exp > b/libgomp/testsuite/lib/libgomp.exp > index 7e94527c7ca..cb7757b6a91 100644 > --- a/libgomp/testsuite/lib/libgomp.exp > +++ b/libgomp/testsuite/lib/libgomp.exp > @@ -346,11 +346,11 @@ proc check_effective_target_offload_targ

Re: [Patch][Testsuite] – More fixes for remote execution: check_gc_sections_available, …

Tobias Burnus writes: > Still pending: libgomp-Testsuite patch > https://gcc.gnu.org/ml/gcc-patches/2020-02/msg00207.html > > This is the same fix – but for gcc/testsuite/. > > To illustrate the problem again. Using remote testing > (here: modified target_compile, but DejaGNU's default_target_com

Re: [GCC][BUG][Aarch64][ARM] (PR93300) Fix ICE due to BFmode placement in GET_MODES_WIDER chain.

Stam Markianos-Wright writes: > On 2/4/20 12:02 PM, Richard Sandiford wrote: >> Stam Markianos-Wright writes: >>> On 1/31/20 1:45 PM, Richard Sandiford wrote: >>>> Stam Markianos-Wright writes: >>>>> On 1/30/20 10:01 AM, Richard Sandiford wrote: >

Re: [PATCH 2/3] Add patch_area_size and patch_area_entry to cfun

"H.J. Lu" writes: > Currently patchable area is at the wrong place. Agreed :-) > It is placed immediately > after function label and before .cfi_startproc. A backend should be able > to add a pseudo patchable area instruction durectly into RTL. This patch > adds patch_area_size and patch_area_

Re: [PATCH] Add patch_area_size and patch_area_entry to crtl

wrote: >> > > > >> > > > On Wed, Feb 5, 2020 at 9:00 AM Richard Sandiford >> > > > wrote: >> > > > > >> > > > > "H.J. Lu" writes: >> > > > > > Currently patchable area is at the wrong

Re: [PATCH] Use a non-empty test program to test ability to link

Sandra Loosemore writes: > This patch is for PR 79193 and 88999, problems where libstdc++ is > mis-configuring itself when building for a bare-metal target because it > thinks it can link programs without pulling in the BSP that provides > low-level I/O support. (Specifically, this was observe

Re: [GCC][PATCH][AArch64] ACLE intrinsics bfmmla and bfmlal for AArch64 AdvSIMD

Delia Burduv writes: > Sure, here it is. I'll do that for the other patch too. Thanks, belatedly pushed as f78335df69993a900512f92324cab6a20b1bde0c. Sorry for the delay. Richard > > Thanks, > Delia > > On 1/31/20 3:37 PM, Richard Sandiford wrote: >> Delia Burduv w

[committed] aarch64: Add an extra sbfiz pattern [PR87763]

This patch matches another form of sbfiz, in which the input has DImode and the output has SImode. It fixes a regression in gcc.target/aarch64/lsl_asr_sbfiz.c from GCC 8. Tested on aarch64-linux-gnu & pushed. Richard 2020-02-04 Richard Sandiford gcc/ PR rtl-optimization/8

[committed] aarch64: Add an and/ior-based movk pattern [PR87763]

This patch adds a second movk pattern that models the instruction as a "normal" and/ior operation rather than an insertion. It fixes the third insv_1.c failure in PR87763, which was a regression from GCC 8. Tested on aarch64-linux-gnu & pushed. Richard 2020-02-04 Richard Sa

[committed] aarch64: Add a type attribute to aarch64_movk

Kyrill pointed out off-list that this new pattern was missing a type attribute -- sorry about that. Tested on aarch64-linux-gnu & pushed. Richard 2020-02-06 Richard Sandiford gcc/ * config/aarch64/aarch64.md (aarch64_movk): Add a type attribute. --- gcc/config/aar

Re: [PATCH] alias: Fix offset checks involving section anchors [PR92294]

Richard Biener writes: > On Tue, Feb 4, 2020 at 6:44 PM Richard Sandiford > wrote: >> >> Richard Sandiford writes: >> > [...] >> >> I'm not sure given the issues you've introduced if I could actually >> >> fill out the matrix of answe

Re: [PATCH] issues with configure --enable-checking option

Roman Zhuykov writes: > Hi! > I've investigated a bit, because some of the following confused me while > working with some local 9.2-based branch. > > Documentation issues: > (0) See patch for install.texi at the bottom, two possible values are > not documented. Ok for master? Backports? > (1) F

Re: [PATCH][AArch64] Improve clz patterns

Wilco Dijkstra writes: > Hi Richard, > >> Could you go into more detail about what the before and after code >> looks like, and what combine is doing? Like you say, this sounds >> like a target-independent thing on face value. > > It is indeed, but it seems specific to instructions where we have

Re: [PATCH][AArch64] Improve clz patterns

Wilco Dijkstra writes: > Hi Richard, > > Right, so this is an alternative approach using costs - Combine won't try to > duplicate instructions if it increases costs, so increasing the ctz cost to 2 > instructions (which is the correct cost for ctz anyway) ...agreed... > ensures we still get effi

Re: [PATCH][AArch64] Improve popcount expansion

Wilco Dijkstra writes: > The popcount expansion uses umov to extend the result and move it back > to the integer register file. If we model ADDV as a zero-extending > operation, fmov can be used to move back to the integer side. This > results in a ~0.5% speedup on deepsjeng on Cortex-A57. > > A

Re: [PATCH][AArch64] Add support for fused compare and branch

Wilco Dijkstra writes: > Hi Richard, > >> But what uses CMP_BRANCH after the patch? It looked like you renamed >> all existing uses and didn't add any new ones. > > My next patch will be adding uses of it now I've done some benchmarking > to decide when to turn it on. > >>> + && reg_referenc

Fix VIEW_CONVERT_EXPRs for VECTOR_BOOLEAN_TYPE_Ps

-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-04 Richard Sandiford gcc/ * fold-const.c (native_encode_vector_part): Handle VECTOR_BOOLEAN_TYPE_Ps that have subbyte precision. (native_decode_vector_tree): Delete, moving the bulk of the code to

Re: Add a new combine pass

ichard 2019-12-05 Richard Sandiford gcc/ * Makefile.in (OBJS): Add combine2.o * params.opt (--param=run-combine): New option. * doc/invoke.texi: Document it. * tree-pass.h (make_pass_combine2_before): Declare. (make_pass_combine2_after): Likewise.

Check for bitwise identity when encoding VECTOR_CSTs (PR 92768)

chard 2019-12-05 Richard Sandiford gcc/ PR middle-end/92768 * tree-core.h (OEP_BITWISE): New flag. * fold-const.c (operand_compare::operand_equal_p): Handle it. * tree-vector-builder.h (tree_vector_builder::equal_p): Pass it. gcc/testsuite/ PR middle-end/

Re: [Patch, GCC] Fix a condition post r278611

Sudakshina Das writes: > Hi > > While looking at vect_model_reduction_cost function, it seems Richard's > change in a recent commit r278611 missed an update to the following if > condition. Since the check for EXTRACT_LAST_REDUCTION is now split > above, the same check in the if condition will

Ping: [PATCH][C++] Pass type uses through the verify_type_context hook

Ping. Richard Sandiford writes: > This patch makes the C++ frontend work with the verify_type_context hook > [https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00942.html]. We need > some new type contexts for features that don't exist in C, but otherwise > the patch is very sim

Avoid quadratic behaviour in prune_runtime_alias_test_list

problem, but still, it's easy to remove as we go. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-06 Richard Sandiford gcc/ * tree-data-ref.c (prune_runtime_alias_test_list): Exit early for empty vectors. Avoid using ordered_remove and in

Fix @multitable handling in texi2pod.pl

s. This causes it to be underlined in the man output. Tested by making sure that it doesn't change the current gcc.pod output, but fixes the problems mentioned above when the new @multitable is added. OK to install? Richard 2019-12-05 Richard Sandiford contrib/ * texi2pod.p

Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16

Dennis Zhang writes: > 2019-12-04 Dennis Zhang > > * config/aarch64/aarch64-arches.def (armv8.6-a): New. > * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define > __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and > __ARM_FEATURE_BF16_SCALAR

Re: Ping Re: Fix libdecnumber handling of non-canonical BID significands (PR middle-end/91226)

Joseph Myers writes: > Ping. This patch > is pending > review. Like you say, it seems we no longer have a maintainer for this, and I wonder how many people other than you understand it well enough to do a meaningful technical review.

Re: Ping: [PATCH][C++] Pass type uses through the verify_type_context hook

Jason Merrill writes: > On 12/5/19 1:21 PM, Richard Sandiford wrote: >> + else if (!verify_type_context (input_location, TCTX_EXCEPTIONS, type)) >> +return false; >> + >> + else if (TYPE_REF_P (type) >> + && !verify_type

Re: [committed, amdgcn] Enable QI/HImode vector moves

, and therefore different bit-sizes, > this meant that allowing QImode or HImode could prevent it vectorizing > SImode or DImode, which are the ones we really want vectorized. > > Now that Richard Sandiford has introduced TARGET_VECTORIZE_RELATED_MODE > this issue has now been removed, and

Re: [committed, amdgcn] Enable QI/HImode vector moves

Andrew Stubbs writes: > On 06/12/2019 18:21, Richard Sandiford wrote: >> Andrew Stubbs writes: >>> Hi all, >>> >>> This patch re-enables the V64QImode and V64HImode for GCN. >>> >>> GCC does not make these easy to work with because there is

Re: [PATCH] Refactor IPA devirt a bit.

+ return IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (type_name)); > +} > + > /* A struct for encapsulating location information about an operator > and the operation built from it. > This drops the TYPE_DECL test from the original code above, which causes an ICE for C tags. Tested

Re: [RFC, vectorizer] Fix ICE with masked vectors

Andrew Stubbs writes: > Hi, > > This patch fixes an ICE in testcase gcc.dg/vect/vect-ctor-1.c: > > during GIMPLE pass: vect > dump file: vect-ctor-1.c.159t.vect > .../gcc.dg/vect/vect-ctor-1.c: In function 'intrapred_luma_16x16': > .../gcc.dg/vect/vect-ctor-1.c:9:6: internal compiler error: in >

Fix EXTRACT_LAST_REDUCTION handling of pattern stmts

ied to replace the pattern statement in this way, rather than replacing the original scalar statement. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-10 Richard Sandiford gcc/ * tree-vect-stmts.c (vect_finish_replace_stmt): Always use the or

[committed] Disallow EXTRACT_LAST_REDUCTION for reduction chains

work. Tested on aarch64-linux-gnu and x86_64-linux-gnu, applied as obvious. Richard 2019-12-10 Richard Sandiford gcc/ * tree-vect-loop.c (vectorizable_reduction): Don't use EXTRACT_LAST_REDUCTION for chained reductions. Index: gcc/tree-v

Record the loop masks needed for EXTRACT_LAST_REDUCTIONs

2019-12-10 Richard Sandiford gcc/ * tree-vect-stmts.c (vectorizable_condition): Record the loop masks required for extract-last reductions. gcc/testsuite/ * gcc.target/aarch64/sve/clastb_9.c: New test. Index: gcc/tree-ve

Add missing conversion in vect_create_epilog_for_reduction

x86_64-linux-gnu. OK to install? Richard 2019-12-10 Richard Sandiford gcc/ * tree-vect-loop.c (vect_create_epilog_for_reduction): When handling direct_slp_reduc, allow the PHI arguments to have a different type from the vector elements. Index: gcc/tree-vect-loop.c

Make dwarf2out punt for MODE_VECTOR_BOOL

r now the safest thing is to punt, like we already do for variable-length vectors. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-10 Richard Sandiford gcc/ * dwarf2out.c (loc_descriptor): Punt for MODE_VECTOR_BOOL. (add_const_value_attr

[committed][AArch64] Fix INDEX patterns for partial VNx2 modes

hoice between Wn and Xn registers would need to be updated to use the container size too. For partial VNx2s, we were using .d containers with Wn rather than Xn source registers. Tested on aarch64-linux-gnu, applied as r279173. Richard 2019-12-10 Richard Sandiford gcc/ * config/aa

[committed][AArch64] Don't allow partial SVE modes in GPRs

ng it into a GPR via register operations would be expensive. Tested on aarch64-linux-gnu, applied as r279174. Richard 2019-12-10 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't allow SVE modes in GPRs. gcc/testsuite/ *

Re: [PATCH] Fix vect rotate pattern recog (PR target/92723)

Jakub Jelinek writes: > Hi! > > Unlike x86, where the last operand of vector by scalar shift is DImode for > V[248]DImode shifts, on aarch64 they seem to be SImode. > vect_recog_rotate_pattern when the rotate amount is not constant casts the > amount to the element type of the vector, so for V[248

Re: [PATCH] Fix vect rotate pattern recog (PR target/92723)

Jakub Jelinek writes: > On Wed, Dec 11, 2019 at 04:52:30PM +0000, Richard Sandiford wrote: >> WDYT about instead having: >> >> if (dt != vect_internal_def || TYPE_MODE (TREE_TYPE (oprnd1)) == mode) >> >> and removing the ext_def stuff? I'd have expec

Re: [PATCH] Fix simplify-rtx.c handling of avx512 vector comparisons (PR target/92908)

Richard Biener writes: > On December 12, 2019 12:56:01 AM GMT+01:00, Jakub Jelinek > wrote: >>Hi! >> >>The AVX512{F,VL} vector comparisons that set %kN registers are >>represented >>in RTL as comparisons with vector mode operands and scalar integral >>result, >>where at runtime the scalar intege

Re: AW: [PATCH] m68k architecture: support ccmode + lra

Stefan Franke writes: > Am 2019-12-08 01:54, schrieb Oleg Endo: >> On Tue, 2019-11-26 at 07:38 +0100, ste...@franke.ms wrote: >>> > On 11/21/19 10:30 AM, ste...@franke.ms wrote: >>> > > Hi there, >>> > > >>> > > here is mc68k's patch to switch the m68k architecture over to ccmode >>> > > and >>> >

Add a compatible_vector_types_p target hook

tests. I'm still planning to fix that as a follow-on. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-12 Richard Sandiford gcc/ * target.def (compatible_vector_types_p): New target hook. * hooks.h (hook_bool_const_tree_const_tree_true

Fix tree-nrv.c ICE for direct internal functions

xist in C, the target hook was complaining about an unexpected use of SVE modes. (And we want to keep asserting for that, so that we don't accidentally define an ABI for an unexpected corner case.) Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-12

[C++ PATCH] Make same_type_p return false for gnu_vector_type_p differences (PR 92789)

comptypes (t1, t2, strict); Since structural_comptypes ignored the COMPARE_STRUCTURAL bit of "strict" before the patch, the "else if" was harmless but AFAICT unnecessary. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-12-12 Richard Sandiford g

Re: Add a compatible_vector_types_p target hook

Richard Biener writes: > On December 12, 2019 4:10:33 PM GMT+01:00, Richard Sandiford > wrote: >>One problem with adding an N-bit vector extension to an existing >>architecture is to decide how N-bit vectors should be passed to >>functions and returned from functions. A

Re: Add a compatible_vector_types_p target hook

Richard Biener writes: > On December 12, 2019 5:44:25 PM GMT+01:00, Richard Sandiford > wrote: >>Richard Biener writes: >>> On December 12, 2019 4:10:33 PM GMT+01:00, Richard Sandiford >> wrote: >>>>One problem with adding an N-bit vector extension to an

Re: Add a compatible_vector_types_p target hook

Richard Biener writes: The AArch64 port emits an error if calls pass values of SVE type to >>an unprototyped function. To do that we need to know whether the value really is an SVE type rathr than a plain vector. For varags the ABI is the same for 256 bits+. But we'll have t

Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16

Dennis Zhang writes: > Hi Richard, > > On 06/12/2019 10:22, Richard Sandiford wrote: >> Dennis Zhang writes: >>> 2019-12-04 Dennis Zhang >>> >>> * config/aarch64/aarch64-arches.def (armv8.6-a): New. >>> * config/aarch6

Re: [GCC][PATCH][AArch64]Add ACLE intrinsics for dot product (usdot - vector, dot - by element) for AArch64 AdvSIMD ARMv8.6 Extension

Stam Markianos-Wright writes: > @@ -573,6 +586,44 @@ >[(set_attr "type" "neon_dot")] > ) > > +;; These instructions map to the __builtins for the armv8.6a I8MM usdot, > sudot > +;; (by element) Dot Product operations. > +(define_insn "aarch64_dot_lane" > + [(set (match_operand:VS 0 "regis

Re: [GCC][testsuite][ARM][AArch64] Add ARM v8.6 effective target checks to target-supports.exp

Stam Markianos-Wright writes: > Hi all, > > This small patch adds support for the ARM v8.6 extensions +bf16 and > +i8mm to the testsuite. This will be tested through other upcoming > patches, which is why we are not providing any explicit tests here. > > Ok for trunk? > > Also I don't have commi

Re: Add a compatible_vector_types_p target hook

Richard Biener writes: >>> The frontend are in charge of specifying the actual argument type and >>> at that point the target may fix the ABI. The ABI can be recorded in >>> the calls fntype, either via its TYPE_ARG_TYPES or in more awkward >>> ways for varargs functions (in full generality that w

Re: AW: [PATCH] m68k architecture: support ccmode + lra

John Paul Adrian Glaubitz writes: > Hi! > > On 12/13/19 4:06 PM, Oleg Endo wrote: >>> What are the combine2 patches? >> >> See the other thread that I've linked in my message. > > I don't see any patch there. The latest version is: https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00287.html Origina

Re: Add a compatible_vector_types_p target hook

Richard Biener writes: > On December 13, 2019 10:12:40 AM GMT+01:00, Richard Sandiford > wrote: >>Richard Biener writes: >>>>>>The AArch64 port emits an error if calls pass values of SVE type to >>>>an >>>>>>unprototyped function. To

Re: [patch] Guard aarch64/aapcs64 tests using abitest.S by check_weak_available

Olivier Hainque writes: > Hello, > > Some tests from gcc/testsuite/gcc.target/aarch64/aapcs64 > resort to the abitest.S source, which defines a few weak symbols: > > ... > .weak testfunc > .weak testfunc_ptr > .weak saved_return_address > > The attached patch is a proposal to preven

Re: [patch] Guard aarch64/aapcs64 tests using abitest.S by check_weak_available

Olivier Hainque writes: >> On 16 Dec 2019, at 11:19, Richard Sandiford >> wrote: > >>> * gcc.target/aarch64/aapcs64/aapcs64.exp: Guard tests using >>> abitest.S by check_weak_available. >> >> OK, thanks. > > Great, thanks for your

Re: Add a compatible_vector_types_p target hook

Richard Biener writes: > On December 14, 2019 11:43:48 AM GMT+01:00, Richard Sandiford > wrote: >>Richard Biener writes: >>> On December 13, 2019 10:12:40 AM GMT+01:00, Richard Sandiford >> wrote: >>>>Richard Biener writes: >>>>>>>

Re: [GCC][testsuite][ARM][AArch64] Add ARM v8.6 effective target checks to target-supports.exp

Stam Markianos-Wright writes: > On 12/13/19 11:15 AM, Richard Sandiford wrote: >> Stam Markianos-Wright writes: >>> Hi all, >>> >>> This small patch adds support for the ARM v8.6 extensions +bf16 and >>> +i8mm to the testsuite. This will be tested thr

[RFC][C++ PATCH] Don't mangle attributes that have a space in their name

e adding new flags much simpler in future. What do you think? Do any of these sound OK, or is there a better way of doing it? Tested on aarch64-linux-gnu and x86_64-linux-gnu. Thanks, Richard 2019-12-18 Richard Sandiford gcc/cp/ * mangle.c (write_CV_qualifiers_for_type): Don't ma

Re: [GCC][PATCH][Aarch64] Add Bfloat16_t scalar type, vector types and machine modes to Aarch64 back-end [1/2]

Stam Markianos-Wright writes: > [...] > @@ -659,6 +666,8 @@ aarch64_simd_builtin_std_type (machine_mode mode, >return float_type_node; > case E_DFmode: >return double_type_node; > +case E_BFmode: > + return aarch64_bf16_type_node; > default: >gcc_unreacha

Re: [GCC][PATCH][Aarch64] Add Bfloat16_t scalar type, vector types and machine modes to Aarch64 back-end [2/2]

Stam Markianos-Wright writes: > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index f57469b6e23..f40f6432fd4 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -21661,6 +21661,68 @@ aarch64_stack_protect_guard (void) >return NULL_

[AArch64] Handle arguments and return types with partial SVE modes

. [*] Advanced SIMD always wins for 64-bit and 128-bit vectors though. Tested on aarch64-linux-gnu, applied as r279571. Richard 2019-12-19 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_function_value_1): New function, split out from... (aarch64_function_value

[committed][AArch64] Reject invalid subregs involving partial SVE modes

When adding partial SVE modes, I'd remembered to handle reloads in a similar way to full big-endian SVE vectors, but forgot the just-as-important mode-change rules. Tested on aarch64-linux-gnu and applied as r279572. Richard 2019-12-19 Richard Sandiford gcc/ * config/aa

[AArch64] Fix handling of npatterns>1 constants for partial SVE modes

that because they're forbidden by aarch64_can_change_class_mode; we should handle them in the same way as for big-endian instead. Tested on aarch64-linux-gnu and applied as r279580. Richard 2019-12-19 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_simd_valid_immedi

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