On 07/11/2022 08:57, Andrea Corallo via Gcc-patches wrote:
Hi all,
please find attached the lastest version of this patch incorporating some
more improvents. Feel free to ignore V3.
Best Regards
Andrea
> As part of previous upstream suggestions a test for varargs has been
> added and
On 28/10/2022 17:40, Andrea Corallo via Gcc-patches wrote:
Hi all,
please find attached the third iteration of this patch addresing review
comments.
Thanks
Andrea
@@ -23374,12 +23374,6 @@ output_probe_stack_range (rtx reg1, rtx reg2)
return "";
}
-static bool
-aarch_bti_enabled (
On 06/12/2022 15:46, Andrea Corallo wrote:
Hi Richard,
thanks for reviewing.
Just one clarification before I complete the respin of this patch.
Richard Earnshaw writes:
[...]
Also, I think (out of an abundance of caution) we really need a
scheduling barrier placed before calls to gen_au
On 31/10/2022 15:36, Srinath Parvathaneni via Gcc-patches wrote:
Hi,
This patch adds the support for pacbti multlilib linking by making
"-mbranch-protection=none" as default in the command line for all M-profile
targets and uses "-mbranch-protection=none" for multilib matching. If any
valid v
On 09/11/2022 14:32, Srinath Parvathaneni via Gcc-patches wrote:
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to em
On 08/12/2022 16:39, Tamar Christina via Gcc-patches wrote:
Hi All,
At -O0 (as opposed to e.g. volatile) we can get into the situation where the
in0 and result RTL arguments passed to the division function are memory
locations instead of registers. I think we could reject these early on by
c
On 17/12/2021 15:52, Andrea Corallo wrote:
Hi Richard,
thanks for reviewing! Some comments inline.
Richard Earnshaw writes:
On 05/11/2021 08:52, Andrea Corallo via Gcc-patches wrote:
Hi all,
this patch enables address return signature and verification based
on
Armv8.1-M Pointer Authentic
On 24/11/2021 12:18, Richard Earnshaw via Gcc-patches wrote:
On 24/11/2021 12:15, Murray Steele wrote:
On 18/11/2021 15:40, Richard Earnshaw wrote:
On 16/11/2021 10:14, Murray Steele via Gcc-patches wrote:
Hi all,
This patch moves the arm_simd_type and arm_type_qualifiers enums, and
On 09/12/2021 15:24, Murray Steele via Gcc-patches wrote:
Changes from original patch:
1. Make mentioned changes to changelog.
2. Add namespace-end comments.
3. Add #error for when arm-mve-builtins.def is included without
defining DEF_MVE_TYPE.
4. Make placement of '#undef DEF_MVE_TYPE' c
On 22/12/2021 15:55, Murray Steele via Gcc-patches wrote:
> Hi All,
>
> This patch fixes the implementation of the existing __arm_vld1q_z* and
> __arm_vst1q_p* MVE intrinsic functions.
>
> The MVE ACLE allows for __ARM_MVE_PRESERVE_USER_NAMESPACE to be defined,
> which removes definitions for int
On 12/01/2022 09:02, Martin Liška wrote:
Hello.
We've got -Wformat-diag for some time and I think we should start using it
in -Werror for GCC bootstrap. The following patch removes last pieces of
the warning
for aarch64 target.
Ready to be installed?
Thanks,
Martin
OK.
R.
gcc/ChangeL
On 12/01/2022 12:59, Martin Liška wrote:
Hello.
We've got -Wformat-diag for some time and I think we should start using it
in -Werror for GCC bootstrap. The following patch removes last pieces of
the warning
for ARM target.
> diff --git a/gcc/config/arm/arm-builtins.c
b/gcc/config/arm
My change r13-416-g485a0ae0982abe caused the compiler to stop
generating auto-inc operations on mve loads and stores. The fix
is to check whether there is a replacement register available
when in strict mode and the register is still a pseudo.
gcc:
PR target/107674
* config/arm/
On 11/04/2023 10:46, Richard Sandiford via Gcc-patches wrote:
writes:
ARM SVE has：svint8_t, svint8x2_t, svint8x3_t, svint8x4_t
As far as I known, they don't have tuple type for partial vector.
Yeah, there are no separate types for partial vectors, but there
are separate modes. E.g. VNx2QI
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