On Wed, Aug 26, 2020 at 12:08 PM Richard Biener via Gcc-patches
wrote:
>
> On Tue, Aug 25, 2020 at 6:32 PM Maciej W. Rozycki wrote:
> >
> > Hi Kito,
> >
> > > I just found the mail thread about div mod with -fnon-call-exceptions,
> > > I think keeping the default LIB2_DIVMOD_EXCEPTION_FLAGS uncha
On Thu, Sep 3, 2020 at 6:13 PM Kees Cook via Gcc-patches
wrote:
>
> On Thu, Sep 03, 2020 at 09:29:54AM -0500, Qing Zhao wrote:
> > On average, all the options starting with “used_…” (i.e, only the
> > registers that are used in the routine will be zeroed) have very low
> > runtime overheads, at
On Wed, Apr 22, 2020 at 5:38 AM Joel Jones via Gcc-patches
wrote:
>
> I just joined the gcc-patches list, so I hope the mail software can parse
> this out with an "In-Reply-To" header.
>
> I work for Marvell, and Anton's work is approved for submittal. I wrote the
> first version of the .md file
On Wed, Apr 22, 2020 at 8:25 PM Joel Jones wrote:
>
> Yes, Bellsoft's contribution is to be covered under the Marvell copyright
>
> assignment, as this is a work for hire.
Thanks !
Ramana
>
>
>
> Joel
>
>
>
> >Yes, Bellsoft's contribution is to be covered under the Marvell copyright
>
> >assign
On Wed, Apr 29, 2020 at 11:30 AM Richard Sandiford
wrote:
>
> Essentially the same fix as for x86.
>
> Tested on arm-linux-gnueabihf and armeb-eabi. Bordering on the obvious
> I guess, but OK to install?
>
> Richard
>
Ok.
Ramana
>
> 2020-04-29 Richard Sandiford
>
> gcc/
> * config/a
On Wed, Apr 29, 2020 at 4:19 PM Christophe Lyon via Gcc-patches
wrote:
>
> Remove two duplicate entries in isr_attribute_args ("abort" and
> "ABORT").
>
> 2020-04-29 Christophe Lyon
>
> PR target/57002
> gcc/
> * config/arm/arm.c (isr_attribute_args): Remove duplicate en
On Thu, May 14, 2020 at 3:57 PM Christophe Lyon via Gcc-patches
wrote:
>
> While running the tests with -march=armv5t -mthumb, I came across this
> error message which I think could be clearer.
>
> 2020-05-14 Christophe Lyon
>
> gcc/
> * config/arm/arm.c (thumb1_expand_prologue)
On Thu, May 14, 2020 at 3:58 PM Christophe Lyon via Gcc-patches
wrote:
>
> The same code pattern occurs in several functions, so it seems cleaner
> to move it into a dedicated function.
>
> 2020-05-14 Christophe Lyon
>
> gcc/
> * config/arm/arm.c (reg_needs_saving_p): New functi
> static bool reg_needs_saving_p (unsigned reg)
> {
>unsigned long func_type = arm_current_func_type ();
Ah ok , you needed it here.
Ramana
On Fri, May 15, 2020 at 7:36 AM Christophe Lyon
wrote:
>
> On Thu, 14 May 2020 at 17:58, Ramana Radhakrishnan
> wrote:
> >
> > > static bool reg_needs_saving_p (unsigned reg)
> > > {
> > >unsigned long func_type = arm_current_func_type ();
> &g
On Fri, May 15, 2020 at 12:31 PM Srinath Parvathaneni
wrote:
>
> Armv8.1-M Mainline Security Extensions related changes in GCC-10.
>
>
> ### Attachment also inlined for ease of reply
> ###
>
>
> diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
>
On Mon, Apr 27, 2020 at 2:22 PM Andre Vieira (lists)
wrote:
>
> Hi,
>
> The code change that caused this regression was not meant to affect neon
> code-gen, however I missed the REG fall through. This patch makes sure
> we only get the left-hand of the PLUS if it is indeed a PLUS expr.
>
> I sugg
Update affiliation as I'm moving on from Arm. More from me in a month or so.
Pushed to trunk
regards
Ramana
commit 4e5f373406ed5da42c4a7c4b7f650d92195f2984
Author: Ramana Radhakrishnan
Date: Fri Nov 4 09:30:00 2022 +
Update affiliation
diff --git a/htdocs/steering.html b/h
while I fix my environment ?
gcc/ChangeLog:
PR target/92999
* config/arm/arm.c (aapcs_vfp_allocate_return_reg): Adjust to handle
aggregates with elements smaller than SFmode.
gcc/testsuite/ChangeLog:
* gcc.target/arm/pr92999.c: New test.
Thanks,
Ramana
Signed-off-by: Ramana Radhakrishnan
On Thu, Nov 10, 2022 at 6:03 PM Richard Earnshaw
wrote:
>
>
>
> On 10/11/2022 17:21, Richard Earnshaw via Gcc-patches wrote:
> >
> >
> > On 08/11/2022 18:20, Ramana Radhakrishnan via Gcc-patches wrote:
> >> PR92999 is a case where the VFP calling conv
On Thu, Nov 10, 2022 at 10:24 AM Srinath Parvathaneni via Gcc-patches
wrote:
>
> Hi,
>
> This patch adds the -mcpu support for the Arm Cortex-X1C CPU.
>
> Regression tested on arm-none-eabi and bootstrapped on
> arm-none-linux-gnueabihf.
>
> Ok for GCC master?
Ok
Ramana
>
> Regards,
> Srinath.
On Thu, Nov 10, 2022 at 7:46 PM Ramana Radhakrishnan
wrote:
>
> On Thu, Nov 10, 2022 at 6:03 PM Richard Earnshaw
> wrote:
> >
> >
> >
> > On 10/11/2022 17:21, Richard Earnshaw via Gcc-patches wrote:
> > >
> > >
> > > On 08/11/2022 18:20
>
> OK with the comment typos fixed.
>
> > > > gcc/ChangeLog:
> > > >
> > > > 2018-11-11 Tamar Christina
> > > >
> > > > * config/aarch64/aarch64-simd.md (aarch64_fcadd,
> > > > fcadd3, aarch64_fcmla,
> > > > fcmla4): New.
> > > > * config/aarch64/aarch64.h (TAR
On Fri, Nov 11, 2022 at 9:50 PM Ramana Radhakrishnan
wrote:
>
> On Thu, Nov 10, 2022 at 7:46 PM Ramana Radhakrishnan
> wrote:
> >
> > On Thu, Nov 10, 2022 at 6:03 PM Richard Earnshaw
> > wrote:
> > >
> > >
> > >
> > &
On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via Gcc-patches
wrote:
>
> Hi,
>
> This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When
> an exception is taken and "0xb5" instruction is encounter during runtime
> stack-unwinding, we use effective vsp as modifier in po
On Thu, Nov 17, 2022 at 5:30 PM Richard Sandiford via Gcc-patches
wrote:
>
> Wilco Dijkstra writes:
> > Hi Richard,
> >
> >> Can you go into more detail about:
> >>
> >>Use :option:`-mdirect-extern-access` either in shared libraries or in
> >>executables, but not in both. Protected symbo
On Mon, Oct 24, 2022 at 9:55 AM Eric Botcazou via Gcc-patches
wrote:
>
> Hi,
>
> until most other machine attributes, this one does not work in Ada because,
> while it applies to pointer-to-function types, it is explicitly marked as
> requiring declarations in the implementation.
>
> Now, in Ada,
On Fri, Nov 18, 2022 at 9:33 AM Srinath Parvathaneni
wrote:
>
> Hi,
>
> > -Original Message-
> > From: Ramana Radhakrishnan
> > Sent: Thursday, November 17, 2022 8:27 PM
> > To: Srinath Parvathaneni
> > Cc: gcc-patches@gcc.gnu.org; Richard Earnsha
On Fri, Nov 18, 2022 at 4:59 PM Kyrylo Tkachov via Gcc-patches
wrote:
>
>
>
> > -Original Message-
> > From: Andrea Corallo
> > Sent: Thursday, November 17, 2022 4:38 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov ; Richard Earnshaw
> > ; Stam Markianos-Wright > wri...@arm.com
o the tree later this week after having built armhf and
a bootstrap and test run on aarch64-linux-gnu.
Thanks,
Ramana
commit 7dd15fae0ac1455f5818a1fc0078e35d85e1e250
Author: Ramana Radhakrishnan
Date: Wed Nov 16 10:32:04 2022 +
[Patch Arm] Add neon_fcadd and neon_fcmla to is
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