On Thu, Apr 3, 2014 at 2:27 PM, Charles Baylis
wrote:
> Hi
>
> This bug causes the compiler to create a Thumb-2 TBB instruction with
> a jump table containing an out of range value in a .byte field:
>
> whatever.s:148: Error: value of 256 too large for field of 1 bytes at 100
>
> This occurs becau
On Thu, Apr 3, 2014 at 9:22 PM, Jeff Law wrote:
>
>
> As noted in the PR, there are a few insns in the ARM backend which use
> const_int_operand as a predicate, but which have constraints like "I" or
> "M".
>
> With the predicate accepting all constants, it's possible for a pass such as
> combine
On Thu, Mar 27, 2014 at 11:25 AM, Ramana Radhakrishnan wrote:
> Hi,
>
>This is a partial fix for PR60655 where dwarf2out.c rejects NOT of a
> value in const_ok_for_output_1. There is still a problem with the testcase
> on armhf where we get operations of the form, const (m
>>
>> My first reaction is to wonder why this is this not a bug in the
>> "shorten" phase.
>
> I don't think that code ever expected an alignment directive to be emitted
> by ASM_OUTPUT_CASE_END :(
Fair point and it looks like this support came in when the support for
Thumb2 was added eons ago.
>
On Fri, Apr 4, 2014 at 1:35 PM, Kyrill Tkachov wrote:
> Hi all,
>
> In PR 60743 it is noted that the genautomata computation has increased a lot
> in both size and time due to my recently added a53 scheduling additions.
> This patch attempts to mitigate that by reducing the large reservation
> dur
As subject says.
Applied as obvious.
Ramana
2014-04-07 Ramana Radhakrishnan
* gcc.target/arm/pr60657.c: Fix missing curly brace.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.Index: gcc/testsuite/ChangeLog
Sorry about the delayed review. I seem to have missed this earlier.
On Tue, Mar 25, 2014 at 12:21 PM, Eric Botcazou wrote:
> Hi,
>
> because of popular demand we switched the Ada compiler to ZCX, i.e. table-
> driven EH scheme, on ARM/Linux, only to discover that GCC doesn't generate
> correct EH
".popsection\n");
#endif
Forgot to mention:
the patch has been tested on ARM - no regressions.
And by that what do you mean ?
arm-eabi , arm-linux-gnueabi(hf) with / without Neon, ARM state / Thumb
state ?
regards
Ramana
Best regards,
Merzlyakov Alexey
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
he typical distro configuration - testing came back clean.
Applied to trunk.
regards
Ramana
2014-04-10 Ramana Radhakrishnan
PR debug/60655
* config/arm/arm.c (TARGET_CONST_NOT_OK_FOR_DEBUG_P): Define
(arm_const_not_ok_for_debug_p): Reject MINUS with SYM_REF's
4.9 changes for ARM / AArch64. Sorry it's taken me a while to get this
out but better late than never :)
Ok ?
Ramana
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.Index: htdocs/gcc-4.9/changes.html
===
RCS file: /cv
On Tue, Apr 8, 2014 at 6:28 PM, Steve Ellcey wrote:
> On Tue, 2014-04-08 at 10:10 +0200, Dominique Dhumieres wrote:
>> > richi asked for a testcase for 60731, and since we didn't already
>> > have support for tests using dlopen, I had to add it.
>> > Does this approach make sense?
>>
>> r209187 ca
On Wed, Apr 2, 2014 at 12:04 PM, Jiong Wang wrote:
>
> On 25/03/14 15:44, Richard Earnshaw wrote:
>>
>> On 24/03/14 11:26, Jiong Wang wrote:
>>>
>>> This patch enables tail call optimization for long call on arm.
>>>
>>> Previously we have too strict check on arm_function_ok_for_sibcall and
>>> be
On Tue, Apr 22, 2014 at 7:26 AM, Zhenqiang Chen
wrote:
> Hi,
>
> ARM trunk build fail from @209484, since it requires the argument of
> GET_MODE_SIZE to be "enum machine_mode".
>
> gcc/gcc/config/arm/arm.c:21433:13: error: invalid conversion from
> 'int' to 'machine_mode' [-fpermissive]
> ...
>
>
On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon
wrote:
> On 27 February 2014 14:58, Ramana Radhakrishnan wrote:
>> Hi
>>
>> I noticed that for T32 we don't allow any old register for DImode values.
>> The restriction of an even register is true only for ARM
On Fri, Mar 28, 2014 at 3:50 PM, Alan Lawrence wrote:
> Final patch in series, adds new tests of the ARM TRN Intrinsics, that also
> check
> the execution results, reusing the test bodies introduced into AArch64 in
> the
> first patch. (These tests subsume the autogenerated ones in
> testsuite/gcc
On Wed, Apr 23, 2014 at 2:06 PM, Ramana Radhakrishnan
wrote:
> On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon
> wrote:
>> On 27 February 2014 14:58, Ramana Radhakrishnan wrote:
>>> Hi
>>>
>>> I noticed that for T32 we don't allow any old register
On Wed, Apr 23, 2014 at 8:43 PM, Marc Glisse wrote:
> On Wed, 23 Apr 2014, Richard Henderson wrote:
>
>> On 04/13/2014 01:41 AM, Marc Glisse wrote:
>>>
>>> Hello,
>>>
>>> this patch generates typeinfo for target types. On x86_64, it adds these
>>> 6
>>> lines to nm -C libsupc++.a. A follow-up patc
>> Well some of these scalar types are not really user visible which is
>> where I believe the problem is coming from and prima-facie I don't
>> think we should be inventing mangling for some of these "internal"
>> types.
>
>
> If the types are not user-visible, it is not clear to me why they need
On Thu, Apr 24, 2014 at 2:54 PM, Kyrill Tkachov wrote:
> On 24/04/14 14:44, Ryan Mansfield wrote:
>>
>> On 14-04-23 11:38 AM, Kyrill Tkachov wrote:
>>>
>>> http://gcc.gnu.org/ml/gcc-patches/2014-03/msg00934.html
>>> (http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01634.html)
>>
>> This patch breaks
gcc/testsuite/ChangeLog
2012-12-11 Kyrylo Tkachov
Missing reference to PR in the testsuite changelog entry.
* gcc.target/arm/pr55642.c: New testcase.
Ok with that change.
Ramana
On Wed, Nov 28, 2012 at 5:53 AM, Terry Guo wrote:
> Hello,
>
> Attached patch intends to fix a bug on how to check argument register number
> which should consider the PCS. A test case is also included. Without this
> fix, one of the function argument will be overridden in the case. Tested on
> QE
On 12/13/12 14:26, Kyrylo Tkachov wrote:
Hi all,
This patch adds a copyright notice to the recently added unspecs.md file in
the arm backend (r193204). The file just gathered some unspecs definitions
into one place.
Ok for trunk?
Ouch - my (real) bad at having missed this in the review.
Plea
On 01/14/13 23:03, Janis Johnson wrote:
The options specified for gcc.target/arm/fma.c and fma-sp.c can conflict
with several multilib options. This patch skips the tests for multilibs
with conflicting options, and it adds option "-mfloat-abi=hard" which is
needed for the test.
OK for trunk?
J
ead of just one more inequality test.
The only part I'm not sure about is how to treat the simple_alu_shift
category here , so a patch to handle them in the pj4 pipeline
description would be welcome.
Thanks
Ramana
2013-01-18 Yi-Hsiu Hsu
Ramana Radhakrishnan
* co
On 01/20/13 20:36, Matthias Klose wrote:
Am 18.01.2013 15:28, schrieb Ramana Radhakrishnan:
On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
marvell-pj4 is added to BE8_LINK_SPEC.
Sorry about the time it's taken to finish this patch up. I seem to have missed
this one in the review process.
I&#
Fix up wrong file committed earlier to incorporate the changes as in my
original patch. Additionally fix up copyright years.
Applied to trunk.
regards
Ramana
2013-01-21 Ramana Radhakrishnan
PR target/56058
* config/arm/marvell-pj4.md: Update copyright year.
Fix up
pj4_shift): Handle simple_alu_shift.
Cheers,
Yi-Hsiu, Hsu
-Original Message-----
From: Ramana Radhakrishnan [mailto:ramra...@arm.com]
Sent: Friday, January 18, 2013 10:28 PM
To: Yi-Hsiu Hsu
Cc: gcc-patches@gcc.gnu.org ;
Subject: Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores
On 06/2
On 01/21/13 10:55, Jakub Jelinek wrote:
Hi!
As can be seen on the testcase, this backend bug is still reproduceable even
on trunk, the backend just can't rely on cstoredi4 or cbranchdi4 expansion
not being performed with two constants, unless it has predicates that
disallow it (Steven's patch in
On 01/15/13 16:31, Janis Johnson wrote:
On 01/14/2013 03:04 PM, Janis Johnson wrote:
Test gcc.target/arm/neon-vld1_dupQ.c started failing with r194594, a C
front end change that causes the test to get warnings. The test passes
local variables of type int64x1_t to functions declared with argumen
On 01/22/13 09:21, Xinyu Qi wrote:
Ping,
Fix ChangeLog
The ChangeLog format includes .
If you want a patch accepted in the future, please help by creating the
Changelog entry in the correct format, i.e. fill in the author's name as
well as email address as below. I've created an entry
age this for 4.9 ?
regards,
Ramana
gcc/
Ramana Radhakrishnan
PR driver/47785
* gcc.c (set_collect_as_options): New.
(main): Call this.
* lto-wrapper.c (run_gcc): Handle COLLECT_AS_OPTIONS.
testsuite/
Ramana Radhakrishnan
PR driver/47785
*
On 01/23/13 15:36, Richard Biener wrote:
On Tue, Jan 22, 2013 at 5:00 PM, Ramana Radhakrishnan wrote:
Hi,
I ran into PR driver/47785 when doing some testing with an option passed to
the testsuite and I chose to fix this by putting out COLLECT_AS_OPTIONS as
though these are options for the
Well, if you look at the testcase you added with your patch you see
-Wa,--defsym=x=42, so the answer is yes.
Bah I must be blind.
Ramana
Richard.
cheers,
Ramana
[Taking gcc-help off this thread.]
Amol,
I have tested these instruction with GCC and these instructions are generated.
Please review and marge this test support patch in gcc main trunk.
Thanks for this patch and sorry about the delay in getting around to this.
This is ok and I'll take thi
gcc/
2013-01-03 Greta Yorsh
* config/arm/arm.md (type): Add ffmas and ffmad to "type" attribute.
* config/arm/vfp.md (fma,fmsub,fnmsub,fnmadd): Change type
from fmac to ffma.
* config/arm/vfp11.md (vfp_farith): Use ffmas.
(vfp_fmul): Use ffmad.
On 01/25/13 18:22, Greta Yorsh wrote:
This patch updates the description of vmul, vdiv, vsqrt, vmla,vmls, vfma,
vfms operations for vfp and neon. It uses ffmas and ffmad type attribute
introduced by the previous patch.
gcc/
2013-01-03 Greta Yorsh
* config/arm/cortex-a7.md (cortex_a
On 01/25/13 18:23, Greta Yorsh wrote:
Add bypasses to forward the result of one MAC operation to the accumulator
of another MAC operation.
Towards this end, we add a new function arm_mac_accumulator_is_result to be
used as a guard for bypasses. Existing guard
arm_mac_accumulator_is_mul_result re
On 01/25/13 18:24, Greta Yorsh wrote:
Improve handling of call insns in cortex-a7 pipeline description, as
follows.
A call can dual-issue as a younger instruction but not as an older
instruction (from compiler's point of view). This patch adjusts the function
cortexa7_younger (used by the implem
On 01/25/13 18:25, Greta Yorsh wrote:
In cortex_a7_idiv, the use of cortex_a7_all reservation can be replaced by
cortex_a7_both, because all other reservations require at least one of
cortex_a7_ex1 or cortex_a7_ex2. Then, remove unused reservation units
cortex_a7_neon and cortex_a7_all.
gcc/
20
ifies that these instructions only have the scalar
forms (Section 8.8.318)
vfnm<>.f64 Dd, Dn, Dm
vfnm<>.f32 Sd, Sn, Sm
instructions.
I have now reverted this patch as obvious.
Sorry about the inconvenience caused.
regards
Ramana
Thank You,
Amol Pise
On Mon, Jan 28, 2013 a
Here is a new version of my patch, with the cleanup you requested.
2012-12-18 Christophe Lyon
gcc/
* config/arm/arm-protos.h (tune_params): Add
prefer_neon_for_64bits field.
* config/arm/arm.c (prefer_neon_for_64bits): New variable.
(arm_slowmu
es that I'm aware of.
Thanks for bringing this up. It looks like it slipped through the cracks
when I left Linaro.
regards
Ramana
On Tue, Jul 24, 2012 at 8:09 PM, Ramana Radhakrishnan
wrote:
Hi ,
While testing my neon intrinsics work with some testcases
that I was writing up,
On 12/18/12 13:33, Kyrylo Tkachov wrote:
Hi all,
This patch does some refactoring by moving the definitions of the NEON
builtins to a separate file (arm_neon_builtins.def) and includes that when
initialising the neon_builtin_data array and also during
the definition of enum arm_builtins (with ap
On 12/18/12 13:33, Kyrylo Tkachov wrote:
Hi all,
This patch adds support for the vectorisation of the rounding functions:
floorf, ceilf, truncf, roundf. These can be implemented using the ARMv8 NEON
instructions: vrintm, vrintp, vrintz, vrinta.
This is done by defining the TARGET_VECTORIZE_BUILT
On 01/30/13 09:24, Kyrylo Tkachov wrote:
Hi all,
This patch uses the new ARMv8 AArch32 vsel instruction to implement
conditional moves of floating point numbers.
For example, an instruction of the form:
vsel.f32 s0, s1, s2
means
s0 := cond ? s1 : s2
This can be useful, among oth
On Fri, Feb 15, 2013 at 10:40 PM, Seth LaForge wrote:
> gcc 4.7.2 generates incorrect code for big-endian ARM VFP processors
> when storing a local double to a packed memory location, as described
> in bug 56351.
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56351
>
> A fix has been submitted to t
>> What do other people do?
>
> We usually can cut and paste the one line and run the one case by hand. Test
> cases that don't fall into this category, well, suck, I mean, are more
> annoying.
>
These days I find contrib/repro_fail
file.log.useful to rebuild the failing test(s).
regards
Rama
On 28 September 2011 09:48, Joey Ye wrote:
> 2011-09-28 Joey Ye
>
> * gcc.target/arm/pr42575.c: Remove architecture option.
OK.
FTR - Joey had checked that it ran ok with an optional march=armv5te
in RUNTESTFLAGS .
Ramana
Hi Julian,
There are a couple of minor formatting nits.
>+static int
>+arm_movmemqi_unaligned (rtx *operands)
>+ /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
>+ size of code if optimizing for size. We'll use ldm/stm if
>src_aligned
>+ or ds
orrow A.M. UK time.
cheers
Ramana
2011-10-19 Ramana Radhakrishnan
PR target/50106
* config/arm/arm.c (thumb_unexpanded_epilogue): Handle return
reg size from 1-3.
Index: gcc/config/arm/arm.c
===
--- gcc/confi
On 19 October 2011 20:38, Nathan Froyd wrote:
> On 10/19/2011 3:27 PM, Ramana Radhakrishnan wrote:
>>
>> Index: gcc/config/arm/arm.c
>> - live_regs_mask |= extra_mask<< (size / UNITS_PER_WORD);
>> + live_regs_mask |= extra_mask<< ((size + 3
On 20 October 2011 08:42, Xinyu Qi wrote:
> Ping
>
> http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01106.html
> Index: gcc/config/arm/marvell-f-iwmmxt.md
> ===
> --- gcc/config/arm/marvell-f-iwmmxt.md(revision 0)
> +++ gcc/conf
On 20 October 2011 08:35, Xinyu Qi wrote:
> Ping
>
> http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01100.html
>
> * config/arm/arm.c (arm_option_override): Enable use of iWMMXt with
> VFP.
> Disable use of iwMMXt and Neon.
> (arm_expand_binop_builtin): Accept VOIDmode op.
>
> Otherwise the generic parts of the patch look good.
> Please get separate approval for the arm portions of the patch.
Is it just me or has no one else seen this patch on the archives at
gcc-patches@. ?
Ramana
Hi,
Some time back Michael pointed out that the ARM backend doesn't generate
vcvt.f32.s where you have a conversion from fixed to floating point
as in the example below. It should also be possible to generate the vector forms
of this which will be the subject of a follow-up patch .
I've chosen to
Hi Sameera,
The comment about REG_FRAME_RELATED_EXPR vs REG_CFA_RESTORE from one
of your later patches
applies here as well.
>diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>index 3162b30..f86a3e6 100644
>--- a/gcc/config/arm/arm.c
>+++ b/gcc/config/arm/arm.c
>@@ -8754,6 +8754,140 @@ ne
> 2011-10-11 Sameera Deshpande
>
>
> * config/arm/arm-cores.def (cortex_a15): Update.
> * config/arm/arm-protos.h (struct tune_params): Add new field...
> (arm_gen_ldrd_strd): ... this.
> * config/arm/arm.c (arm_slowmul_tune): Add
> arm_gen_ldrd_strd field s
On 11 October 2011 10:27, Sameera Deshpande wrote:
> Hi!
>
> This patch generates STRD instruction instead of PUSH in thumb2 mode for
> A15.
>
> For optimize_size, original prologue is generated for A15.
> The work involves defining new functions, predicates and patterns.
>
> +/* Generate and em
>+/* STRD in ARM mode needs consecutive registers to be stored. This function
>+ keeps accumulating non-consecutive registers until first consecutive
>register
numchar > 80.
>+ pair is found. It then generates multi-reg PUSH for all accumulated
>+ registers, and then generates STRD with
> 2011-10-11 Sameera Deshpande
>
>
> * config/arm/arm.c (arm_emit_ldrd_pop): New static function.
> (arm_expand_epilogue): Update.
> * config/arm/ldmstm.md (arm_ldrd_base): New pattern.
> (arm_ldr_with_update): Likewise.
rth's comment about REG_CFA_RESTORE applies
On 24 October 2011 15:02, Joseph S. Myers wrote:
> On Mon, 24 Oct 2011, Dmitry Plotnikov wrote:
>
>> * neon.md (floatv2siv2sf2): New.
>> (floatunsv2siv2sf2): New.
>
>> (floatv4siv4sf2): New.
>> (floatunsv4siv4sf2): New.
>
> My undertstanding is that the NEON conversions of in
.
>
> Ok for mainline?
This is OK.
Ramana
> /home/sh/archive/gcc-4.7-20111029/libgcc/unwind-dw2.c: In function
> 'init_dwarf_reg_size_table':
> /home/sh/archive/gcc-4.7-20111029/libgcc/unwind-dw2.c:1482:39: internal
> compiler error: in arm_dbx_register_number, at config/arm/arm.c:23536
Your original post in this thread suggested that you
>> (Note that while the patch contains changes to common code, those
>> should be no-ops for all targets that do not implement the new hook.)
>
> I'll defer the decision to the target maintainers.
I'd rather have this consistent across all maintained release branches
today than to leave this for
On 3 August 2012 16:00, Richard Earnshaw wrote:
> On 30/07/12 12:43, Ramana Radhakrishnan wrote:
>>> Patch 1 fixes up the vaba and vabal patterns to use a canonical RTL
>>> form with the first operand to the plus being the more complex one.
>>
>> This patch canon
>
> I guess people will complain soon enough if this causes horrible performance
> regressions in vectorized code.
Not having looked at your patch in great detail,. surely what we don't
want is a situation where 2 constant permutations are converted into
one generic permute. Based on a quick read
On 13 August 2012 14:21, Marc Glisse wrote:
> On Mon, 13 Aug 2012, Richard Guenther wrote:
>
>> On Mon, Aug 13, 2012 at 3:12 PM, Ramana Radhakrishnan
>> wrote:
>>>>
>>>>
>>>> I guess people will complain soon enough if this causes horribl
On 13 August 2012 14:54, Jakub Jelinek wrote:
> On Mon, Aug 13, 2012 at 03:45:00PM +0200, Marc Glisse wrote:
>> On Mon, 13 Aug 2012, Jakub Jelinek wrote:
>>
>> >On Mon, Aug 13, 2012 at 03:13:26PM +0200, Richard Guenther wrote:
>> >>The patch does not do that. It merely assumes that the target kno
Ramana Radhakrishnan
PR target/54212
* config/arm/neon.md (vec_set_internal VD,VQ): Do not
mark as predicable. Adjust asm template.
(vec_setv2di_internal): Likewise.
(vec_extract VD, VQ): Likewise.
(vec_extractv2di): Likewise
[It looks like I missed hitting the send button on this response]
>
> Seems to be one instruction shorter at least ;-) Yes, there can be much
> worse regressions than that because of the patch (like 40 instructions
> instead of 4, in the x86 backend).
If this is replacing 4 instructions with 40 i
On 15 August 2012 13:07, Jakub Jelinek wrote:
> On Wed, Aug 15, 2012 at 01:46:05PM +0200, Richard Guenther wrote:
>> Well, we're waiting for someone to break the tie ... I'd go with the original
>> patch, improving the backends where necessary.
>
> E.g. i?86/x86_64 with just plain -msse2 has only
On 07/24/12 13:27, Julian Brown wrote:
On Fri, 20 Jul 2012 11:15:27 +0100
Julian Brown wrote:
Anyway: this revised version of the patch removes the strange libgcc
Makefile-fragment changes, the equivalent of which have since been
incorporated into mainline GCC now anyway, so the patch is somew
ith a number of handwritten tests and observed size
of the memory accesses look sane.
Applied on trunk and will wait for a few days before backporting to 4.7
branch.
regards,
Ramana
2012-08-29 Ramana Radhakrishnan
Richard Earnshaw
PR target/54252
* c
On 08/31/12 13:49, Greta Yorsh wrote:
Ping
http://gcc.gnu.org/ml/gcc-patches/2012-07/msg01026.html
From: Greta Yorsh [greta.yo...@arm.com]
Sent: Friday, July 20, 2012 7:33 PM
To: GCC Patches
Cc: Richard Earnshaw; Ramana Radhakrishnan
Subject: [Patch
On 08/31/12 13:50, Greta Yorsh wrote:
Ping
http://gcc.gnu.org/ml/gcc-patches/2012-07/msg01025.html
From: Greta Yorsh [greta.yo...@arm.com]
Sent: Friday, July 20, 2012 7:28 PM
To: GCC Patches
Cc: Richard Earnshaw; Ramana Radhakrishnan
Subject: [Patch,ARM
On 09/03/12 09:59, Christophe Lyon wrote:
On 31 August 2012 17:59, Richard Henderson wrote:
On 2012-08-31 07:25, Christophe Lyon wrote:
+ offset = gen_rtx_CONST_INT (VOIDmode, location);
Never call gen_rtx_CONST_INT directly. Use GEN_INT.
Here is an updated patch with that small change.
On 09/03/12 16:28, Christophe Lyon wrote:
Hi,
As discussed in
http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00077.html, this patch is
a cleanup pass to replace calls to gen_rtx_CONST_INT by GEN_INT.
Tested on arm-linuxeabi with qemu.
Ok. Thanks for doing this so quickly.
Thanks,
Ramana
I ran regression test with/without Os for cortex-m0 and everything is ok.
Ok for trunk and 4.7/4.6 release branches?
OK for trunk.
Ok to backport if no release manager objects in 24 hours and if it tests
without regressions there.
Thanks,
Ramana
Applied on trunk and will wait for a few days before backporting to 4.7
branch.
Applied now to 4.7 branch .
regards,
ramana
ve with no regressions.
Committed.
regards,
Ramana
2012-09-11 Ramana Radhakrishnan
Matthew Gretton-Dann
* config/arm/neon.md (fma4): New pattern.
(*fmsub4): Likewise.
* doc/sourcebuild.texi (arm_neon_v2_ok, arm_neon_v2_hw): Document it.
2012-09-11 Ramana Rad
realized
another issue with the command line and committed this as obvious after
checking that the documentation built fine.
Thanks and apologies for the slip-up.
I've changed machines recently and somethings not ok in this new setup.
regards,
Ramana
2012-09-11 Ramana Radhakrishnan
On 09/13/12 09:12, Kyrylo Tkachov wrote:
Can I get this commited please?
Now applied with a minor tweak to the changelog.
2012-09-12 Kyrylo Tkachov
* c-c++-common/pr51712.c: Handle for short-enum targets.
Thanks,
ramana
On 29 May 2012 10:07, Yi-Hsiu Hsu wrote:
> Hi,
>
> This patch maintains Marvell PJ4 cores pipeline description.
> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>
> * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
> * config/arm/arm.c (ar
Hi,
This patch allows propagation of vector constants into VEC_PERM_EXPRs
in lower_vec_perm, motivation explained in
http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00615.html
Bootstrapped and regression tested on gcc110.fsffrance.org .
Ok ?
regards,
Ramana
* tree-vect-generic.c (lower_vec_per
On 15 June 2012 01:44, Jason Merrill wrote:
> OK.
Thanks, now committed with the only change being that the PR number is
now referenced in the Changelog.
Ramana
> I just noticed this part. Rereading my comment in
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51033#c22
I haven't been able to make it break with -std=c++11 . Is there
something I'm missing here ?
>
> it seems like this may break things with -std=c++11 and you used the old
> version from co
On 15 June 2012 18:18, Marc Glisse wrote:
> On Fri, 15 Jun 2012, Ramana Radhakrishnan wrote:
>
>>> I just noticed this part. Rereading my comment in
>>>
>>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51033#c22
>>
>>
>> I haven't been able
On 15 June 2012 20:04, Marc Glisse wrote:
> On Fri, 15 Jun 2012, Ramana Radhakrishnan wrote:
>
>> On 15 June 2012 18:18, Marc Glisse wrote:
>>>
>>> On Fri, 15 Jun 2012, Ramana Radhakrishnan wrote:
>>>
>>>>> I just noticed this part. Rereading
Hi,
This patch following on from the fix for turning on __builtin_shuffle
for c++ , enables folding of vec_perm_exprs in the front-end for
constexpr and constructor style values. I was originally going to go
with Marc's patch but then took a look at what it would take to
support this properly whi
On 15 June 2012 20:04, Marc Glisse wrote:
> On Fri, 15 Jun 2012, Ramana Radhakrishnan wrote:
>
>> On 15 June 2012 18:18, Marc Glisse wrote:
>>>
>>> On Fri, 15 Jun 2012, Ramana Radhakrishnan wrote:
>>>
>>>>> I just noticed this part. Rereading
hes one for the prototype cleanup and
the other for the vdup case ) ?
regards,
Ramana
2012-06-20 Ramana Radhakrishnan
* config/arm/arm.c (arm_vector_alignment_reachable): Fix declaration.
(arm_builtin_support_vector_misalignment): Likewise.
(arm_preferred_rename_c
On 10 April 2012 10:11, Ramana Radhakrishnan
wrote:
>>> The patch with correct configure output is ok.
>>
>> Thanks - this is what I committed.
>
> Is this something that can be considered for backporting to release
> branches ? This patch technically doesn't fi
On 18 June 2012 14:04, Ramana Radhakrishnan
wrote:
> Hi,
>
> This patch following on from the fix for turning on __builtin_shuffle
> for c++ , enables folding of vec_perm_exprs in the front-end for
> constexpr and constructor style values. I was originally going to go
> wit
On 20 June 2012 12:29, Julian Brown wrote:
> On Wed, 20 Jun 2012 11:56:39 +0100
> Ramana Radhakrishnan wrote:
>
>> Hi,
>>
>> This patch helps use the __builtin_shuffle intrinsics to implement the
>> Neon permute intrinsics following on from Julian's and my
On 20 June 2012 14:37, Christophe Lyon wrote:
> On 06.06.2012 11:00, Ramana Radhakrishnan wrote:
>>
>> Ok with those changes. Ramana .
>
>
> Hi Ramana,
>
> How about this version?
>
> Christophe.
>
OK -
This should also go into the release branches a
On 20 June 2012 03:53, Yi-Hsiu Hsu wrote:
> marvell-pj4 is added to BE8_LINK_SPEC.
>
> Modified patch is attached.
Missing a modified changelog entry.
Ramana
>
> Thanks!
>
> B.R.
> Yi-Hsiu, Hsu
>
> -Original Message-
> From: Ramana Radhakrishnan [mailt
On 22 June 2012 18:58, Ramana Radhakrishnan
wrote:
> On 20 June 2012 14:37, Christophe Lyon wrote:
>> On 06.06.2012 11:00, Ramana Radhakrishnan wrote:
>>>
>>> Ok with those changes. Ramana .
>>
>>
>> Hi Ramana,
>>
>> How about this versio
On 25 June 2012 04:32, Jason Merrill wrote:
> On 06/18/2012 09:04 AM, Ramana Radhakrishnan wrote:
>>
>> + location_t loc = EXPR_LOC_OR_HERE (t);
>
>
> We should only use EXPR_LOC_OR_HERE for diagnostics. For a location to use
> in building other expressions, use EXP
On 27 June 2012 15:58, Dmitry Melnik wrote:
> Hi,
>
> We'd like to note about CodeSourcery's patch for ARM backend, from which GCC
> mainline can gain 4% on SPEC2K INT:
> http://cgit.openembedded.org/openembedded/plain/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch
> (also the patch is att
On 8 June 2012 10:12, Carrot Wei wrote:
> Hi
>
> In rtl expression, substract a constant c is expressed as add a value -c, so
> it
> is alse processed by adddi3, and I extend it more to handle a subtraction of
> 64bit constant. I created an insn pattern arm_subdi3_immediate to specifically
> repr
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