_opt_masks[] =
> >{ "float128-hardware", OPTION_MASK_FLOAT128_HW,false, true },
> >{ "fprnd", OPTION_MASK_FPRND, false,
> > true },
> >{ "power10", OPTION_MASK_POWER1
On Thu, Jan 25, 2024 at 05:28:49PM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> on 2024/1/6 07:38, Michael Meissner wrote:
> > The MMA subsystem added the notion of accumulator registers as an optional
> > feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlap
> + [(set (match_operand:XO 0 "dmr_operand" "=wD")
> > + (unspec:XO [(const_int 0)]
> > + UNSPECV_MMA_XXSETACCZ))]
> > + "TARGET_DENSE_MATH"
> > + "dmsetdmrz %0"
> > + [(set_attr "type" "mma")])
> > +
> > (define_insn "mma_"
> > - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
> > - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
> > - (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
> > + [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
> > + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
> > + (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
> > MMA_VV))]
> >"TARGET_MMA"
> >" %A0,%x1,%x2"
> > - [(set_attr "type" "mma")])
> > + [(set_attr "type" "mma")
> > + (set_attr "isa" "dm,not_dm,not_dm")])
>
> Like what's suggested in previous patches, s/not_dm/nodm/
Ok.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Wed, Feb 07, 2024 at 05:21:10PM +0800, Kewen.Lin wrote:
> on 2024/2/6 14:01, Michael Meissner wrote:
> Sorry for the possible confusion here, the "tune_proc" that I referred to is
> the variable in the above else branch:
>
>enum processor_type tune
uot;
> + "@
> + pmdm %A0,%x1,%x2,%3,%4,%5
> + pm %A0,%x1,%x2,%3,%4,%5
> + pm %A0,%x1,%x2,%3,%4,%5"
>
> and
>
> - define_insn "mma_"
> + define_insn "mma_pm"
>
> (or updating its use in corresponding bif expander field)
Yes I can do that.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
e an issue since rs6000_setup_reg_addr_masks won't
allow reg+reg addresses for TDOmode.
> >>> #ifdef TARGET_REGNAMES
> >>> @@ -1250,6 +1255,8 @@ static const char alt_reg_names[][8] =
> >>>"%cr0", "%cr1", "%cr2", "%cr3&qu
On Mon, Feb 05, 2024 at 11:58:31AM +0800, Kewen.Lin wrote:
> Hi Mike,
I will comment on about 1/2 of the things, and come back with the other
comments.
> on 2024/1/6 07:42, Michael Meissner wrote:
> > This patch is a prelimianry patch to add the full 1,024 bit dense math
> &g
there were no regressions. Even though these patches have been posted for 1.5
years now, I assume they have to wait for GCC 15. But I will immediately want
to back port these to GCC 14.1 after they go into GCC 15.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss
-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option
bits for -mcpu=future.
(POWERPC_MASKS): Add -mfuture mask.
(future cpu): Add -mcpu=future.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New processor
This patch prints that -mcpu=future was selected if you use the debugging
switch -mdebug=reg.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_opt_masks): Add entry to print out
-mfuture in the isa flags.
---
gcc/config/rs6000/rs6000.cc | 1 +
1 file
This patch defines _ARCH_PWR_FUTURE if -mcpu=future was used.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
---
gcc/config/rs6000/rs6000-c.cc | 2 ++
1 file changed, 2 insertions(+)
diff
This patch passes -mfuture to the assembler if the user used -mcpu=future.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000.h (ASM_CPU_SPEC): If -mcpu=future, pass -mfuture
to the assembler.
---
gcc/config/rs6000/rs6000.h | 1 +
1 file changed, 1 insertion(+)
diff
Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Make
-mtune=future become -mtune=power10.
---
gcc/config/rs6000/rs6000.cc | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc
This patch uses the .machine directive to tell the assembler to use any
possible future instructions.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Output .machine
future if -mcpu=future.
---
gcc/config/rs6000/rs6000.cc | 2 ++
1
.
Previously the -mblock-ops-vector-pair switch was not set in POWERPC_MASKS.
This means the option was not reset if the cpu was changed via target
attributes or targt pragmas. I added this mask to POWERPC_MASKS since the
option is set via -mcpu=future.
2024-02-14 Michael Meissner
gcc
On Tue, Feb 20, 2024 at 06:35:34PM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> Sorry for late reply (just back from vacation).
>
> on 2024/2/8 03:58, Michael Meissner wrote:
> > On Wed, Feb 07, 2024 at 05:21:10PM +0800, Kewen.Lin wrote:
> >> on 2024/2/6 14:01, Michael
On Tue, Jan 09, 2024 at 04:35:22PM -0600, Peter Bergner wrote:
> On 1/5/24 4:18 PM, Michael Meissner wrote:
> > @@ -14504,13 +14504,17 @@ print_operand (FILE *file, rtx x, int code)
> > print_operand (file, x, 0);
> >return;
> >
> > +case '
adds %S that acts like %x, except that it adds 1 to the
register number.
I have tested this on power10 and power9 little endian systems and on a power9
big endian system. There were no regressions in the patch. Can I apply it to
the trunk?
It would be nice if I could apply it to the open branches.
,%x2\n\txvadddp %S0,%S1,%S2"
> : "=wa" (p)
> : "wa" (q), "wa" (r));
> ptr[2] = p;
> }
>
> /* { dg-final { scan-assembler-times {\mxvadddp 10,42,44\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvadddp 11,43,45\M} 1 } } */
a REG, or a
size*number added to a memory address if it is a MEM.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Ping
| Date: Fri, 5 Jan 2024 18:35:37 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 1/6] Add -mcpu=future
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641961.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss
Ping
| Date: Fri, 5 Jan 2024 18:37:17 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 2/6] PowerPC: Make -mcpu=future enable
-mblock-ops-vector-pair.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641962.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping
| Date: Fri, 5 Jan 2024 18:38:23 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 3/6] PowerPC: Add support for accumulators in DMR
registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641963.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping
| Date: Fri, 5 Jan 2024 18:39:55 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641964.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping
| Date: Fri, 5 Jan 2024 18:40:58 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 5/6] PowerPC: Switch to dense math names for all MMA
operations.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641965.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping
| Date: Fri, 5 Jan 2024 18:42:02 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641966.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping
| Date: Thu, 11 Jan 2024 12:29:23 -0500
| From: Michael Meissner
| Subject: [PATCH, V2] PR target/112886, Add %S to print_operand for vector
pair support.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642727.html
--
Michael Meissner, IBM
PO Box 98, Ayer
526.blender_r4 more stack spills, but 149 LXVPs
One benchmark actually generated fewer stack spills as well as generating
LXVPs.
538.imagick_r 11 fewer stack spills, and 26 LXVPs
Note, these are changes to the static instructions generated. It does not
evaluate
wer10 and power9 little endian systems and on a power9
big endian system. There were no regressions in the patch. Can I apply it to
the trunk?
It would be nice if I could apply it to the open branches. Can I backport it
after a burn-in period?
2024-01-04 Michael Meissner
gcc/
P
e are preliminary patches for a potential future machine. Things
will likely change in terms of implementation and usage over time.
Originally these patches were submitted in November 2022:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605581.html
--
Michael Meissner, IBM
PO Box 98,
ill be set for power10.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
__ARCH_PWR_FUTURE__ if -mcpu=future.
and store vector pair instructions for memory options by default. This patch
re-enables generating these instructions if -mcpu=future is used.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc
correspondence.
It is possible that the mangling for DMRs and the GDB register numbers may
change in the future.
2024-01-05 Michael Meissner
gcc/
* config/rs6000/constraints.md (wD constraint): New constraint.
* config/rs6000/mma.md (UNSPEC_DM_ASSEMBLE_ACC): New unspec.
endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/mma.md (mma_): New define_expand to handle
mma_ for dense math and non dense math.
(mma_ insn): Restrict to non dense math.
(mma_xxsetaccz): Convert to
both little and big endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/mma.md (vvi4i4i8_dm): New int attribute.
(avvi4i4i8_dm): Likewise.
(vvi4i4i2_dm): Likewise.
(avvi4i4i2_dm): Likewise.
(vvi4i4_dm
endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(
:REG_DEAD (reg:V2DF 117 [ _6 ])
(nil
Now in theory you could get ride of the UNSPEC_VSX_ASSEMBLE also using SUBREG's.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
I discovered a short coming in the patch I proposed to add
-mno-load-vector-pair and -mno-store-vector-pair tuning options. I will submit
a new patch shortly.
| Date: Fri, 13 Oct 2023 19:41:13 -0400
| From: Michael Meissner
| Subject: [PATCH] Power10: Add options to disable load and store
master
branch?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair
and
-mno-store-vector-pair.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for
-mload-vector-pair and
reductions that should be done.
I have built and tested these patches on:
* A little endian power10 server using --with-cpu=power10
* A little endian power9 server using --with-cpu=power9
* A big endian power9 server using --with-cpu=power9.
Can I check these patches into the ma
--with-cpu=power9
* A big endian power9 server using --with-cpu=power9.
Can I check this patch into the master branch?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/rs6000-builtins.def (__builtin_vpair_f32_*): Add vector
pair built-in functions for float
after the preceeding patches have
been checked in?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/predicates.md (mma_assemble_input_operand): Allow any
16-byte vector, not just V16QImode.
* config/rs6000/rs6000-builtins.def (__builtin_vpair_zero): New vector
power10 server using --with-cpu=power10
* A little endian power9 server using --with-cpu=power9
* A big endian power9 server using --with-cpu=power9.
Can I check this patch into the master branch after the preceeding patches have
been checked in?
2023-11-08 Michael Meissner
gcc
* A big endian power9 server using --with-cpu=power9.
Can I check this patch into the master branch after the preceeding patch is
checked in?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/rs6000-builtins.def (__builtin_vpair_i8*): Add built-in
functions for integer
ements the floating point arithmetic operations.
The third patch implements the integer operations.
The fourth patch provides new tests to test these features.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
h little endian power9 and big
endian power9 systems, and there are no regressions. Can I check these
patches into the master branch?
2023-11-19 Michael Meissner
gcc/
* config/rs6000/constraint.md (eV): New constraint.
* config/rs6000/predicates.md (cons_0_to_31_operand)
d run the tests on both little endian power9 and big
endian power9 systems, and there are no regressions. Can I check these
patches into the master branch?
2023-11-19 Michael Meissner
gcc/
* config/rs6000/constraint.md (eV): New constraint.
* config/rs6000/predicates.md (cons_
erand" "=wa,wa")
+ (minus:VPAIR_FP
+(mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+(match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32
+ && flag_fp_contract_mode == FP_CONTRACT_FAST"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (neg:VPAIR_FP
+ (match_dup 3]
+{
+}
+ [(set_attr "length" "8")
+ (set_attr "type" "vecfloat")])
+
+;; Optimize vector pair -((a * b) + c) into -fma (a, b, c)
+(define_insn_and_split "*nfma_fpcontract_4"
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+(plus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32
+ && flag_fp_contract_mode == FP_CONTRACT_FAST"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (neg:VPAIR_FP
+(fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (match_dup 3]
+{
+}
+ [(set_attr "length" "8")])
+
+;; Optimize vector pair -((a * b) - c) into -fma (a, b, -c)
+(define_insn_and_split "*nfms_fpcontract_4"
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+(minus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32
+ && flag_fp_contract_mode == FP_CONTRACT_FAST"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (neg:VPAIR_FP
+(fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (neg:VPAIR_FP
+ (match_dup 3)]
+{
+}
+ [(set_attr "length" "8")
+ (set_attr "type" "vecfloat")])
+
--
2.41.0
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
perand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+ (not:VPAIR_INT
+(and:VPAIR_INT
+ (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"]
+ "TARGET_MMA
px?\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltib\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
--
2.41.0
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
he
behavior on actual code.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
did the
functions as part of another change (rewriting built-ins maybe)
But prefixed and pc-rel cannot be added willy-nilly with -mcpu=power10 due to
conforming with other parts of the system (assembler, linker, ABIs, etc.).
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Fri, Nov 24, 2023 at 05:41:02PM +0800, Kewen.Lin wrote:
> on 2023/11/20 16:56, Michael Meissner wrote:
> > On Mon, Nov 20, 2023 at 08:24:35AM +0100, Richard Biener wrote:
> >> I wouldn't expose the "fake" larger modes to the vectorizer but rather
> >> a
On Fri, Nov 24, 2023 at 05:31:20PM +0800, Kewen.Lin wrote:
> Hi Ajit,
>
> Don't forget to CC David (CC-ed) :), some comments are inlined below.
>
> on 2023/10/8 03:04, Ajit Agarwal wrote:
> > Hello All:
> >
> > This patch add new pass to replace contiguous addresses vector load lxv
> > with mma
that this optimization will match less often.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Tue, Nov 28, 2023 at 05:44:43PM +0800, Kewen.Lin wrote:
> on 2023/11/28 15:05, Michael Meissner wrote:
> > I tried using this patch to compare with the vector size attribute patch I
> > posted. I could not build it as a cross compiler on my x86_64 because the
> > assemble
.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
trunk?
2024-07-10 Michael Meissner
libgfortran/
PR target/115800
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h (GFC_REAL_17): Add check for
trunk?
2024-07-10 Michael Meissner
libstdc++-v3/
PR target/115800
* configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC
systems without VSX.
* configure: Regenerate.
* numeric_traits.h: Don't enable IEEE 128-bit on PowerPC syste
the compiler on both little endian and big endian systems.
There were no regressions in either case. Can I check these patches into the
GCC trunk? After a waiting period assuming there are no issues, can I check
these patches into the GCC 14 branch?
--
Michael Meissner, IBM
PO Box 98, Ayer
the __builtin_cpu_is built-in
function.
2024-07-02 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
*
endian and big endian systems.
Can I check these changes into the GCC 15 trunk. After a waiting period, can I
check these patches into the GCC 14 branch?
2024-07-10 Michael Meissner
gcc/
* config/rs6000/power10.md (all reservations): Add power11 as an
alternative to power10
bootstrapped these patches on both little endian and big endian systems.
There were no regressions. Can I check these patches into the GCC 15 trunk?
After a waiting period to make sure there are no errors, can I check these
patches into the GCC 14 branch?
2024-07-10 Michael Meissner
gcc/testsuite
not enable float128 on those systems.
Can I check these patches into the trunk assuming the original bugzilla author
says they fix the problem?
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
r float128 in glibc and the GCC
compiler does not enable float128 on those systems.
Can I check these patches into the trunk assuming the original bugzilla author
says they fix the problem?
2024-07-18 Michael Meissner
libgcc/
PR target/113652
* config.host (powerpc*-*-linux*): Do
k assuming the original bugzilla author
says they fix the problem?
2024-07-18 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* gcc.target/powerpc/abs128-1.c: Remove adding -mvsx, -mfloat128, and
-mfloat128-hardware options to float128 test. Ad
On Thu, Jul 18, 2024 at 08:08:44AM -0500, Segher Boessenkool wrote:
> Hi!
>
> [ I reviewed this together with Ke Wen. All blame should go to me, all
> praise to him. ]
>
> On Wed, Jul 10, 2024 at 01:34:26PM -0400, Michael Meissner wrote:
> > [This is a repost of the Ju
option.
I have bootstrapped the compiler on both little endian and big endian systems.
There were no regressions in either case. Can I check these patches into the
GCC trunk? After a waiting period assuming there are no issues, can I check
these patches into the GCC 14 branch?
--
Michael Meissner
patches into the GCC 14 branch?
2024-06-03 Michael Meissner
gcc/
* config/rs6000/power10.md (all reservations): Add power11 as an
alternative to power10.
---
gcc/config/rs6000/power10.md | 144 +--
1 file changed, 72 insertions(+), 72 deletions
I have bootstrapped these patches on both little endian and big endian systems.
There were no regressions. Can I check these patches into the GCC 15 trunk?
If there are no issues after a waiting period, can I check these patches into
the GCC 14 branch?
2024-06-03 Michael Meissner
gcc/
endian systems.
There were no regressions. Can I check these patches into the GCC 15 trunk?
After a waiting period to make sure there are no errors, can I check these
patches into the GCC 14 branch?
2024-06-03 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test
into the GCC 15 trunk.
[gcc]
2024-08-12 Michael Meissner
PR target/89213
* config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec.
(VSHIFT_MODE): New mode iterator.
(vshift_code): New code iterator.
(vshift_attr): New code attribute
://gcc.gnu.org/pipermail/gcc-patches/2024-June/653553.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
ot;.machine power11", the testsuite will skip these tests.
I just built a GCC using the system assembler instead of a recent binutils that
includes ".machine power11" support, and the 3 power11 tests are not done due
to them being UNSUPPORTED.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
he
patches installed compared to the compiler before installing the patches.
Can I install these nine patches on the GCC 15 trunk?
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
trunk?
2024-08-01 Michael Meissner
gcc/
* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an
I ran
this test for all supported combinations of -mcpu, big/little endian, and 32/64
bit support. Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Mi
32/64
bit support. Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Michael Meissner
gcc/
* config/rs6000/rs6000.cc
compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Michael Meissner
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER5 instead of TARGET_POPCNTB.
* config/rs6000/rs6000.h
the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-09-01 Michael Meissner
* config/rs6000/rs6000.cc (report_architecture_mismatch): Use
TARGET_POWER5X instead of TARGET_FPRND.
* config/rs6000/rs6000.md (fmod3): Use
compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Michael Meissner
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.h (TARGET_FCFID
compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Michael Meissner
* config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
TARGET_POWER7.
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported
combinations of -mcpu, big/little endian, and 32/64
bit support. Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Michael Meissner
* config/rs6000
installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-08-01 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
when we need to add VSX support. Add test for adding cpu=power7 no-vsx
to generate only
ck in
this patch to the master branch for GCC 15?
2024-09-16 Michael Meissner
gcc/
PR target/89213
* config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec.
(VSHIFT_MODE): New mode iterator.
(vshift_code): New code iterator.
(vshift_attr): New
endian and big endian PowerPC
servers, and there was no regression in the code. Can I apply this patch to
the master trunk for GCC 15?
2024-09-16 Michael Meissner
gcc/
* config/rs6000/vsx.md (vsx_splat_extract_): New insn.
gcc/testsuite/
* gcc.target/powerpc/builtins-1.c
In doing make check, I noticed that I'm now getting warnings from one of the
tests that I wrote for power8 support (pr57744). I applied this patch as
obvious:
2013-08-22 Michael Meissner
* gcc.target/powerpc/pr57744.c: Declare abort.
Index: gcc/testsuite/gcc.target/powerpc/pr57
e ChangeLog parts in the message, and if it is more than a few
lines, the patch (without the ChangeLog bits) should be a separate attachment.
That allows us to apply the patch without an error.
I just got back from vacation, and noticed the powerpc linux compiler no longer
builds, and I've bee
options to enable paired floating point support.
2011-04-01 Andrew Pinski
Michael Meissner
PR target/48262
* config/rs6000/vector.md (movmisalign): Allow for memory
operands, as per the specifications.
* config/rs6000/altivec.md (vec_extract_evenv4si
and altivec disabled for 64/32-bit
cell 64/32-bit
e5500, e6500 64/32-bit
G4 32-bit
G5 64/32-bit
linuxpaired 32-bit
linuxspe 32-bit
2013-09-20 Michael Meissner
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new
This patch is an infrastructure patch that combines the 3 reload helper
function arrays into a single array of structures. All machines generate the
same code with this patch (and no regressions were found in bootstrap/make
check). Is it ok to apply?
2013-09-23 Michael Meissner
bootstrap test and
make check test. I tested all of the targets I tested previously (power4-8,
G4/G5, SPE, cell, e5500/e5600, and paired floating point), and all machines
generate the same code. Is it ok to install this patch?
[gcc]
2013-09-24 Michael Meissner
* config/rs6000/rs6000.c
the previous patch.
2013-09-26 Michael Meissner
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Don't
allow wv/wu constraints to be ALTIVEC_REGISTERS unless DF/SF can
occupy the Altivec registers.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King S
Just to be clear, I was only asking about the change in rs6000.c. The other
two changes (rs6000-builtins.def, rs6000.h) will be part of the next patch
set.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899
On Thu, Sep 26, 2013 at 06:56:37PM -0400, David Edelsohn wrote:
> On Thu, Sep 26, 2013 at 4:51 PM, Michael Meissner
> wrote:
> > I discovered that I was setting the wv/wu constraints incorrectly to
> > ALTIVEC_REGS, which leads to reload failures in some cases.
> >
>
On Thu, Sep 26, 2013 at 06:56:37PM -0400, David Edelsohn wrote:
> On Thu, Sep 26, 2013 at 4:51 PM, Michael Meissner
> wrote:
> > I discovered that I was setting the wv/wu constraints incorrectly to
> > ALTIVEC_REGS, which leads to reload failures in some cases.
> >
>
resubmit the first of
the infrastructure patches again, or commit both together.
2012-09-28 Michael Meissner
* config/rs6000/rs6000.c (rs6000_option_override_internal): If
-mcpu= is not specified and the compiler is not configured
using --with-cpu=, use the bits from the
dependent directories so we can avoid breakage like this.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
On Mon, Oct 01, 2012 at 02:02:26PM -0400, Michael Meissner wrote:
> Your change on September 30th, breaks the powerpc port because the
> REPORT_DETAILS value in the enumeration is no longer there, and the
> rs6000_density_test function was using that. Please in the future, when you
>
I tracked down some of the other code that previously used REPORT_DETAILS, and
MSG_NOTE is the new way to do the same thing. This bootstraps and no
unexpected errors occur during make check. Is it ok to install?
2012-10-01 Michael Meissner
* config/rs6000/rs6000.c (toplevel
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