On Sun, Feb 04, 2024 at 11:21:49AM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> > --- a/gcc/config/rs6000/mma.md
> > +++ b/gcc/config/rs6000/mma.md
> > @@ -559,190 +559,249 @@ (define_insn "*mma_disassemble_acc_dm"
> > "dmxxextfdmr256 %0,%1,2"
> > [(set_attr "type" "mma")])
> >
> > -(define_insn "mma_<acc>"
> > +;; MMA instructions that do not use their accumulators as an input, still
> > must
> > +;; not allow their vector operands to overlap the registers used by the
> > +;; accumulator. We enforce this by marking the output as early clobber.
> > If we
> > +;; have dense math, we don't need the whole prime/de-prime action, so just
> > make
> > +;; thse instructions be NOPs.
>
> typo: thse.
Ok.
> > +
> > +(define_expand "mma_<acc>"
> > + [(set (match_operand:XO 0 "register_operand")
> > + (unspec:XO [(match_operand:XO 1 "register_operand")]
>
> s/register_operand/accumulator_operand/?
Ok.
> > + MMA_ACC))]
> > + "TARGET_MMA"
> > +{
> > + if (TARGET_DENSE_MATH)
> > + {
> > + if (!rtx_equal_p (operands[0], operands[1]))
> > + emit_move_insn (operands[0], operands[1]);
> > + DONE;
> > + }
> > +
> > + /* Generate the prime/de-prime code. */
> > +})
> > +
> > +(define_insn "*mma_<acc>"
>
> May be better to name with "*mma_<acc>_nodm"?
Ok.
> > [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
> > (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
> > MMA_ACC))]
> > - "TARGET_MMA"
> > + "TARGET_MMA && !TARGET_DENSE_MATH"
>
> I found that "TARGET_MMA && !TARGET_DENSE_MATH" is used much (like changes in
> function
> rs6000_split_multireg_move in this patch and some places in previous
> patches), maybe we
> can introduce a macro named as TARGET_MMA_NODM short for it?
As I said in the message about the last patch, I added
TARGET_MMA_NO_DENSE_MATH.
> > "<acc> %A0"
> > [(set_attr "type" "mma")])
> >
> > ;; We can't have integer constants in XOmode so we wrap this in an
> > -;; UNSPEC_VOLATILE.
> > +;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't
> > need
> > +;; to disable optimization and we can do a normal UNSPEC.
> >
> > -(define_insn "mma_xxsetaccz"
> > - [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
> > +(define_expand "mma_xxsetaccz"
> > + [(set (match_operand:XO 0 "register_operand")
>
> s/register_operand/accumulator_operand/?
Ok.
> > (unspec_volatile:XO [(const_int 0)]
> > UNSPECV_MMA_XXSETACCZ))]
> > "TARGET_MMA"
> > +{
> > + if (TARGET_DENSE_MATH)
> > + {
> > + emit_insn (gen_mma_xxsetaccz_dm (operands[0]));
> > + DONE;
> > + }
> > +})
> > +
> > +(define_insn "*mma_xxsetaccz_vsx"
>
> s/vsx/nodm/
Ok.
> > + [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
> > + (unspec_volatile:XO [(const_int 0)]
> > + UNSPECV_MMA_XXSETACCZ))]
> > + "TARGET_MMA && !TARGET_DENSE_MATH"
> > "xxsetaccz %A0"
> > [(set_attr "type" "mma")])
> >
> > +
> > +(define_insn "mma_xxsetaccz_dm"
> > + [(set (match_operand:XO 0 "dmr_operand" "=wD")
> > + (unspec:XO [(const_int 0)]
> > + UNSPECV_MMA_XXSETACCZ))]
> > + "TARGET_DENSE_MATH"
> > + "dmsetdmrz %0"
> > + [(set_attr "type" "mma")])
> > +
> > (define_insn "mma_<vv>"
> > - [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
> > - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
> > - (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
> > + [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d")
> > + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
> > + (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
> > MMA_VV))]
> > "TARGET_MMA"
> > "<vv> %A0,%x1,%x2"
> > - [(set_attr "type" "mma")])
> > + [(set_attr "type" "mma")
> > + (set_attr "isa" "dm,not_dm,not_dm")])
>
> Like what's suggested in previous patches, s/not_dm/nodm/
Ok.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
