> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Tuesday, November 18, 2014 12:22 PM
> > To: Rozycki, Maciej
> > Cc: gcc-patches@gcc.gnu.org; Moore, Catherine; Eric Christopher
> > Subject: RE: [PATCH] MIP
> > From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
> >
> > On Tue, 18 Nov 2014, Andrew Bennett wrote:
> >
> > > Produces (for the atomic operation):
> > >
> > >.setnoat
> > > sync
> > > 1:
> > > ll $3,0($5)
> > > and $1,$3,$4
> > > bne
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
> 02268f3..368c6f0 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -12997,7 +12997,12 @@ mips_process_sync_loop (rtx_insn *insn, rtx
> *operands)
> This will sometimes be a delayed branch; see the w
> Ok to commit?
> gcc/
> * config/mips/mips.c (mips_process_sync_loop): Place a nop in the
> delay slot of the branch likely instruction.
With an updated ChangeLog to account for the changes in the callers, OK.
Matthew
+0100
Add MIPS .module directive
commit 351cdf24d223290b15fa991e5052ec9e9bd1e284
Author: Matthew Fortune
Date: Tue Jul 29 11:27:59 2014 +0100
[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions
I have updated the configure check for .module to check for both
.module and FPXX support.
Matthew Fortune writes:
> (I'm not sure if I need approval from someone else for MIPS specific
> top level 'configure' changes. I'm cautiously assuming I do for now.)
FWIW, MIPS maintainership covers all MIPS-specific code and documentation
(except for externally-mai
Andrew Pinski writes:
> On Wed, Nov 12, 2014 at 2:56 PM, Matthew Fortune
> wrote:
> >> > Moore, Catherine writes:
> >> > > The patch looks good. Please fix up these couple of nits prior to
> >> > > committing.
> >> >
> >
Hi,
I have had to use this patch several times when performing cross testing
but I'm not sure if it is the right fix. The MIPS target testsuite runs
all tests regardless of the current compiler configuration and downgrades
run tests to link tests and then to assembly tests depending on what
librar
Richard Biener writes:
> On Sun, Nov 23, 2014 at 10:15 AM, Matthew Fortune
> wrote:
> > Hi,
> >
> > I have had to use this patch several times when performing cross testing
> > but I'm not sure if it is the right fix. The MIPS target testsuite runs
>
Hi Prachi,
> OK with fixes to the changelog entry:
>
> latency not latency. Remember to tab in the changelog entry and split the
> line as it will exceed 80 chars. Also two spaces between the date/name and
> name/email. E.g.
>
> 2014-11-05 Prachi Godbole
>
> * config/mips/mips.c (mips
| 8
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b577824..7b9b365 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2014-11-25 Matthew Fortune
+
+ * gcc.target/mip
> Changelog:
>
> 2014-12-03 Prachi Godbole
>
> * config/mips/p5600.md (define_automaton, define_cpu_unit): Replace
> p5600_agen_pipe and p5600_alu_pipe with p5600_agen_alq_pipe.
>
> (p5600_int_arith_1, p5600_int_arith_2, p5600_int_arith_4): Change
> reservation order.
Jakub Jelinek writes:
> On Tue, Feb 17, 2015 at 08:10:37PM +0000, Matthew Fortune wrote:
> > Ping. Please could you advise if I can approve MIPS changes to release
> > branches of if I need you/someone else to do so?
>
> Any maintainer or reviewer can approve changes to
Thanks for looking through and catching this.
I had conflicting thoughts on whether the new condition should
reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we take it
that FP_CONDMOVE is the only way to get an integer conditional
move based on an FP condition then that's fine.
> 2015-0
Steve Ellcey writes:
> On Mon, 2015-03-02 at 15:54 -0800, Matthew Fortune wrote:
> > Thanks for looking through and catching this.
> >
> > I had conflicting thoughts on whether the new condition should
> > reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we t
Gerald Pfeifer writes:
> On Thu, 5 Feb 2015, Matthew Fortune wrote:
> > Thanks Catherine. Good call to remove the markup while reviewing. I've
> > done one more pass on this to have the same phrasing used where
> > similar points are being made. I also added a comment ab
Hi Steve,
Having worked on the new layout I of course am happy with it. I think it
makes the cross compiled sysroots much easier to use for installing
on a target as well as making the library paths match for cross compiled
and native. A couple of minor things...
> diff --git a/gcc/config/mips/mt
Steve Ellcey writes:
> As follow-up to this patch, I forgot to include a testsuite patch to two
> mips specific tests that fail with the new layout. These tests are
> loongson specific and have includes of system headers in them. The way
> mips.exp in testsuite/gcc.target/mips works is that for
Steve Ellcey writes:
> On Wed, 2015-06-17 at 19:44 +0100, Richard Sandiford wrote:
>
> >
> > FWIW, to be specific, I think we're talking about every check except
> > the last two in mips.md:
> >
> > and the one mips-ps-3d.md:
> >
> > In particular, the two checks in mips.c should go.
>
> OK, her
Maciej W. Rozycki writes:
> Richard, please have a look at my question below in a reference to your
> previous statement.
>
> On Thu, 18 Jun 2015, Steve Ellcey wrote:
>
> > OK, I checked in the prequel patch and here is a new copy of the
> > original patch based off of that (and with no HONOR_NA
Bernd Edlinger writes:
> Hi,this patch fixes a regression that was triggered by commit
> r225260.See
> pr66747 for details.Is it OK for
> trunk?ThanksBernd.
Thanks Bernd. I was just reviewing this PR. I think it will probably be safer
to move
the fix up to the mips_find_gp_ref and consider eac
Bernd Edlinger writes:
> On Sat, 4 Jul 2015 09:04:41, Richard Sandiford wrote:
> >
> > The final return here would also mishandle SEQUENCE PATTERNs.
> > The idea was that this function would only see "real" instructions,
> > so I think instead the FOR_EACH_SUBINSN should be here:
> >
> > static bo
Andrew Bennett writes:
> The stack-1.c testcase fails when being compiled for micromips with the
> -O0 optimization level. The reason is the testcase is expecting the
> following sequence at the end of the function:
>
>addiu $sp,$sp,16
>jrc $31
>
> But for micromips it gen
Moore, Catherine writes
> Hi Matthew,
>
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Tuesday, January 06, 2015 7:43 AM
> > To: Moore, Catherine
> > Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@
Richard Sandiford writes:
> "Maciej W. Rozycki" writes:
> > On Wed, 14 Jan 2015, Richard Sandiford wrote:
> >> I think we just have to accept that there are so many possible
> >> combinations that we can't test everything that's potentially
> relevant.
> >> I think it's more useful to be flexible
Moore, Catherine writes:
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Wednesday, January 14, 2015 2:54 PM
> > To: Moore, Catherine
> > Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
> >
c
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6b73d31..1285633 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2015-01-15 Andrew Bennett
+ Matthew Fortune
+
+ * gcc.target/mips/call-saved-4.c (foo): Ad
@@ -1,3 +1,9 @@
+2015-01-15 Matthew Fortune
+
+ * gcc.target/mips/mips.exp (mips-dg-options): -mips3d requires
+ -mno-micromips. MIPS32R1 and below require -mno-micromips.
+ -march=loongson* and -march=octeon* require -mno-micromips.
+
2015-01-15 Andrew Bennett
Jeff Law writes:
> On 01/15/15 03:13, Robert Suchanek wrote:
> >> Robert, can you look at reload.c::reload_inner_reg_of_subreg and
> >> verify that the comment just before its return statement is
> >> effectively the situation you're in.
> >>
> >> There are certainly cases where a SUBREG needs to
> > OK. The MIPS and Sparc ports are probably going to hit this the
> > hardest. So you've got a vested interest in dealing with any fallout
> > :-)
> >
> > jeff
>
> That's fine. The MIPS port has been widely tested and I cross tested it
> on sparc-linux-gnu target so hopefully there won't any f
> On 2015.01.16 at 14:56 +0100, Markus Trippelsdorf wrote:
> > On 2015.01.14 at 17:10 +, Robert Suchanek wrote:
> > > + u = v;
> > > + r = b | a[4];
> > > + return e;
> > > +
> >
> > There is a missing } in the testcase.
>
> Fixed in r219740 as obvious.
Thanks Markus.
Sorry about that, I
Hi Catherine,
> The new behaviour of the GCC driver passing floating point options like
> -msoft-float to the assembler is essential for the new o32 ABI
> extensions but is a change in behaviour. In particular GCC 5 used with
> binutils 2.24 would require a user to fix any hand-crafted code that
>
Moore, Catherine writes:
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Monday, January 19, 2015 5:54 PM
> > To: Moore, Catherine
> > Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
> >
I committed the following patch to wwwdocs having received approval
from Gerald.
Thanks,
Matthew
Index: htdocs/index.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v
retrieving revision 1.953
diff -r1.953 index.html
54a55,59
>
> This is a follow-up to a change [1] in glibc. It fixes the issue [2]
> when jal can not reach a target in different region.
>
> It has been tested with DejaGnu for mips32/o32, mips64/n32 and
> mips64/n64.
>
> Let me know what you think.
So to confirm, the issue is non-pic crt calling an init r
> 2015-01-23 Robert Suchanek
>
> * config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit
> accumulators
> for all vector modes.
This seems like a genuine bug and although it can only be triggered by
loongson or paired-single support it probably qualifies for fixing.
My suspicion
Richard Sandiford writes:
> Jeff Law writes:
> > On 01/15/15 03:13, Robert Suchanek wrote:
> >>> Robert, can you look at reload.c::reload_inner_reg_of_subreg and
> >>> verify that the comment just before its return statement is
> >>> effectively the situation you're in.
> >>>
> >>> There are cert
> This is a minimal backport of features added to GCC 5 to enable use
> of binutils 2.25 with GCC 4.9 for MIPS soft-float builds. Further
> details in the PR:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64569
>
> The commits which are being backported are listed below (the last
> one is post
Richard Sandiford writes:
> Matthew Fortune writes:
> >> 2015-01-23 Robert Suchanek
> >>
> >>* config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit
> >> accumulators
> >>for all vector modes.
> >
> > This seems
Hi Catherine,
I've made a first pass at writing up the MIPS changes for GCC 5.0.
Could you take a read and see what needs some more work?
Thanks,
Matthew
Index: htdocs/gcc-5/changes.html
===
Andrew Pinski writes:
> On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune
> wrote:
> > Hi Catherine,
> >
> > I've made a first pass at writing up the MIPS changes for GCC 5.0.
> > Could you take a read and see what needs some more work?
>
> One comment
e same phrasing used where similar
points are being made. I also added a comment about link compatibility
for FP64. Updated text is at the end.
Thanks,
Matthew
>
> Thanks,
> Catherine
>
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@
m: Petar Jovanovic [mailto:petar.jovano...@rt-rk.com]
> Sent: 05 February 2015 19:28
> To: gcc-patches@gcc.gnu.org; 'Maciej W. Rozycki'; Matthew Fortune
> Subject: [PATCH v2][MIPS] fix CRT_CALL_STATIC_FUNCTION macro
>
> v2:
> - add ChangeLog entry
> - use DLA instead of
Maciej W. Rozycki writes:
> On Thu, 5 Feb 2015, Matthew Fortune wrote:
>
> > I'm OK with this change but I'd like Catherine to comment before
> committing.
> > It seems a shame to duplicate the block of code but it is probably just
> as
> > ugly to d
Mike Stump writes:
> On Feb 6, 2015, at 4:23 AM, Maciej W. Rozycki
> wrote:
> > This consideration made me realise I've had a patch outstanding for
> > some
> > 10 years to convert all the `BAL x' instructions there to `BLTZAL $0,
> x'.
> > This has always been a good idea in case implementations
Hi Jakub,
I haven't done a backport to a release branch before. Could you tell me
who needs to approve this change, it only affects MIPS?
Thanks,
Matthew
> -Original Message-
> From: Matthew Fortune
> Sent: 26 January 2015 16:30
> To: 'gcc-patches@gcc.gnu.org
Ping. Please could you advise if I can approve MIPS changes to release branches
of if I need you/someone else to do so?
Thanks,
Matthew
> -Original Message-
> From: Matthew Fortune
> Sent: 07 February 2015 08:22
> To: ja...@redhat.com
> Cc: Moore, Catherine (catherine_m
> >> > Do you have an objection to allowing an option to disable these
> >> instructions (despite the reason for wanting to do so)?
> >>
> >> Yes this seems like a bad workaround for broken code.
> >>
> > Well, we work around broken hardware all the time. What would you
> suggest that Steve do i
Moore, Catherine writes:
> Review comments are attached. I will tackle the R6 patch next.
> Thanks,
> Catherine
Thanks Catherine. Depending on whether the fix to the following
hunk needs discussion I'll make the changes and commit.
>> static bool
>> mips_function_value_regno_p (const unsigned i
Matthew Fortune writes:
> > >> > Do you have an objection to allowing an option to disable these
> > >> instructions (despite the reason for wanting to do so)?
> > >>
> > >> Yes this seems like a bad workaround for broken code.
> > &
Hi James,
I think you have a bug in the following hunk where you pass
STORE_MAX_PIECES in place of the optimise for speed flag. I guess you
would need an extra argument to pass a different *_MAX_PIECES value
in.
thanks,
Matthew
>@@ -192,8 +184,7 @@ static void write_complex_part (rtx, rtx, bool)
Andrew Pinski writes:
> On Thu, Oct 30, 2014 at 11:30 PM, Zhenqiang Chen
> wrote:
> > Thank you all for the comments. Patch is updated.
> >
> > Bootstrap and no make check regression on X86-64.
> > No make check regression with Cortex-M0 qemu.
> > No performance changes for coremark, dhrystone, s
Steve Ellcey writes:
> Here is another MIPS configuration patch, this one allows the mips
> configuration to handle the --with-endian, --with-arch, and --with-abi
> configure options. Basically instead of having targets set
> MIPS_ABI_DEFAULT
> and MIPS_ISA_DEFAULT directly in tm_defines based o
> The patch below fixes the memory cost for P5600.
>
> ChangeLog:
> 2014-11-05 Prachi Godbole
>
> * config/mips/mips.c (mips_rtx_cost_data): Fix memory_letency cost for
> p5600.
Please follow these instructions to add yourself to MAINTAINERS in the
write-after-approval section now that you have
Hi Catherine,
The full patch is attached and the delta from v2 is inline below.
Testing (O32):
MIPS I - FP32, MIPS II - FP32, MIPS II - FPXX
MIPS32 - FP32, MIPS32 - FPXX, MIPS32 - FPXX ODDSPREG,
MIPS32R2 - FP32, MIPS32R2 - FPXX, MIPS32R2 - FPXX ODDSPREG,
MIPS32R2 - FP64, MIPS32R2 - FP64A
One of
This patch fixes all failures in the MIPS target tests which were failing
because of
-Wimplicit-int or -Wimplicit-function-declaration.
+2014-11-05 Matthew Fortune
+
+ * gcc.target/mips/asm-1.c (bar): Add prototype.
+ * gcc.target/mips/call-1.c (f, h): Add return type
Sorry to follow myself up. I realised that the new configure options should
be documented in install.texi. The only change from V3 is the
doc/install.texi change.
The MIPS64 tests have completed without regression.
Regards,
Matthew
gcc/
* common/config/mips/mips-common.c (mips_handle_opt
Moore, Catherine writes:
> The patch looks good. Please fix up these couple of nits prior to
> committing.
OK, thanks for the second read through. One further amendment below, I'll
aim to commit later today.
> Index: gcc/config/mips/mips.c
> ===
> (for MIPS) https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01481.html,
> although I have not been able to test this as there doesn't seem to be
> any working MIPS/Loongson hardware in the Compile Farm;
I will post a patch to remove vec_shl and only support vec_shr for
little endian. This is on the
> > Moore, Catherine writes:
> > > The patch looks good. Please fix up these couple of nits prior to
> > > committing.
> >
> > OK, thanks for the second read through. One further amendment below,
> > I'll aim to commit later today.
> >
>
> Yes, that's better.
Committed as r217446
Fingers cros
Richard Biener writes:
> The following patch avoids overaligned types created from IPA parameter
> replacement. It is said to help mipsel which still suffers from the
> backend-looks-at-type-alignment-for-parameter-passing-ABI bug.
>
> Bootstrap and regtest pending on x86_64-unknown-linux-gnu.
>
I have applied the MIPS specific fix for PR65345. It is a mechanical
change. This fixes the MIPS failures in atomic/pr65345-4.c.
gcc/
PR c/65345
* config/mips/mips.c (mips_atomic_assign_expand_fenv):
Use create_tmp_var_raw instead of create_tmp_var.
Thanks,
Matthew
diff
MIPS creates more invariants than gcc.dg/loop-8.c expects. There is
no way to represent what the original test was trying to verify given
the additional invariants being moved out of the loop.
Thanks,
Matthew
gcc/
PR rtl-optimization/9
* gcc.dg/loop-8.c: Skip for MIPS due to
Szabolcs Nagy writes:
> gcc should use libc headers, not kernel headers.
>
> libgcc/
> 2016-08-24 Szabolcs Nagy
>
> * config/mips/linux-unwind.h: Use sys/syscall.h.
OK.
Thanks for the fix.
Matthew
Szabolcs Nagy writes:
> Add the musl dynamic linker names for mips r6.
>
> It seems DRIVER_SELF_SPECS sets the default mips isa
> (MIPS_DEFAULT_ISA_LEVEL_SPEC) on *-mti-linux* or *-mti-elf, but not on
> gnu linux targets (see config/mips/mti-linux.h vs config/mips/gnu-
> user.h).
>
> Is that ok?
Andrew Haley writes:
> As discussed. I think I should ask a Global reviewer to approve this
> one. For obvious reasons I haven't included the diffs to the deleted
> gcc/java and libjava directories. The whole tree, post GCJ-deletion, is
> at svn+ssh://gcc.gnu.org/svn/gcc/branches/gcj/gcj-deleti
I've found a case of suboptimal code coming from LRA when we have a large
frame and have the frame grow downwards with MIPS. A good testcase for
this is the qsort benchmark from the automotive section of mibench[1].
Any frame access where the offset is not supported as an add-immediate
should bene
Hi,
I've identified a latent bug in the java interpreter that affects MIPS
n32 and n64 ABIs both little and big endian and, I presume, any 64-bit
big endian target with int as 32-bit.
A full description is in my original post:
https://gcc.gnu.org/ml/java-patches/2016-q2/msg00020.html
Patch test
Tom Tromey writes:
> >>>>> "Matthew" == Matthew Fortune writes:
> Matthew> I've identified a latent bug in the java interpreter that affects
> MIPS
> Matthew> n32 and n64 ABIs both little and big endian and, I presume, any
> 64-
ect.exp testsuite
change?
Thanks,
Matthew
>
> Regards,
> Robert
>
> > -Original Message-
> > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
> > On
> > Behalf Of Robert Suchanek
> > Sent: 10 August 2015 13:15
>
Jim Wilson writes:
> Hand tested to verify that I didn't accidentally break passing -g to
> the assembler.
In case you are waiting on an OK for the MIPS part... this is fine.
Thanks,
Matthew
Hi Sandra,
> The testcase gcc.target/mips/msa.c gives dozens of FAILs if it's tested
> with a GCC configured to default to -fno-common, because of patterns
> like
>
> /* { dg-final { scan-assembler-times "\t.comm\tv16i8_\\d+,16,16" 3 } }
> */
>
> Seems like the simplest solution is to force -fco
Prachi Godbole writes:
> Please find the updated patch below. I hope I've covered everything.
> I've added the test for inline restriction, could you check if I got all
> the options correct?
I think the test is probably good enough. It is a little too forgiving due
to handling the indirect call
Maciej Rozycki writes:
> On Fri, 23 Jun 2017, Prachi Godbole wrote:
>
> > Index: gcc/config/mips/mips.md
> > ===
> > --- gcc/config/mips/mips.md (revision 246899)
> > +++ gcc/config/mips/mips.md (working copy)
> > @@ -6578,6 +6581,20
Jakub Jelinek writes:
> Bootstrapped/regtested on x86_64-linux and i686-linux, where it improves
> e.g. the code generation for slp-43.c and slp-45.c testcases.
> make cc1 tested in cross-compilers to the remaining targets.
No objections for the MIPS part. I've pointed out this change to Sameera
Simon Atanasyan writes:
> Currently GCC supports 'long_call', 'far', and 'near' attributes. The
> 'long_call' and 'far' attributes are synonyms. This patch adds support
> for the 'short_call' attribute as a synonym for `near` to make this list
> complete, consistent with other targets, and compati
Simon Atanasyan writes:
> Here is the updated patch with chnaged e-mail address and fixed
> indentation issues:
> -8<
> Currently GCC supports 'long_call', 'far', and 'near' attributes. The
> 'long_call' and 'far' attributes are synonyms. This patch adds support
> for the 'shor
Simon Atanasyan writes:
> On Mon, Sep 11, 2017 at 03:26:52PM +0000, Matthew Fortune wrote:
> > Simon Atanasyan writes:
> > > Here is the updated patch with chnaged e-mail address and fixed
> > > indentation issues:
> > > -8<
> &g
Hi Paul,
Paul Hua writes:
> cc: Matthew.
>
> ping.
Sorry a little slow on the reply.
> On Thu, Jun 1, 2017 at 3:35 PM, Paul Hua wrote:
> > Hi,
> >
> > There are duplicate testcase in gcc.target/mips dir.
> >
> > div-5.c same as div-9.c.
> > div-6.c same as div-10.c.
> > div-7.c same as div-1
Sandra Loosemore writes:
> On 12/21/2016 11:54 AM, Yunqiang Su wrote:
> > By this patch, I add a build-time option ` --with-unfused-madd4=yes/no',
> > and runtime option -m(no-)unfused-madd4,
> > to disable generate madd.fmt instructions.
>
> Your patch also needs a documentation change so that t
Joseph Myers writes:
> The MIPS sfp-machine.h has an _FP_CHOOSENAN implementation which
> emulates hardware semantics of not preserving signaling NaN payloads for
> an operation with two NaN arguments (although that doesn't suffice to
> avoid sNaN payload preservation in any case with just one NaN
Joseph Myers writes:
> On Wed, 4 Jan 2017, Maciej W. Rozycki wrote:
>
> > AFAIR we deliberately decided not to define a 2008-NaN soft-float
> > ABI, and chose to require all soft-float binaries to use the legacy
> encoding.
>
> Soft-float and 2008-NaN are naturally completely orthogonal and the
Sandra Loosemore writes:
> On 01/10/2017 07:24 AM, Yunqiang Su wrote:
> > Hi, folks, any idea about this patch?
>
> I can only comment on the documentation parts.
I am reviewing the patch but need to determine if the changes are sufficient and
safe to meet the goal. This area is complex in the M
Maciej Rozycki writes:
> On Thu, 5 Jan 2017, Matthew Fortune wrote:
> > It is true to say that users are discouraged from using 2008-NaN with
> > soft-float for pre-R6 architectures simply to avoid further fragmentation
> > of software for no real gain. However, for R6 then s
Maciej Rozycki writes:
> On Thu, 12 Jan 2017, Toma Tabacu wrote:
>
> > > > Unfortunately, this interferes with the generation of DIV.G and
> > > > MOD.G (the div3 and mod3 patterns) for Loongson
> > > > targets,
> > > which
> > > > causes test failures.
> > >
> > > What test failures? Details p
Kito Cheng writes:
> On Mon, Jan 16, 2017 at 02:42:08PM +0800, Kito Cheng wrote:
> > 2017-01-16 Kito Cheng
> > Kuan-Lin Chen
> >
> > PR target/PR79079
> > * gcc/internal-fn.c (expand_mul_overflow): Use convert_modes
> instead of
> > gen_lowpart.
Thanks for t
Doug Gilmore
> I recently bisected PR78176 to problems introduced with r21650.
>
> Given the short time until the release, we would like to provide a
> target flag and build option to avoid the bug until we are able to
> resolve the problem with the commit. Note that as Matt
Moore, Catherine writes:
> > -Original Message-
> > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> > ow...@gcc.gnu.org] On Behalf Of Matthew Fortune
> > Sent: Monday, January 16, 2017 11:25 AM
> > To: Doug Gilmore ; gcc-
> > patc...@
Maciej Rozycki writes:
> On Mon, 16 Jan 2017, Toma Tabacu wrote:
>
> > After searching through the archives, I have found an interesting bit
> > of information about DIV.G/MOD.G in the original submission thread:
> >
> > > > Ruan Beihong 23 July 2008:
> > > >
> > > > I've seen the Loongson 2F man
Toma Tabacu writes:
> Matthew Fortune writes:
> >
> > Sounds good. I'd prefer to get the testsuite clean first then improve the
> > code quality as a later step since it is not a regression and we are
> > a few days off stage 4.
> >
> > In terms of
nused.
This optimization is off by default at all optimization levels.
+@item -mlxc1-sxc1
+@itemx -mno-lxc1-sxc1
+@opindex mlxc1-sxc1
+When applicable, enable (disable) the generation of @code{lwxc1},
+@code{swxc1}, @code{ldxc1}, @code{sdxc1} instructions. Enabled by default.
+
Hi Paul,
Your latest version of the patch is now committed. I have been doing some
work on the recursive build failure but the issue is complex and involves
LRA so I went ahead with committing your change independently. It also
turns out that (at least when targeting loongson3a) there are stage2
suite/gcc.target/mips/madd4-1.c
create mode 100644 gcc/testsuite/gcc.target/mips/madd4-2.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e53f9e1..7496071 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2017-01-19 Matthew Fortune
+ Yunqiang Su
+
+ * confi
Matthew Fortune writes:
> I've rewritten/simplified this patch as it provides far too much control
> to end users who will undoubtedly shoot themselves in the foot so to
> speak. The option I intend to support is simply --with-madd4 --without-madd4
> and -mmadd4 -mno-madd4.
Moore, Catherine writes:
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Thursday, January 19, 2017 5:30 PM
> > To: Moore, Catherine
> > Cc: 'Aurelien Jarno' ; 'Richard Sandiford'
> >
Toma Tabacu writes:
> The pic-3,4.c and pie-3,4.c tests are failing for some configurations of
> mips*-*-linux-*.
>
> This is because PIC is always on for MIPS Linux by default, except when the
> compiler is built with --with-mips-plt, in which case PIC is on by default
> only
> for the n64 ABI,
pr52125.c verifies that orphaned %hi relocs are deleted if they feed
an inline asm statement that never emits the %lo part. Orphaned %hi
relocs are only strictly a problem for o32 but are eliminated for
any ABI as long as 32-bit addressing is in use so force -msym32 as well
as require absolute addr
This is a fix for a compile failure in gcc.c-torture/compile/pr70240.c
with options -O1 -mmsa.
The expand code for replicated constant vectors with small immediate
values was simply wrong and would never work. This code is not used in the
simple case of initialising a variable with a constant vect
Another MSA related fix; this time relating to using -mno-odd-spreg.
This fixes a build-failure with gcc.c-torture/execute/20050604-1.c
when using -mabi=32 -mmsa -mno-odd-spreg.
The fix is to copy the whole vector from the odd-numbered source
register to the even numbered single-precision destinat
Hi Catherine,
I'm following up on PR target/80057 to update the description of -mvirt.
I agree with Roland that the description is inconsistent and should not
state 'application specific' as none of the other ASE options include
it. Instead I suggest we put the shortened form of (VZ) in like (XPA
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