Bernd Edlinger writes:
> this patch skips the redundant re-computing of the frame info after reload
> completed.
>
> I looked at all available targets initial_elimination_offset functions:
>
> All of them currently use either a trivial function of
> crtl->outgoing_args_size,
> get_frame_size (
Bernd Edlinger writes:
> Matthew Fortune writes:
> > Has the patch been tested beyond just building GCC? I can do a
> > test run for you if you don't have things set up to do one yourself.
>
> I built a cross-gcc with all languages and a cross-glibc, but I have
Richard Sandiford writes:
> "Steve Ellcey " writes:
> > Here is a patch for PR6400. The problem is that and_operands_ok was
> > checking
> > one operand to see if it was a memory_operand but MIPS16 addressing is more
> > restrictive than what the general memory_operand allows. The fix was to
>
Jeff Law writes:
> On 02/05/2016 12:31 PM, Bernd Schmidt wrote:
> > This patch fixes PR60410 by removing -fshort-double. Nick earlier
> > propsed a fix for the crash, but Richard B suggested removing the option
> > entirely, and I'd agree with that. It's a pointless ABI-changing option
> > on most
Woon yung Liu wries
> Bump! Sorry, but could I please get an answer? I'm willing to update the
> patch without
> credit, if necessary.
Hi WY,
Apologies for exceptionally slow response.
The patch you referenced is mostly OK but I would like to get the MIPS16 check
changed to a configure time ch
Steve Ellcey writes:
> Here is a new patch for PR 68273. The original problem with gsoap has
> been fixed by changing GCC to not create overly-aligned variables in
> the SRA pass but the MIPS specific problem of how user-aligned variables
> are passed to functions remains.
>
> Because MIPS GCC
> 2015-07-09 Steve Ellcey
>
> * config/mips/mti-linux.h (MIPS_SYSVERSION_SPEC): Update
> to handle mips[32|64]r3 and mips[32|64]r5.
OK, thanks.
Matthew
Andrew Bennett writes:
> I have noticed that in the mips.exp dg-option handling code the isa and
> arch_test_option_p variables are not updated after the pre-arch to arch
> dependency handling. This means that if this code changes the
> architecture the post-arch dependency handling code (which r
Robert Suchanek writes:
> > Hi Robert,
> > The patch is OK, but will you please name the test something other than the
> > date?
>
> OK. I'll change it to interrupt_handler-5.c, add a comment and commit after
> approval for the new interrupt handler options.
I believe this change is independent
Richard Sandiford writes:
> Robert Suchanek writes:
> > @@ -771,7 +771,8 @@ struct mips_cpu_info {
> >
> > /* Infer a -mnan=2008 setting from a -mips argument. */
> > #define MIPS_ISA_NAN2008_SPEC \
> > - "%{mnan*:;mips32r6|mips64r6:-mnan=2008}"
> > + "%{mnan*:;mips32r6|mips64r6:-mnan=2008;m
Robert Suchanek writes.
> 2015-07-16 Prachi Godbole
>
> gcc/
>
> * config/mips/m5100.md: New file.
> * config/mips/mips-cpus.def (m5100, m5101): Define.
> * config/mips/mips-tables.opt: Regenerate.
> * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100.
>
Robert Suchanek writes:
> 2015-07-16 Prachi Godbole
>
> gcc/
> * config/mips/i6400.md: New file.
> * config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400.
> (mips64r6): Likewise.
> (i6400): Define.
> * config/mips/mips-tables.opt: Regenerate.
> *
Andrew Bennett writes:
> diff --git a/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> b/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> index 0890ffa..20c26ca 100644
> --- a/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> +++ b/gcc/testsuite/gcc.target/mips/p5600-bonding.c
> @@ -1,6 +1,7 @@
> /*
A full range of 'compact' branch instructions were introduced to MIPS
as part of Release 6. The compact term is used to identify the fact
that these do not have a delay slot.
http://imgtec.com/mips/architectures/mips64/
The one subtlety of compact branches is that while they do not have
a delay s
Jeff Law writes:
> Another instance of left shifting a negative value. Fixed in an obvious
> way. Verified all the mips configurations in config-list.mk build now
> using a trunk compiler.
>
> Installed on the trunk,
Thanks Jeff.
Matthew
Moore, Catherine writes:
> The patch itself looks good, but the tests that you added need a little more
> work.
>
> I tested with the mips-sde-elf-lite configuration and I'm seeing failures for
> many
> options. The main failure mode seems to be that the stack is incremented by
> 24 instead o
Hi Robert,
Next batch of comments. This set covers the rest of mips-msa.md.
>+++ b/gcc/config/mips/mips-msa.md
>+(define_expand "vec_perm"
>+ [(match_operand:MSA 0 "register_operand")
>+ (match_operand:MSA 1 "register_operand")
>+ (match_operand:MSA 2 "register_operand")
>+ (match_operand:
Uros Bizjak writes:
> Fairly trivial patch that introduces no functional changes.
>
> * config/mips/mips.h (MIPS_STACK_ALIGN): Implement using
> ROUND_UP macro.
> * config/mips/mips.c (mips_setup_incoming_varargs): Use
> ROUND_DOWN to calculate off.
> (mips_gimplify_va_arg_exp
> This patch implements a more compact format for exception handling data.
> Although I don't
> have recent numbers for the amount of compression achieved, an earlier
> measurement showed
> a 30% reduction in the size of EH data for libstdc++.
>
> A design document detailing the new format is a
Maciej Rozycki writes:
> Move the `-mcompact-branches=' option out of the middle of a block of
> floating-point options. The option is not related to FP in any way.
> Place it immediately below other branch instruction selection options.
>
> gcc/
> * doc/invoke.texi (Option Summary)
Maciej Rozycki writes:
> Further to my changes made last November here is an update to the MIPS16
> `casesi' pattern making it emit bounds checking as RTL rather than having
> it as hardcoded assembly within the `casesi_internal_mips16_'
> dispatcher. See below for how PR tree-optimization/51513
Prachi Godbole writes:
> Changelog:
>
> 2017-04-25 Prachi Godbole
>
> gcc/
> * config/mips/mips.h (machine_function): New variable
> use_hazard_barrier_return_p.
> * config/mips/mips.md (UNSPEC_JRHB): New unspec.
> (mips_hb_return_internal): New insn pattern.
> *
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -77,7 +77,7 @@ m68k port Andreas Schwab
m68k-motorola-sysv portPhilippe De Muyter
mcore port Nick Clifton
microblaze Michael Eager
-mips port Matthew Fortune
+mips
Richard Sandiford writes:
> vect_recog_divmod_pattern currently bails out if the target has
> native support for integer division, but I think in practice
> it's always going to be better to open-code it anyway, just as
> we usually open-code scalar divisions by constants.
>
> I think the only cu
Robert Suchanek writes:
> This patch adds -mcrc and -mginv options to pass through them
> to the assembler.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
>
> * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc,
&g
Robert Suchanek writes:
> Update to i6400 scheduler.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Prachi Godbole
>
> * config/mips/i6400.md (i6400_gpmuldiv): Remove cpu_unit.
> (i6400_gpmul): Add cpu_unit.
> (i6400_gpdiv): Likewise.
> (i6400_msa_add_d): Up
Robert Suchanek writes:
> This patch adds i6500 CPU as an alias for i6400.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
>
> * config/mips/mips-cpus.def: New MIPS_CPU for i6500.
> * config/mips/mips-tables.opt: Regener
Robert Suchanek writes:
> The below adds support for -march=p6600. It includes
> a new scheduler plus performance tweaks.
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
> Prachi Godbole
> * config/mips/mips-cpus.def: Define P6600.
> *
Paul Hua writes:
> The gcc.c-torture/execute/scal-to-vec1.c trigger a gcc ICE bug.
>
> It's a mistake in define_expand vec_setv4hi in loongson.md file.
>
> 375 (define_expand "vec_setv4hi"
> 376 [(set (match_operand:V4HI 0 "register_operand" "=f")
> 377 (unspec:V4HI [(match_operand:V4
Hi,
This patch was developed as part of preparing ever more complex multilib
combinations for the MIPS architecture and aims to solve several problems
in this area. I've attempted to be quite verbose in the description, so
that I can explain how I am using various terms as pretty much everyone
has
t; gcc/ChangeLog:
>
> 2018-06-12 Matthew Fortune
> Prachi Godbole
>
> * config/mips/mips-cpus.def: Define P6600.
> * config/mips/mips-tables.opt: Regenerate.
> * config/mips/mips.c (mips_ucbranch_type): New enum.
> (mips_rtx_cost_data): A
Robert Suchanek writes:
> This patch adds -mcrc and -mginv options to pass through them
> to the assembler.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
>
> * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc,
&g
Tom de Vries writes:
> On 01/08/2018 05:32 PM, Tom de Vries wrote:
> > On 12/18/2017 05:57 PM, Vladimir Makarov wrote:
> >>
> >>
> >> On 12/15/2017 06:25 AM, Tom de Vries wrote:
> >>>
> >>> Proposed Solution:
> >>>
> >>> The patch addresses the problem, by:
> >>> - marking the hard regs that have
Tom de Vries writes:
> On 02/26/2018 12:00 PM, Matthew Fortune wrote:
> > Tom de Vries writes:
> >> On 01/08/2018 05:32 PM, Tom de Vries wrote:
> >>> On 12/18/2017 05:57 PM, Vladimir Makarov wrote:
> >>>>
> >>>>
> >>>> On
Tom de Vries writes:
> On 02/26/2018 12:00 PM, Matthew Fortune wrote:
> > Tom de Vries writes:
> >> On 01/08/2018 05:32 PM, Tom de Vries wrote:
> >>> On 12/18/2017 05:57 PM, Vladimir Makarov wrote:
> >>>>
> >>>>
> >>>> On
Hi,
This issue was caught with assert checking enabled but is not a
functional bug as XINT(x, 0) happens to overlay INTVAL(x) anyway.
Committed to trunk.
Thanks,
Matthew
gcc/
* config/mips/mips.c (mips_final_prescan_insn): Fix incorrect
XINT with INTVAL.
(mips_final_post
Hi,
It seems we have had a bug for some time that causes an ICE and prevents the
MIPS16 library builds from completing but is likely unrelated to MIPS16.
The problem is when we call target_reinit and library functions get created
as shown in the call stack at the end of this message. The first bui
Jason Merrill writes:
> On Thu, Mar 1, 2018 at 7:02 AM, Matthew Fortune
> wrote:
> > Hi,
> >
> > It seems we have had a bug for some time that causes an ICE and
> prevents the
> > MIPS16 library builds from completing but is likely unrelated to
> MIP
Hans-Peter Nilsson writes:
> All patches are together run through the gcc and g++ test-suites
> to check ASAN results for mipsisa32r2el-linux-gnu. As of
> r258635 those results are on par with those for
> arm-linux-gnueabihf, so without delay I present the current
> state. Maybe it's non-intrusi
Hi Paul
> ChangeLog entries:
>
> gcc/testsuite/ChangeLog
>
> 2018-03-24 Chenghua Xu
>
> * gcc.target/mips/umips-stroe16-2.c: Change "length = 2"
> to "l=2" in dg-final.
Looks good. Thanks for the cleanup. OK to commit.
Matthew
Hi Paul,
> ChangeLog entries:
>
> gcc/testsuite/ChangeLog
>
> 2018-03-24 Chenghua Xu
>
> * gcc.target/mips/fix-r4000-1.c: Delete "[^\n]" in dg-final.
> * gcc.target/mips/fix-r4000-2.c: Likewise.
> * gcc.target/mips/fix-r4000-3.c: Likewise.
> * gcc.target/mips/fix-r4000-4.c: Li
Maciej Rozycki writes:
> Given that the SVR4 vs PLT code model consideration is irrelevant for
> this test case rather than rewriting the regular expression to match
> this variant of code just enforce the PLT model by using the `-mplt'
> option. It is safe to use this option unconditionally as i
Maciej Rozycki writes:
> (we have no support for hard-float n64 MIPS16 code generation), which
> means that the test case will fail, as the regular expression pattern
> expects `lw' and `.word' rather than `ld' and `.dword' respectively to
> appear in assembly code generation. Correct the pattern
> Please don't add target macros. Add a hook if you must, but we're
> supposed to remove target macros, not add new ones :-)
Thanks Steven, I wasn't sure if there were still things that were
acceptable as macros. There's a lot to get rid of still.
Updated patch using a target hook. I've opted to
Moore, Catherine writes:
> > -Original Message-
> > From: Steve Ellcey [mailto:sell...@mips.com]
> > Sent: Friday, August 08, 2014 3:42 PM
> > To: Moore, Catherine; matthew.fort...@imgtec.com; echri...@gmail.com;
> >
> > 2014-08-08 Steve Ellcey
> >
> > * config/mips/mips.h (ASM_SPEC
Matthew Fortune writes:
> Moore, Catherine writes:
> > > -Original Message-
> > > From: Steve Ellcey [mailto:sell...@mips.com]
> > > Sent: Friday, August 08, 2014 3:42 PM
> > > To: Moore, Catherine; matthew.fort...@imgtec.com; echri...@gmail.co
Eric Christopher writes:
> On Sat, Aug 9, 2014 at 12:00 PM, Matthew Fortune
> wrote:
> > Moore, Catherine writes:
> >> > -Original Message-
> >> > From: Steve Ellcey [mailto:sell...@mips.com]
> >> > Sent: Friday, August 08, 2014 3
> > > > What is harder to fix about n32 than o32?
> > >
> > > "-msingle-float" with n32 creates 64 bit FPU instructions like dmtc1 and
> > > dmfc1. So I can't compile it for r5900. When I disable it, I get
> internal
> > > compiler errors.
> >
> > That certainly seems like a bug. Can you file a bug
The secondary_reload_class hook gets called for pseudos which have
not been allocated a hard register. For pseudos with the FP_REGS
class this results in the hook stating that the pseudo must be
reloaded via GR_REGS as it is neither in an FP_REG nor in memory.
This is obviously wasteful as LRA will
Ping.
Thanks,
Matthew
> Sent: 07 August 2014 07:21
> > Please don't add target macros. Add a hook if you must, but we're
> > supposed to remove target macros, not add new ones :-)
>
> Thanks Steven, I wasn't sure if there were still things that were
> acceptable as macros. There's a lot to get
rg/ml/gcc-patches/2014-08/msg01748.html
"Do not reload unallocated FP_REGS pseudos via GR_REGS"
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01745.html
Regards,
Matthew
2014-07-31 Matthew Fortune
gcc/
* common/config/mips/mips-common.c (mips_handle_option): Ensure
Ping^2
Added Jason as maintainer for dwarf related things.
This hook will be used in the following patch:
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg02172.html
Thanks,
Matthew
> Ping.
>
> Thanks,
> Matthew
>
> > Sent: 07 August 2014 07:21
> > > Please don't add target macros. Add a hook if
> On 09/02/2014 01:59 AM, Matthew Fortune wrote:
> >> > gcc/
> >> > * target.def (TARGET_DWARF_FRAME_REG_MODE): New target hook.
> >> > * targhooks.c (default_dwarf_frame_reg_mode): New function.
> >> > * targhooks.h (default_dwarf_frame
Ping!
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
> On Behalf Of Matthew Fortune
> Sent: 18 August 2014 14:25
> To: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
> Cc: Richard Sandiford; Eric Chr
Ping!
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
> On Behalf Of Matthew Fortune
> Sent: 22 August 2014 10:43
> To: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org); Eric Christopher
> (echri...@gmail
Hi Steve,
You're the lucky recipient of my first review so apologies for being
slow and cautious...
I tried to find a reason why the files were originally separated like this
and I can't see anything obvious. I assume you also found no reason.
Presumably the separation was just to avoid disturbi
> I talked to Andrew about what files he changed in GCC and created and
> tested this new patch. Andrew also mentioned changing some assembly
> files in glibc but I don't see any use of '.section .note.GNU-stack' in
> any assembly files in glibc (for any platform) so I wasn't planning on
> creatin
> 2014-10-08 Steve Ellcey
>
> * config/mips/mti-linux.h (DRIVER_SELF_SPECS): Change
> LINUX64_DRIVER_SELF_SPECS to LINUX_DRIVER_SELF_SPECS
OK. I'd agree with obvious here.
Matthew
> 2014-10-08 Andrew Pinski
>
> * config/mips/mips-cpus.def (octeon3): New cpu.
> * config/mips/mips.c (mips_rtx_cost_data): Add octeon3.
> (mips_print_operand ): Fix a bug as the mode
> of the comparison no longer matches mode of the operands.
> (mips_issue_rate): Handle PRO
Alan Lawrence writes:
> Patches 7-11 migrate migrate ARM, x86, IA64 (I think), and mostly PowerPC,
> to
> the new reduc_(plus|[us](min|max))_scal_optab. I have not managed to work
> out
> how to do the same for MIPS (specifically what I need to add to
> mips_expand_vec_reduc), and have had no resp
> gcc/
> * config/mips/mips.c (mips_rewrite_small_data_1): Take the context
> as a parameter instead of the containing MEM. Iterate over all
> subrtxes. Don't return a value.
> (mips_rewrite_small_data): Update call accordingly.
OK
> gcc/
> * config/mips/mips.c: Include rtl-iter.h.
> (mips_small_data_pattern_1): Take an rtx rather than an rtx pointer.
> Take the context as a parameter instead of the containing MEM.
> Iterate over all subrtxes.
> (mips_small_data_pattern_p): Update call accordingl
> gcc/
> * config/mips/mips.c (mips16_rewrite_pool_refs_info): Delete.
> (mips16_rewrite_pool_refs): Take the insn and constant pool as
> parameters. Iterate over the instruction's pattern and return void.
> (mips16_lay_out_constants): Update accordingly.
OK
> gcc/
> * config/mips/mips.c (r10k_needs_protection_p_1): Take an rtx
> rather than an rtx pointer. Change type of insn from "void *"
> to its real type. Return bool rather than int. Iterate over
> all subrtxes here.
> (r10k_needs_protection_p_store): Update accord
> gcc/
> * config/mips/mips.c (mips_kernel_reg_p): Replace with...
> (mips_refers_to_kernel_reg_p): ...this new function.
> (mips_expand_prologue): Update accordingly.
OK
> gcc/
> * config/mips/mips.c (mips_sim_insn): Update comment.
> (mips_sim_wait_regs_2): Delete.
> (mips_sim_wait_regs_1): Use FOR_EACH_SUBRTX_VAR.
OK
> gcc/
> * config/mips/mips.c (mips_record_lo_sum): Replace with...
> (mips_record_lo_sums): ...this new function.
> (mips_reorg_process_insns): Update accordingly.
OK
> gcc/
> * config/mips/mips.c (r10k_needs_protection_p_call): Take a const_rtx
> and return a bool. Iterate over all subrtxes here.
> (r10k_needs_protection_p): Update accordingly.
OK
> gcc/
> * config/mips/mips.c (mips_at_reg_p): Delete.
> (mips_need_noat_wrapper_p): Use FOR_EACH_SUBRTX.
OK. That should be the last one to cover all changes to use
new rtl iterators for MIPS.
Thanks for splitting this up per change it made it easy to read
through.
Matthew
Zhenqiang Chen writes:
> For CSiBE, ARM Cortex-m0 result is a little better. A little regression
> for
> MIPS. Roughly no change for PowerPC.
Do I take it that a little regression for MIPS is so small it can be
considered noise? I haven't had chance to run CSiBE to see the difference.
Thanks,
Ma
Hi Richard,
I've realised that I may need to do 'something' to prevent GCC from loading or
storing DFmode/DImode values to/from FPRs using pairs of SWC1/LWC1 when using
an unaligned address. Initial tests show that when loading from an unaligned
address (4-byte aligned) then GCC loads the two halv
Richard Sandiford writes:
> Matthew Fortune writes:
> > I've realised that I may need to do 'something' to prevent GCC from
> loading or
> > storing DFmode/DImode values to/from FPRs using pairs of SWC1/LWC1
> when using
> > an unaligned address. In
Richard Sandiford writes:
> Matthew Fortune writes:
> > MIPSr6 only supports 64-bit registers which naturally leads to needing
> > -mfp64. MIPSr6 does however also support a single-precision only
> variant.
> >
> > For a single purpose native toolchain then
hings
are resolved and more testing has been done.
Regards,
Matthew
From 4fc4f1c72e1d226691d4cebf2c5fa6de809fb409 Mon Sep 17 00:00:00 2001
From: Matthew Fortune
Date: Sat, 31 May 2014 23:33:21 +0100
Subject: [PATCH] fpxx feature fix
---
gcc/config.gcc |8
gcc/config/mi
This is a small clean-up patch to remove code relating to reloading or moving
mips fcc registers. At some point in the past these registers were allocated
as part of register allocation but they are now statically allocated in the
backend in a round robin fashion. The code for reloading them is the
Richard Sandiford writes:
> Matthew Fortune writes:
> > This is a small clean-up patch to remove code relating to reloading or
> moving
> > mips fcc registers. At some point in the past these registers were
> allocated
> > as part of register allocation but they are
> On 2014-06-16, 12:12 PM, Robert Suchanek wrote:
> > Pinging for approval.
> >
> > This part of the patch will be needed for MIPS16. The second part to
> enable
> > LRA in MIPS has been already approved.
> >
>
>Sorry, Robert. I thought you are waiting for some Richard's comment
> (actually h
Richard Sandiford writes:
> Sorry for the slow review.
And my slow response :-)
> Matthew Fortune writes:
> > The initial support for MIP64r6 is intentionally minimal to make
> review
> > easier. Performance enhancements and use of new MIPS64r6 features will
> > be
> This patch fixes an internal compiler error when micromips/nomicromips
> attributes are used.
>
> The problem here was that the cached boolean attributes for the current
> target did not agree with the uncached attributes throwing an assertion
> error.
>
> It appears that saving and restoring t
> > We could add -mflip-micromips complementing -mflip-mips16 and use
> > that for testing too. Chances are it'd reveal further issues.
> > Looking at how
> > -mflip-mips16 has been implemented it does not appear to me adding
> > -mflip-micromips would be a lot of effort.
>
> I'm in favour of ad
The change for MIPS looks fine by visual inspection and I've built both
a default pie and default no-pie compiler. The default pie won't build
glibc but I am pretty sure it is not down to this patch. I haven't had
time to look into why it won't build though, something related to
selecting the CRT f
Hi Robert,
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
> c3755f5..3c8ac30 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -19415,6 +19415,17 @@ mips_lra_p (void) {
>return mips_lra_flag;
> }
> +
> +/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOC
Robert Suchanek writes:
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index c3755f5..976f844 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -19415,6 +19415,21 @@ mips_lra_p (void)
> {
>return mips_lra_flag;
> }
> +
> +/* Implement TARGET_IRA_CHAN
Sameera Deshpande writes:
> Gentle reminder!
Thanks Sameera. Just a couple of comments inline below and a question
for Catherine at the end.
> - Thanks and regards,
>Sameera D.
>
> On Monday 30 March 2015 04:58 PM, sameera wrote:
> > Hi!
> >
> > Sorry for delay in sending this patch for rev
Szabolcs Nagy writes:
> Set up dynamic linker name for mips.
>
> gcc/Changelog:
>
> 2015-04-16 Gregor Richards
>
> * config/mips/linux.h (MUSL_DYNAMIC_LINKER): Define.
I understand that mips musl is o32 only currently is that correct?
There does however appear to be both soft and hard
Rich Felker writes:
> On Tue, Apr 21, 2015 at 01:58:02PM +0000, Matthew Fortune wrote:
> > Szabolcs Nagy writes:
> > > Set up dynamic linker name for mips.
> > >
> > > gcc/Changelog:
> > >
> > > 2015-04-16 Gregor Richards
> > &
> 2015-04-23 Steve Ellcey
>
> * config/mips/mips.md: (*madd4) Remove accum_in attribute.
> (*madd3): Ditto.
> (*msub4): Ditto.
> (*msub3): Ditto.
> (*nmadd4): Ditto.
> (*nmadd3): Ditto.
> (*nmadd4_fastmath): Ditto.
> (*nmadd3_fastmath): Ditto.
>
> Hi Matthew,
>
> 2015-04-21 15:24 GMT+01:00 Jiong Wang :
>
> >
> > 2015-04-21 Jiong Wang
> >
> > gcc/
> > * loop-invariant.c (find_defs): Enable DF_DU_CHAIN build.
> > (vfp_const_iv): New hash table.
> > (expensive_addr_check_p): New boolean.
> > (init_inv_motion_data): Initialize new
Steve Ellcey writes:
> This patch changes the default processor for mips4 from the r8000 to
> the
> r1. There are several reasons for this change, the main one
> being the difference in the r8000 madd instruction and the rest of the
> mips4
> family. The r8000 has a fused madd instruction (
H.J. Lu writes:
> On Mon, Apr 27, 2015 at 7:40 AM, Szabolcs Nagy
> wrote:
> >
> >
> > On 21/04/15 15:59, Matthew Fortune wrote:
> >> Rich Felker writes:
> >>> On Tue, Apr 21, 2015 at 01:58:02PM +, Matthew Fortune wrote:
> >>>&
Szabolcs Nagy writes:
> On 08/05/15 15:25, Matthew Fortune wrote:
> > H.J. Lu writes:
> >> On Mon, Apr 27, 2015 at 7:40 AM, Szabolcs Nagy
> >>
> >> wrote:
> >>>
> >>>
> >>> On 21/04/15 15:59, Matthew Fortune wrote:
>
Jeff Law writes:
> On 05/08/2015 10:50 AM, Joseph Myers wrote:
> >
> > Note that however the dynamic linker does properly need to save and
> > restore call-clobbered registers used for argument passing (because of
> > IFUNCs, user-provided malloc, audit hooks etc. that might affect them
> > even i
Hi Sameera,
Sameera Deshpande writes:
> Changelog:
> gcc/
> * config/mips/mips.md (JOIN_MODE): New mode iterator.
> (join2_load_Store): New pattern.
> (join2_loadhi): Likewise.
> (define_peehole2): Add peephole2 patterns to join 2
> HI/SI/SF/DF-mode
>
Jeff Law writes:
> On 05/11/2015 01:46 PM, Jeff Law wrote:
> > On 05/11/2015 01:44 PM, Steve Ellcey wrote:
> >> On Mon, 2015-05-11 at 13:22 -0500, Segher Boessenkool wrote:
> >>> Hi Steve,
> >>>
> >>> On Mon, May 11, 2015 at 10:50:02AM -0700, Steve Ellcey wrote:
> This patch broke a number of
Segher Boessenkool writes:
> On Mon, May 11, 2015 at 08:16:41PM +0000, Matthew Fortune wrote:
> > Does this patch effectively change the canonicalization rules? The
> > following Still exists in md.texi:
> >
> > @item
> > Within address computations (i.e., in
This patch adds new triplets: mips*-img-linux* and mips*-img-elf*
The purpose of these triplets is essentially to provide a clear separation
between tools which support mips32r5 and below and tools which support
mips32r6 and above.
Thanks,
Matthew
/
* configure.ac: Add mips-img-elf tripl
Eric Botcazou writes:
> > IIRC, fill_eager and its related friends are all speculative in some
> way
> > and aren't those precisely the ones that are causing us problems.
> Also
> > note we have backends working around this stuff in fairly blunt ways:
>
> I'd say that the PA back-end went a bit t
> OK to apply?
>
> 2014-11-17 Maciej W. Rozycki
>
> gcc/
> * gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
> range, a jump otherwise.
OK.
I only got my head around this code last week otherwise I wouldn't have
known whether this was correct!
Thanks,
Matth
> The atomic-compare-exchange-3.c and atomic-op-3.c tests are failing when
> using the -mfix-r1 option. This is due to the fact that the delay
> slot of the branch instruction that checks if the atomic operation was
> not successful can be filled with an operation that returns the output
> res
Maciej W. Rozycki writes:
> On Mon, 17 Nov 2014, Matthew Fortune wrote:
>
> > > gcc/
> > > * gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
> > > range, a jump otherwise.
> >
> > OK.
> >
> > I only got my head aroun
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