On 1 May 2015 at 10:11, Yvan Roux wrote:
> Hi all,
>
> As described in the thread bellow, there is a link-time workaround for
> an erratum (843419) of some early revision of Cortex-A53. Similarly
> to what was done for a previous erratum, this patch adds a new
> configure-time option --enable-fix
On 1 May 2015 at 12:26, Wilco Dijkstra wrote:
>
>
>> Marcus Shawcroft wrote:
>> On 27 April 2015 at 14:43, Wilco Dijkstra wrote:
>>
>> >> static unsigned int
>> >> -aarch64_min_divisions_for_recip_mul (enum machine_mode mode
>> >>
On 30 April 2015 at 20:38, Christophe Lyon wrote:
> This is a cleanup of the series of tests I added some time ago.
>
> During the latest reviews, I got comments about the fact that some
> intrinsics do not support all the vector types but the corresponding
> tests would still contain dummy expect
On 1 May 2015 at 09:21, Kyrill Tkachov wrote:
> 2015-05-01 Kyrylo Tkachov
>
> * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle FLOAT and
> UNSIGNED_FLOAT.
OK /Marcus
On 23 March 2015 at 17:06, Szabolcs Nagy wrote:
> GCC can be compiled for aarch64 target with busybox sed except for
> the geniterators.sh script which uses nonstandard basic regex.
>
> I explicitly set LC_ALL=C too because the regex depends on collation
> order.
>
> I tested that the script gives
On 1 May 2015 at 14:56, Yvan Roux wrote:
> 2015-05-01 Yvan Roux
>
> * configure.ac: Add --enable-fix-cortex-a53-843419 option.
> * configure: Regenerate.
> * config/aarch64/aarch64-elf-raw.h (CA53_ERR_843419_SPEC): Define.
> (LINK_SPEC): Include CA53_ERR_843419_SPEC.
>
On 1 May 2015 at 16:30, Renlin Li wrote:
> Thank you, Marcus. I have updated the patch accordingly, please check..
>
> Regards,
> Renlin Li
OK, thanks /Marcus
On 4 May 2015 at 09:58, Yvan Roux wrote:
> Yes this is a better formulation.
>
>> +corresponding flag to the linker. It can be explicitly disabled
>> during
>> +compilation by passing the @option{-mno-fix-cortex-a53-835769} option.
>>
>> Copy paste error here with the previous errata number.
>
>
On 4 May 2015 at 10:13, Chen Shanyao wrote:
> According to your opinion, I split the backports of pr64304 into 2 emails,
> and this one is for 4.9 branch.
> This patch backport the fix of PR target/64304 , miscompilation with
> -mgeneral-regs-only, to the 4.9 branch from trunk r219844. Tested on x
On 4 May 2015 at 10:03, Chen Shanyao wrote:
> According to your opinion, I split the backports of pr64304 into 2 emails,
> and this one is for 4.8 branch.
> This patch backport the fix of PR target/64304 , miscompilation with
> -mgeneral-regs-only, to the 4.8 branch from trunk r219844. Tested on x
On 5 May 2015 at 11:00, Matthew Wahab wrote:
> 2015-05-05 Matthew Wahab
>
>
> * gcc/config/aarch64-protos.h (struct cpu_branch_cost): New.
> (tune_params): Add field branch_costs.
> (aarch64_branch_cost): Declare.
> * gcc/config/aarch64.c (generic_branch_cost):
On 17 April 2015 at 16:40, Alan Lawrence wrote:
> This just adds the necessary patterns used for comparisons of DImode
> vectors. Used as part of arm_neon.h, in next/final patch.
>
> Tested on aarch64-none-elf.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md
> (aarch64_vcond_intern
On 17 April 2015 at 16:41, Alan Lawrence wrote:
> This also makes the existing intrinsics tests apply to the new patterns.
>
> Tested on aarch64-none-elf.
>
> gcc/ChangeLog:
>
> * config/aarch64/arm_neon.h (vceq_s64, vceq_u64, vceqz_s64,
> vceqz_u64,
> vcge_s64, vcge_u64, vcgez_s64
On 5 May 2015 at 12:07, Christian Bruel wrote:
> This fixes PR target/66015 and a latent issue revealed by
> gcc.dg/ipa/iinline-attr.c since
> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01609.html
>
> Regtested on aarch64-linux-gnu by Linaro.
>
> OK for trunk ?
OK. Is this issue present in gc
On 29 October 2014 10:28, Zhenqiang Chen wrote:
>
>
>> -Original Message-
>> From: Richard Henderson [mailto:r...@redhat.com]
>> Sent: Monday, October 27, 2014 10:56 PM
>> To: Zhenqiang Chen
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [Ping] [PATCH, 1/10] two hooks for conditional compa
On 14 November 2014 08:19, Andrew Pinski wrote:
> On Fri, Nov 14, 2014 at 12:12 AM, Tejas Belagod wrote:
>>
>> Hi,
>>
>> Following the discussion here
>> https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02237.html, this has been
>> tracked down to a range-checking bug with symbol + offset style addr
On 12 November 2014 16:46, Ramana Radhakrishnan
wrote:
> v2 , based on Richard's suggestion as well as fixing a bug that I hit in
> some more testing at O1. aarch64_internal_mov_immediate should not generate
> a temporary for subtarget when not actually "generating" code.
>
> Tested again on aarc
On 11 November 2014 23:39, Andrew Pinski wrote:
> Hi,
> The problem here is that aarch64-builtins.c contains gty markers but
> does not include gt-aarch64-builtins.h and is not included in the
> target_gtfiles list in config.gcc. So sometimes the builtins get
> garbage collected when they shoul
On 13 November 2014 06:14, Yangfei (Felix) wrote:
> Hi,
>
> We find that the VALLDI mode iterator used in *aarch64_simd_ld1r
> pattern is not appropriate.
> The reason is that it's impossible to get a new operand of DImode by
> vec_duplicating an operand of the same mode.
> So this patch j
On 14 November 2014 00:56, Andrew Pinski wrote:
> This adds the schedule model for ThunderX. There are a few TODOs in that
> not all of the SIMD is model currently. Also the idea of a simple
> shift/extend is not modeled and all cases where there is a shift/extend
> is considered as non simple an
On 14 November 2014 10:50, James Greenhalgh wrote:
> On Fri, Nov 14, 2014 at 10:42:27AM +, Andrew Pinski wrote:
>> On Fri, Nov 14, 2014 at 2:35 AM, James Greenhalgh
>> wrote:
>> >
>> > Hi,
>> >
>> > We currently do not set any interesting default values for jump and
>> > function
>> > alignm
On 12 November 2014 13:11, Christophe Lyon wrote:
> Hi,
>
> The attached patch adds a few more tests to the recently added
> advsimd-intrinsics series.
>
> OK for trunk?
>
> Christophe.
>
> 2014-11-12 Christophe Lyon
>
> * gcc.target/aarch64/advsimd-intrinsics/vcls.c: New test.
> * gcc.
On 14 November 2014 08:12, Tejas Belagod wrote:
> 2014-11-14 Tejas Belagod
>
> gcc/
> * config/aarch64/aarch64-protos.h (aarch64_classify_symbol):
> Fixup prototype.
> * config/aarch64/aarch64.c (aarch64_expand_mov_immediate,
> aarch64_cannot_force_const_mem, aa
On 11 November 2014 11:59, Kyrill Tkachov wrote:
> Hi all,
>
> This patch models the latency of moves between FP and GP registers on the
> A15 and A57 a bit more accurately by splitting the reservations for FP->GP
> and GP->FP moves and adding an appropriate bypass.
>
> Bootstrapped and tested on
On 14 November 2014 14:35, Wilco Dijkstra wrote:
> 2014-11-14 Wilco Dijkstra
>
> * gcc/config/aarch64/aarch64.c (generic_regmove_cost):
> Increase FP move cost.
OK /Marcus
On 14 November 2014 15:06, Kyrill Tkachov wrote:
> Hi all,
>
> Considering that the erratum workaround option was backported to 4.9, I
> assume we'll need an item for that
> in the changes.html for that branch?
>
> The text is the same as in the trunk version that I committed recently.
Looks OK t
On 17 November 2014 14:48, Kyrill Tkachov wrote:
> Hi all,
>
> Some configurations of Cortex-A53 and Cortex-A57 don't ship with crypto,
> so enabling it by default for -mcpu=cortex-a53 and cortex-a57 is
> inappropriate.
>
> Tested aarch64-none-elf. Reminder that at the moment all the crypto
> exte
On 14 November 2014 10:45, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove.
> * config/aarch64/aarch64-simd-builtins.def (create): Remove.
> * config/aarch64/aarch64-simd.md (aarch64_create): Remove.
> * config/a
On 14 November 2014 10:46, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set): Add
> variant reading from memory and assembling to ld1.
>
> * config/aarch64/arm_neon.h (vld1_lane_f32, vld1_lane_f64,
> vld1_lane_p8,
> v
On 14 November 2014 10:46, Alan Lawrence wrote:
> This patch replaces the inline asm for vld1_dup intrinsics with a vdup_n_
> and a load from the pointer. The existing *aarch64_simd_ld1r insn,
> combiner, etc., are quite capable of generating the expected single ld1r
> instruction from this. (I've
On 14 November 2014 12:01, Christophe Lyon wrote:
> On 14 November 2014 12:17, Marcus Shawcroft
> wrote:
>> On 12 November 2014 13:11, Christophe Lyon
>> wrote:
>>> Hi,
>>>
>>> The attached patch adds a few more tests to the recently added
>&g
On 17 November 2014 06:58, Yangfei (Felix) wrote:
> PING?
> BTW: It seems that Alan's way of improving vld1(q?)_dup intrinsic is more
> elegant.
> So is the improvement of vcls(q?) vcnt(q?) OK for trunk? Thanks.
Please rebase over Alan's patch and repost, thank you /Marcus
On 17 November 2014 07:59, Yangfei (Felix) wrote:
>> +2014-11-13 Felix Yang
>> +
>> + * config/aarch64/aarch64.md (doloop_end): New pattern.
>> +
This looks like a straight copy of the ARM code, but without the
TARGET_CAN_USE_DOLOOP_P definition. If the reason for including this
code is
On 18 November 2014 11:28, Yangfei (Felix) wrote:
> Yeah, that's a good idea. See my updated patch :-)
>
>
> Index: gcc/ChangeLog
> ===
> --- gcc/ChangeLog (revision 217394)
> +++ gcc/ChangeLog (working copy)
> @@ -1,3 +
On 17 November 2014 17:33, Renlin Li wrote:
> Hi all,
>
> This is a simple patch to add more conditional macros defined ACLE 2.0.
>
> aarch64-none-elf target is tested on the model, no new issues.
>
> Is this Okay for trunk?
>
>
> gcc/ChangeLog:
>
> 2014-11-17 Renlin Li
>
> * config/aarch64
On 13 November 2014 10:38, Alan Lawrence wrote:
> Hi,
>
> gcc/config/aarch64/iterators.md contains numerous duplicates - not always
> obvious as they are not always sorted the same. Sometimes, one copy is used
> is aarch64-simd-builtins.def and another in aarch64-simd.md; othertimes
> there is no
On 19 November 2014 14:32, Wilco Dijkstra wrote:
> Hi Jiong,
>
> Can you commit this please?
>
> 2014-11-19 Wilco Dijkstra
>
> * gcc/config/aarch64/aarch64.c (generic_regmove_cost):
> Increase FP move cost (PR61915).
>
Use the proper format for referring to PR's in the Changelo
On 12 November 2014 17:47, Charles Baylis wrote:
> On 12 November 2014 15:35, Alan Lawrence wrote:
>> Nice! One nit - can the extra "tree" argument be a "const_tree" ? - I'll
>> defer to the maintainers on the use of C++ default arguments in the AArch64
>> backend. But LGTM.
>
> Thanks, good catc
On 19 November 2014 16:48, Charles Baylis wrote:
> On 19 November 2014 16:42, Alan Lawrence wrote:
>> Of the calls to aarch64_simd_lane_bounds that remain in aarch64-simd.md:
>> aarch64_get_lanedi
>> aarch64_im_lane_boundsi
>> aarch64_ld{2,3,4}_lane
>>
>> I'll handle the first two. Do we have a p
On 19 November 2014 19:05, Charles Baylis wrote:
> PR target/63870
> * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Pass
> expression to aarch64_simd_lane_bounds.
> * config/aarch64/aarch64-protos.h (aarch64_simd_lane_bounds): Update
> prot
On 20 November 2014 14:33, Tejas Belagod wrote:
> The same patch applies cleanly to 4.9. OK to commit?
>
> Thanks,
> Tejas.
Provided it regresses ok, yes.
/Marcus
On 14 November 2014 16:48, Alan Hayward wrote:
> This is a new version of my BE patch from a few weeks ago.
> This is part 2 and covers all the aarch64 changes.
>
> When combined with the first patch, It fixes up movoi/ci/xi for Big
> Endian, so that we end up with the lab of a big-endian integer
On 13 November 2014 10:09, David Sherwood wrote:
> gcc/:
> 2014-11-13 David Sherwood
>
> * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist,
> aarch64_reverse_mask): New decls.
> * config/aarch64/iterators.md (UNSPEC_REV_REGLIST): New enum.
>
On 20 November 2014 16:27, Alex Velenko wrote:
>
> 2014-11-20 Alex Velenko
>
> *MAINTAINERS (write-after-approval): Add myself.
>
Your patch looks fine, commit it. /Marcus
On 21 November 2014 12:11, Alan Hayward wrote:
> 2014-11-21 Alan Hayward
>
> PR 57233
> PR 59810
> * config/aarch64/aarch64.c
> (aarch64_classify_address): Allow extra addressing modes for BE.
> (aarch64_print_operand): New operand for printing a q regis
On 17 November 2014 17:35, Kyrill Tkachov wrote:
> 2014-11-17 Kyrylo Tkachov
>
> * config/aarch64/arm_neon.h (vsqrt_f64): New intrinsic.
>
> 2014-11-17 Kyrylo Tkachov
>
> * gcc.target/aarch64/simd/vsqrt_f64_1.c
OK /Marcus
On 17 November 2014 11:42, Kyrill Tkachov wrote:
> Makes sense. Here are the changes for the 4.9 and 4.8 changes.html pages.
>
> Ok?
This looks ok to me, I'd suggest changing...
+ Starting with GCC 4.8.4 a workaround for the ARM Cortex-A53
to
+ As of GCC 4.8.4
OK with that change.
/
On 14 November 2014 15:46, Alan Lawrence wrote:
>> gcc/ChangeLog:
>>
>> * config/aarch64/aarch64-simd.md (vec_shr): New.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * lib/target-supports.exp
>> (check_effective_target_whole_vector_shift): Add aarch64{,_be}.
OK /Marcus
On 17 November 2014 16:56, Alan Lawrence wrote:
> This is a pure tidyup, no new functionality. Changes are
> (1) Use op[0] to store the result operand, rather than a separate variable,
> thus combining the two large switch statements into one;
> (2) The 'arg' and 'mode' arrays were (almost-)only e
On 14 November 2014 16:38, Jiong Wang wrote:
>
> gcc/
> * config/aarch64/iterators.md (VS): New mode iterator.
> (vsi2qi): New mode attribute.
> (VSI2QI): Likewise.
> * config/aarch64/aarch64-simd-builtins.def: New entry for ctz.
> * config/aarch64/aarch64-simd.md (ctz2): New pattern for
On 18 November 2014 12:20, Kyrill Tkachov wrote:
>
> On 18/11/14 10:33, Kyrill Tkachov wrote:
>>
>> diff --git a/gcc/config/arm/aarch-common-protos.h
>> b/gcc/config/arm/aarch-common-protos.h
>> index 264bf01..ad7ec43c 100644
>> --- a/gcc/config/arm/aarch-common-protos.h
>> +++ b/gcc/config/arm/aa
On 18 November 2014 10:33, Kyrill Tkachov wrote:
> 2014-11-18 Kyrylo Tkachov
>
> * config/aarch64/aarch64.c: Include tm-constrs.h
> (AARCH64_FUSE_ADRP_ADD): Define.
> (cortexa57_tunings): Add AARCH64_FUSE_ADRP_ADD to fuseable_ops.
> (cortexa53_tunings): Likewise.
> (aarch_m
On 18 November 2014 10:33, Kyrill Tkachov wrote:
> 2014-11-18 Kyrylo Tkachov
>
> * config/aarch64/aarch64.c (AARCH64_FUSE_MOVK_MOVK): Define.
> (cortexa53_tunings): Specify AARCH64_FUSE_MOVK_MOVK in fuseable_ops.
> (cortexa57_tunings): Likewise.
> (aarch_macro_fusion_pair_p): H
On 18 November 2014 10:33, Kyrill Tkachov wrote:
> 2014-11-18 Kyrylo Tkachov
>
> * config/aarch64/aarch64.c (AARCH64_FUSE_ADRP_LDR): Define.
> (cortexa53_tunings): Specify AARCH64_FUSE_ADRP_LDR in fuseable_ops.
> (aarch_macro_fusion_pair_p): Handle AARCH64_FUSE_ADRP_LDR.
OK /Marcu
On 1 December 2014 at 07:48, Gopalasubramanian, Ganesh
wrote:
> Please ignore the previous patch sent. The attachment was wrong.
>
>> There's no point in the buffer or the sprintf.
>> The text is short enough to repeat whole pattern in the array:
>
> Updated the patch for the above suggestions.
>
On 26 February 2015 at 06:22, Xingxing Pan wrote:
> Hi,
>
> This patch fix the type of mov_aarch64 in aarch64.md.
> Is it OK for trunk?
OK, thank you /Marcus
On 25 February 2015 at 09:53, Kyrill Tkachov wrote:
>
> On 13/02/15 10:14, Richard Earnshaw wrote:
>>
>> On 13/02/15 09:52, Kyrill Tkachov wrote:
>>>
>>> Hi all,
>>>
>>> This patch to changes.html mentions the xgene1 support in GCC 5 for arm
>>> and aarch64 and also the FreeBSD support for ARM.
>>
On 10 June 2015 at 11:06, weixiangyu wrote:
> Another backport patch which fixes a csmith ICE problem. Rebased on the
> latest 4.9 branch.
> Tested ok on aarch64-linux with qemu.
>
Hi, The attached patch contains a ChangeLog diff but no code diff.
The patch r210497 on mainline is an adjustment t
t; break;
>
> case SIMD_ARG_STOP:
> @@ -886,7 +889,7 @@ aarch64_simd_expand_args (rtx target, int icode, i
>}
>
>if (!pat)
> -return 0;
> +return NULL_RTX;
>
>> -Original Message-
>> From: James Greenhalgh [mailto:
On 4 June 2015 at 14:36, Renlin Li wrote:
> Hi Marcus,
>
> Sorry for the delay. I have come up with an updated patch. Two test cases
> are added to check against the limit.
>
> __ARM_ALIGN_MAX_STACK_PWR is hard coded into 16.
> __ARM_ALIGN_MAX_PWR is hard coded into 28 which is the maximum allow
On 4 June 2015 at 01:35, Jim Wilson wrote:
> I noticed that poor code is emitted for a long double 0.0. This testcase
> long double sub (void) { return 0.0; }
> void sub2 (long double *ld) { *ld = 0.0; }
> currently generates
> sub:
> ldr q0, .LC0
> ret
> ...
> sub2:
> ldr q0, .LC1
> str q0, [x0]
On 29 May 2015 at 09:32, Shiva Chen wrote:
> Hi, Andrew
>
> I modify the patch as you suggestion and testing on 32/64 bit host.
>
> Thanks your tips.
>
> I really appreciate for your help.
>
> Shiva
OK and committed with this ChangeLog:
2015-06-14 Shiva Chen
* aarch64.c (aarch64_simd_lane_bo
On 12 June 2015 at 21:43, Jim Wilson wrote:
> We have 5 patterns that can emit the movi instruction. These patterns
> map it to 4 different type attributes. The mov_aarch64 pattern
> uses mov_imm. The movdi_aarch64 pattern uses fmov. The movtf_aarch64
> pattern uses fconstd. And the two aarch
On 4 June 2015 at 10:16, Matthew Wahab wrote:
> gcc/
> 2015-06-4 Matthew Wahab
>
> * config/aarch64/aarch64-arches.def: Add "armv8.1-a".
> * config/aarch64/aarch64-options-extensions.def: Update "fP",
> "simd" and "crypto". Add "lse", "pan", "lor" and "rdma".
>
On 18 June 2015 at 20:17, Christophe Lyon wrote:
> Hi,
>
> While backporting the fix for PR62308 from trunk to 4.9-branch, it
> appeared that a testcase would be useful.
>
> Here it is. I'll send another email to request the backport of the fix
> + testcase to the 4.9-branch.
>
> Christophe.
>
> 2
On 20 May 2015 at 11:21, Jiong Wang wrote:
> gcc/
> * config/aarch64/aarch64.md: (ldr_got_small_): Support new GOT
> relocation
> modifiers.
> (ldr_got_small_sidi): Ditto.
> * config/aarch64/iterators.md (got_modifier): New mode iterator.
> * config/aarch64/aarch64-otps.h (aarch64_code
On 23 June 2015 at 14:02, Jiong Wang wrote:
>
> Marcus Shawcroft writes:
>
>> On 20 May 2015 at 11:21, Jiong Wang wrote:
>>
>>> gcc/
>>> * config/aarch64/aarch64.md: (ldr_got_small_): Support new GOT
>>> relocation
>>> modifiers.
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> This patch moves the instruction fusion pairs from a set of #defines
> to an enum which we can generate from a .def file.
>
> We'll use that .def file again, and the friendly names it introduces
> shortly.
>
> OK?
>
> Thanks,
> James
>
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> The FMA steering pass should be enabled through the tuning structures
> rather than be an intrinsic property of the core. This patch moves
> the control of the pass to the tuning structures - turning it off for
> everything other than
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> If we want to overwrite parts of this structure, we're going to need it
> to be more malleable than it is presently.
>
> Run through and remove const from each of the members, create a non-const
> tuning structure we can modify, and set
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> This final patch adds support for the new command line option
> "-moverride". The purpose of this command line is to allow expert-level users
> of the compiler, and those comfortable with experimenting with the compiler,
> *unsupported*
On 26 June 2015 at 10:32, Jiong Wang wrote:
>
> This patch respin https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01804.html.
>
> A new symbol classification "SYMBOL_SMALL_GOT_28K" added to represent symbol
> which needs go through GOT table and it's under -fpic/-mcmodel-small. the
> "_28K"
> suffi
On 26 June 2015 at 10:23, Jiong Wang wrote:
> OK. Reworked this patch. Removed those redundant memory model check by
> adding new symbol classification. Patch splitted into two:
>
> * [1/2] Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G
> * [2/2] Implement -fpic for -mcmodel=small
>
> This is
On 22 June 2015 at 17:17, Matthew Wahab wrote:
> Hello,
>
> The documentation for the ARMv8.1 +rdma option doesn't mention that enabling
> it
> also implies enabling Adv.SIMD. This patch fixes that.
>
> The documentation for the -march and -mcpu options are also a little messy,
> this
> patch trie
On 20 May 2015 at 11:56, Jiong Wang wrote:
> 2015-05-19 Marcus Shawcroft
> Jiong Wang
>
> gcc/
> * config/aarch64/aarch64-protos.h (arch64_symbol_type): Rename
> SYMBOL_SMALL_TPREL to SYMBOL_TLSLE.
> (aarch64_symbol_context): Ditto.
> *
On 20 May 2015 at 12:21, Jiong Wang wrote:
>
> Add new unspec name UNSPEC_TLSLE, use it for all tlsle pattern.
>
> ok for trunk?
>
> 2015-05-19 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (UNSPEC_TLSLE): New enumeration.
> (tlsle): Use new unspec name.
> (tlsle_): Ditto.
OK /Marcus
On 20 May 2015 at 12:19, Jiong Wang wrote:
>
> Similar to the rename from SYMBOL_SMALL_TPREL to SYMBOL_TLSLE, this
> patch rename the rtl pattern name.
>
> ok for trunk?
>
> 2015-05-19 Jiong Wang
> gcc/
> * config/aarch64/aarch64.md (tlsle_small): Rename to tlsle.
> (tlsle_small_): Rename t
On 21 May 2015 at 17:44, Jiong Wang wrote:
>
> This patch add -mtls-size option for AArch64. This option let user to do
> finer control on code generation for various TLS model on AArch64.
>
> For example, for TLS LE, user can specify smaller tls-size, for example
> 4K which is quite usual, to let
On 21 May 2015 at 17:49, Jiong Wang wrote:
> 2015-05-14 Jiong Wang
> gcc/
> * config/aarch64/aarch64.c (aarch64_print_operand): Support tls_size.
> * config/aarch64/aarch64.md (tlsle): Choose proper instruction
> sequences.
> (tlsle_): New define_insn.
> (tlsle_movsym_): Ditto.
> *
On 2 July 2015 at 14:44, Christophe Lyon wrote:
> Hi,
>
> Here is the missing test for ARM/AArch64 AdvSIMD intrinsic: vget_lane.
>
> Tested on arm, armeb, aarch64 and aarch64_be targets (using QEMU).
>
> The tests all pass, expect on armeb where vgetq_lane_s64 and
> vgetq_lane_u64 fail. I haven't
On 6 July 2015 at 09:20, Szabolcs Nagy wrote:
> 2015-07-06 Szabolcs Nagy
>
> * gcc.target/aarch64/fnmul-1.c: New.
> * gcc.target/aarch64/fnmul-2.c: New.
> * gcc.target/aarch64/fnmul-3.c: New.
> * gcc.target/aarch64/fnmul-4.c: New.
+float
+foo_s (float a, float
On 15 January 2015 at 15:38, Renlin Li wrote:
> gcc/testsuite/ChangeLog:
>
> 2015-01-15 Renlin Li
>
> * gcc.dg/builtin-apply2.c: Remove aarch64 target from skip list.
>
OK /Marcus
On 15 January 2015 at 09:50, James Greenhalgh wrote:
> 2015-01-15 James Greenhalgh
>
> * config/arm/cortex-a57.md: New.
> * config/aarch64/aarch64.md: Include it.
> * config/aarch64/aarch64-cores.def (cortex-a57): Tune for it.
> * config/aarch64/aarch64-tune.md:
On 14 January 2015 at 15:31, Jiong Wang wrote:
> 2015-01-15 Jiong. Wang (jiong.w...@arm.com)
> gcc/
> PR64304
> * config/aarch64/aarch64.md (define_insn "*ashl3_insn"): Deleted.
> (ashl3): Don't expand if operands[2] is not constant.
>
> gcc/testsuite/
> * gcc.target/aarch64/pr64304.c: New
On 15 January 2015 at 18:18, Richard Henderson wrote:
> On 12/15/2014 12:41 AM, Zhenqiang Chen wrote:
>> +(define_expand "cmp"
>> + [(set (match_operand 0 "cc_register" "")
>> +(match_operator:CC 1 "aarch64_comparison_operator"
>> + [(match_operand:GPI 2 "register_operand" "")
>>
> +2014-12-09 Felix Yang
> +
> + * config/aarch64/aarch64-simd.md (aarch64_p): New
> + pattern.
> + * config/aarch64/aarch64-simd-builtins.def (smaxp, sminp, umaxp,
> + uminp, smax_nanp, smin_nanp): New builtins.
> + * config/aarch64/arm_neon.h (vpmax_s8, vpmax_s16,
On 12 January 2015 at 15:12, Matthew Wahab wrote:
> 2015-01-08 Matthew Wahab
>
> PR target/64149
> * config/aarch64/aarch64.opt: Remove lra option and aarch64_lra_flag
> variable.
> * config/aarch64/aarch64.c (TARGET_LRA_P): Set to
> hook_bool_void_true.
>
On 12 December 2014 at 15:33, Kyrill Tkachov wrote:
> 2014-12-11 Kyrylo Tkachov
> Ramana Radhakrishnan
>
> PR target/64263
> * config/aarch64/aarch64.md (*movsi_aarch64): Don't split if the
> destination is not a GP reg.
> (*movdi_aarch64): Likewise.
>
> 2014-12-11
On 13 January 2015 at 15:17, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> (Set_Neon_Cumulative_Sat): Add parameter.
> (__set_neon_cumulative_sat): Support new parameter.
> * gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.in
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK):
> Add trace.
> (CHECK_FP): Likewise.
> (CHECK_CUMULATIVE_SAT): Likewise.
OK, provided no regressions and no new fails for aarch64, aarch64_be and a
On 16 January 2015 at 16:21, Christophe Lyon wrote:
> My existing tests only cover armv7 so far.
> I do plan to expand them once they are all in GCC.
>
>> Otherwise, they look good to me(but I can't approve it).
>>
>> Tejas.
>>
OK provided, as per the previous couple, that we don;t regression or
On 16 January 2015 at 16:23, Christophe Lyon wrote:
> On 16 January 2015 at 15:09, Tejas Belagod wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
>> Hmm.. again, I don't see vld1_lane_f64?
>
> Same answer: unless
On 16 December 2014 at 11:26, Yangfei (Felix) wrote:
> The v3 patch attached fixed this minor issue. Thanks.
> +2014-12-13 Felix Yang
> + Haijian Zhang
> +
> + * gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
> + (buffer_float64x2, buffer_pad_float64x2): New
On 16 January 2015 at 16:54, Kyrill Tkachov wrote:
> 2014-01-16 Kyrylo Tkachov
>
> PR target/64448
> * config/aarch64/aarch64-simd.md (aarch64_simd_bsl_internal):
> Match xor-and-xor RTL pattern.
OK /Marcus
On 16 January 2015 at 17:52, Christophe Lyon wrote:
>> OK provided, as per the previous couple, that we don;t regression or
>> introduce new fails on aarch64[_be] or aarch32.
>
> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
> when the input is -NaN.
> It's a corner case,
On 16 January 2015 at 18:12, Christophe Lyon wrote:
> On 16 January 2015 at 16:20, Tejas Belagod wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
>>>
> Thanks, I should mention that this test fails on aarch64_b
On 13 January 2015 at 15:18, Christophe Lyon wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
OK with the the vmlx poly ops dropped
On 13 January 2015 at 15:18, Christophe Lyon wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file.
OK with Tejas' comment
On 16 January 2015 at 11:17, Jiong Wang wrote:
> exactly, thanks, we should use FAIL although DONE and FAIL work the same in
> this scenario.
>
> I checked their definition, FAIL always return the initial value of _val
> which is NULL,
> while DONE stop and return generated insns which for this p
On 13 January 2015 at 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
OK /Marcus
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