[PATCH] match: Fix A || B not optimized to true when !B implies A [PR114326]

estsuite/ChangeLog: * gcc.dg/tree-ssa/fold-xor-and-or-1.c: New test. * gcc.dg/tree-ssa/fold-xor-and-or-2.c: New test. * gcc.dg/tree-ssa/fold-xor-or-1.c: New test. * gcc.dg/tree-ssa/fold-xor-or-2.c: New test. Reviewed-by: Christoph Müllner Signed-off-by: Philipp Tomsich Signed-of

[PATCH v2] match: Fix A || B not optimized to true when !B implies A [PR114326]

estsuite/ChangeLog: * gcc.dg/tree-ssa/fold-xor-and-or-1.c: New test. * gcc.dg/tree-ssa/fold-xor-and-or-2.c: New test. * gcc.dg/tree-ssa/fold-xor-or-1.c: New test. * gcc.dg/tree-ssa/fold-xor-or-2.c: New test. Reviewed-by: Christoph Müllner Signed-off-by: Philipp Tomsich Signed-of

Re: [PATCH] match: Fix A || B not optimized to true when !B implies A [PR114326]

Thanks, fixed ( https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660631.html). On Thu, Aug 15, 2024 at 3:57 PM Sam James wrote: > Konstantinos Eleftheriou writes: > > > From: kelefth > > > > In expressions like (a != b || ((a ^ b) & CST0) == CST1) and > &

[PATCH v3] match: Fix A || B not optimized to true when !B implies A [PR114326]

and-or.c: New test. * gcc.dg/tree-ssa/fold-xor-or.c: New test. Reviewed-by: Christoph Müllner Signed-off-by: Philipp Tomsich Signed-off-by: Konstantinos Eleftheriou --- gcc/match.pd | 30 ++ .../gcc.dg/tree-ssa/fold-xor-and

Re: [PATCH v2] match: Fix A || B not optimized to true when !B implies A [PR114326]

024 at 4:24 PM Konstantinos Eleftheriou > wrote: > > > > From: kelefth > > > > In expressions like (a != b || ((a ^ b) & CST0) == CST1) and > > (a != b || (a ^ b) == CST), (a ^ b) is folded to false. > > In the equivalent expressions (((a ^ b) & CST0)

[PATCH] match: Change (A * B) + (-C) to (B - C/A) * A, if C multiple of A [PR109393]

. gcc/testsuite/ChangeLog: * gcc.dg/pr109393.c: New test. Tested-by: Christoph Müllner Signed-off-by: Philipp Tomsich Signed-off-by: Konstantinos Eleftheriou --- gcc/match.pd| 15 ++- gcc/testsuite/gcc.dg/pr109393.c | 23 +++ 2 files chang

[PATCH v2] match: Change (A * B) + (-C) to (B - C/A) * A, if C multiple of A [PR109393]

. gcc/testsuite/ChangeLog: * gcc.dg/pr109393.c: New test. Tested-by: Christoph Müllner Signed-off-by: Philipp Tomsich Signed-off-by: Konstantinos Eleftheriou --- gcc/match.pd| 21 - gcc/testsuite/gcc.dg/pr109393.c | 23 +++ 2 files c

Re: [PATCH] match: Change (A * B) + (-C) to (B - C/A) * A, if C multiple of A [PR109393]

regression tested on x86-64 and > aarch64. > > > > PR tree-optimization/109393 > > > > gcc/ChangeLog: > > > > * match.pd: (A * B) + (-C) -> (B - C/A) * A, if C a multiple of > A. > > > > gcc/testsuite/ChangeLog: > >

Re: [PATCH v5] Target-independent store forwarding avoidance.

Sent a new version for this in https://gcc.gnu.org/pipermail/gcc-patches/2024-October/665794.html. Thanks, Konstantinos. On Fri, Aug 30, 2024 at 4:32 PM Richard Sandiford wrote: > > Manolis Tsamis writes: > >> > I could have some help with that, because after the new changes a > >> > subreg rel

[PATCH v6] Target-independent store forwarding avoidance.

-store-forwarding-3.c: New test. * gcc.target/aarch64/avoid-store-forwarding-4.c: New test (XFAIL). * gcc.target/aarch64/avoid-store-forwarding-5.c: New test (XFAIL). Signed-off-by: Philipp Tomsich Signed-off-by: Konstantinos Eleftheriou Series-version: 6 Series-changes: 6

Re: [PATCH v6] Target-independent store forwarding avoidance.

0/18/24 3:57 AM, Konstantinos Eleftheriou wrote: > > From: kelefth > > > > This pass detects cases of expensive store forwarding and tries to avoid > > them > > by reordering the stores and using suitable bit insertion sequences. > > For example it can

[PATCH v7] Target-independent store forwarding avoidance.

-store-forwarding-3.c: New test. * gcc.target/aarch64/avoid-store-forwarding-4.c: New test (XFAIL). * gcc.target/aarch64/avoid-store-forwarding-5.c: New test (XFAIL). Signed-off-by: Philipp Tomsich Signed-off-by: Konstantinos Eleftheriou Series-version: 7 Series-changes: 7

Re: [PATCH v7] Target-independent store forwarding avoidance.

.html). Thanks, Konstantinos. On Sat, Oct 26, 2024 at 5:54 PM Jeff Law wrote: > > > > On 10/23/24 8:27 AM, Konstantinos Eleftheriou wrote: > > From: kelefth > > > > This pass detects cases of expensive store forwarding and tries to avoid > > them > >

[PATCH v8] Target-independent store forwarding avoidance.

Signed-off-by: Konstantinos Eleftheriou Series-version: 8 Series-changes: 8 - Fix store_bit_field call for big-endian targets, where BITS_BIG_ENDIAN is false. - Handle store_forwarding_max_distance = 0 as a special case that disables cost checks for avoid-store

Re: [PATCH v3] match: Fix A || B not optimized to true when !B implies A [PR114326]

fold-xor-and-or.c: New test. > > * gcc.dg/tree-ssa/fold-xor-or.c: New test. > > > > Reviewed-by: Christoph Müllner > > Signed-off-by: Philipp Tomsich > > Signed-off-by: Konstantinos Eleftheriou > > --- > > gcc/match.pd

[PATCH v4] match: Fix A || B not optimized to true when !B implies A [PR114326]

-xor-and-or.c: New test. * gcc.dg/tree-ssa/fold-xor-or.c: New test. Tested-by: Christoph Müllner Signed-off-by: Philipp Tomsich Signed-off-by: Konstantinos Eleftheriou --- gcc/match.pd | 32 ++- .../gcc.dg/tree-ssa/fold-xor-and

Re: [PATCH v3] match: Fix A || B not optimized to true when !B implies A [PR114326]

I have sent a new version (https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663350.html). I also added :c to the ne operations. Thanks, Konstantinos On Wed, Sep 18, 2024 at 1:52 PM Richard Biener wrote: > > On Wed, Sep 18, 2024 at 10:42 AM Konstantinos Eleftheriou > wrote: &

[PATCH] testsuite: Exclude test in pr109393.c from ilp32 targets [PR116845]

From: kelefth The match.pd canonicalization that this testcase checks for, is not applied on ilp32 targets. This prevents the test from running on ilp32 targets. PR116845 gcc/testsuite/ChangeLog: * gcc.dg/pr109393.c: Exclude ilp32 targets. --- gcc/testsuite/gcc.dg/pr109393.c

[PATCH] avoid-store-forwarding: Fix base register initialization when eliminating loads [PR117835]

From: kelefth During the initialization of the base register for the zero-offset store, in the case that we are eliminating the load, we used a paradoxical subreg assuming that we don't care about the higher bits of the register. This led to writing wrong values when we were not updating the whol

[PATCH] avoid-store-forwarding: Reject changes when an instruction may throw [PR117816]

From: kelefth Avoid-store-forwarding doesn't handle the case where an instruction in the store-load sequence contains a REG_EH_REGION note, leading to the insertion of instructions after it, while it should be the last instruction in the basic block. This causes an ICE when compiling using `-O -f

[PATCH] match: Change (A + CST0) * CST1 to (A + sign_extend(CST0)) * CST1 [PR116845]

From: kelefth `(A * B) + (-C) to (B - C/A) * A` fails to match on ILP32 targets due to the upper bits of CST0 being zeros in some cases. This patch adds the following pattern in match.pd: (A + CST0) * CST1 -> (A + CST0') * CST1, where CST1 is a power of 2 constant and CST0' is CST0 with the log2

[PATCH] Move COMP/XOR optimization from match.pd into reassoc [PR116860]

Testcases for patterns `((a ^ b) & c) cmp d | a != b -> (0 cmp d | a != b)` and `(a ^ b) cmp c | a != b -> (0 cmp c | a != b)` were failing on some targets, like PowerPC. This patch moves the optimization to reassoc. Doing so, we can now handle cases where the related conditions appear in an AND e

[PATCH v3] reassoc: Optimize CMP/XOR expressions [PR116860]

Testcases for match.pd patterns `((a ^ b) & c) cmp d | a != b -> (0 cmp d | a != b)` and `(a ^ b) cmp c | a != b -> (0 cmp c | a != b)` were failing on some targets, like PowerPC. This patch adds an implemenetation for the optimization in reassoc. Doing so, we can now handle cases where the relate

Re: [PATCH v2] reassoc: Optimize CMP/XOR expressions [PR116860]

On Sun, Mar 16, 2025 at 8:42 PM Sam James wrote: > > Hans-Peter Nilsson writes: > > > On Thu, 13 Mar 2025, Konstantinos Eleftheriou wrote: > >> Testcases for match.pd patterns > >> `((a ^ b) & c) cmp d | a != b -> (0 cmp d | a != b)` and > >> `(

[PING][PATCH] doc: Clarify REG_EH_REGION note usage

Hi, Just a ping for https://gcc.gnu.org/pipermail/gcc-patches/2025-March/677635.html. Thanks, Konstantinos

[PING][PATCH v3] reassoc: Optimize CMP/XOR expressions [PR116860]

Hi, Just a ping for https://gcc.gnu.org/pipermail/gcc-patches/2025-March/677788.html . Thanks, Konstantinos

[PATCH] doc: Clarify REG_EH_REGION note usage

The documentation for the REG_EH_REGION could easily be read (especially by non-native speakers) to indicate that it should be attached to insn at the destination of an excpetion edge. Despite the original text saying that the note "specifies the destination," it is actually always attached to the

Re: [PATCH] asf: Enable pass at O2 or higher

We have sent a new version for this, with updated testcases (https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681606.html). Thanks, Konstantinos On Wed, Jan 29, 2025 at 8:32 PM Richard Sandiford wrote: > > Christoph Müllner writes: > > The avoid-store-forwarding pass is disabled by default

[PATCH v2] asf: Enable pass at O2 or higher

The avoid-store-forwarding pass is disabled by default and therefore in the risk of bit-rotting. This patch addresses this by enabling the pass at O2 or higher. The assembly patterns in `bitfield-bitint-abi-align16.c` and `bitfield-bitint-abi-align8.c` have been updated to account for the asf tra

Re: [PATCH] asf: Enable pass at O2 or higher

Hi Andi, thanks for your response. The pass prevents store forwarding only in cases where smaller stores are followed by a large load. To the best of our knowledge, on most CPUs, the load will stall in that case. Have you taken that into account? Thanks, Konstantinos On Wed, Apr 23, 2025 at 6:55

[PATCH] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

During the base register initialization, when we are eliminating the load instruction, we were calling `emit_move_insn` on registers of the same size but of different mode in some cases, causing an ICE. This patch fixes this, by adding a check for the modes to match before calling `emit_move_insn`

Re: [PATCH] testsuite: Skip pr119160 for RISC-V backend.

Hi, This should be restricted to arm/aarch64 and x86. So it should be: /* { dg-additional-options "-mgeneral-regs-only" { target { x86_64-*-* i?86-*-* aarch64*-*-* arm*-*-* } } } */ Konstantinos On Thu, May 8, 2025 at 11:36 AM jiawei wrote: > > > 在 2025/5/8 16:25, Richard Biener 写道: > > On Thu,

[PATCH] avoid-store-forwarding: Handle REG_EH_REGION notes

From: kelefth The pass rejects the transformation when there are instructions in the sequence that might throw an exception. This was added due to having cases that the load instruction contains a REG_EH_REGION note and moving it before the store instructions caused an error, as it was no longer

Re: [PATCH] Move COMP/XOR optimization from match.pd into reassoc [PR116860]

On Mon, Mar 10, 2025 at 7:52 AM Konstantinos Eleftheriou > wrote: > > > > Testcases for patterns `((a ^ b) & c) cmp d | a != b -> (0 cmp d | a != b)` > > and `(a ^ b) cmp c | a != b -> (0 cmp c | a != b)` were failing on some > > targets, like PowerPC. > >

[PATCH v2] reassoc: Optimize CMP/XOR expressions [PR116860]

Testcases for match.pd patterns `((a ^ b) & c) cmp d | a != b -> (0 cmp d | a != b)` and `(a ^ b) cmp c | a != b -> (0 cmp c | a != b)` were failing on some targets, like PowerPC. This patch adds an implemenetation for the optimization in reassoc. Doing so, we can now handle cases where the relate

Re: [PATCH] avoid-store-forwarding: Handle REG_EH_REGION notes

Hi Richard, thanks for the feedback. On Tue, Feb 18, 2025 at 9:17 PM Richard Biener wrote: > > > > > Am 18.02.2025 um 17:04 schrieb Konstantinos Eleftheriou > > : > > > > From: kelefth > > > > The pass rejects the transformation when there are inst

[PATCH] avoid-store-forwarding: Fix reg init on load-elimination [PR119160]

In the case that we are eliminating the load instruction, we use zero_extend for the initialization of the base register for the zero-offset store. This causes issues when the store and the load use the same mode, as we are trying to generate a zero_extend with the same inner and outer modes. This

[PATCH v2] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

During the base register initialization, when we are eliminating the load instruction, we were calling `emit_move_insn` on registers of the same size but of different mode in some cases, causing an ICE. This patch uses `lowpart_subreg` for the base register initialization, instead of zero-extendin

Re: [PATCH] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

->offset`, that's actually the offset difference between the store and the load (we're trying to find the store with the same offset as the load), so the endianness should be irrelevant in that case. Konstantinos On Tue, Apr 29, 2025 at 8:48 PM Richard Sandiford wrote: > > Konst

Re: [PATCH v3 2/3] sbitmap: Add bitmap_is_range_set_p function

Hi Richard, thanks for your response. On Tue, May 20, 2025 at 8:05 AM Richard Biener wrote: > > On Mon, May 19, 2025 at 4:14 PM Konstantinos Eleftheriou > wrote: > > > > This patch adds the `bitmap_is_range_set_p` function in sbitmap, > > which checks if all the bi

[PATCH v3 2/3] sbitmap: Add bitmap_is_range_set_p function

et_p): New function. Signed-off-by: Konstantinos Eleftheriou --- (no changes since v1) gcc/sbitmap.cc | 27 --- gcc/sbitmap.h | 1 + 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/gcc/sbitmap.cc b/gcc/sbitmap.cc index 94f2bbd6c8fd..99f1db540ab6 100644

[PATCH v3 0/3] asf: Fix ICE on emit_move_insn [PR119884]

_insn`. Konstantinos Eleftheriou (3): sbitmap: Add bitmap_bit_in_range_p_1 helper function sbitmap: Add bitmap_is_range_set_p function asf: Fix calling of emit_move_insn on registers of different modes [PR119884] gcc/avoid-store-forwarding.cc| 45 ++-- gcc/sbitm

[PATCH v3 1/3] sbitmap: Add bitmap_bit_in_range_p_1 helper function

: * sbitmap.cc (bitmap_bit_in_range_p): Call `bitmap_bit_in_range_p_1`. (bitmap_bit_in_range_p_1): New function. Signed-off-by: Konstantinos Eleftheriou --- (no changes since v1) gcc/sbitmap.cc | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/gcc/sbitmap.cc b

[PATCH v3 3/3] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

tore_forwarding): Use `lowpart_subreg` for the base register initialization, and remove redundant stores from the store/load sequence. gcc/testsuite/ChangeLog: * gcc.target/i386/pr119884.c: New test. Signed-off-by: Konstantinos Eleftheriou --- Changes in v3: - Remove r

Re: [PATCH v2] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

set. It could be done in other ways, but this seems cleaner. On Thu, May 8, 2025 at 5:55 PM Richard Sandiford wrote: > > Konstantinos Eleftheriou writes: > > During the base register initialization, when we are eliminating the load > > instruction, we were calling `emit_move_ins

[PING][PATCH v3] reassoc: Optimize CMP/XOR expressions [PR116860]

Ping for https://gcc.gnu.org/pipermail/gcc-patches/2025-March/677788.html . Thanks, Konstantinos

Re: [PATCH] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

On Wed, May 7, 2025 at 11:29 AM Richard Sandiford wrote: > > Konstantinos Eleftheriou writes: > > Hi Richard, > > > > Thanks for the feedback! We have sent a new version that uses > > lowpart_subreg > > (https://gcc.gnu.org/pipermail/gcc-patches/2025-May

[PATCH] expmed: Prevent non-canonical subreg generation in store_bit_field [PR118873]

In `store_bit_field_1`, when the value to be written in the bitfield and/or the bitfield itself have vector modes, non-canonical subregs are generated, like `(subreg:V4SI (reg:V8SI x) 0)`. If one them is a scalar, this happens only when the scalar mode is different than the vector's inner mode. Th

[COMMITTED PATCH v4 1/3] sbitmap: Rename bitmap_bit_in_range_p to bitmap_any_bit_in_range_p

function name. * tree-ssa-dse.cc (live_bytes_read): Updated function call to use the new name. Signed-off-by: Konstantinos Eleftheriou --- (no changes since v1) gcc/sbitmap.cc | 109 ++-- gcc/sbitmap.h | 5 +- gcc/tree-ssa-dse.cc

[COMMITTED PATCH v4 3/3] asf: Fix calling of emit_move_insn on registers of different modes [PR119884]

tore_forwarding): Use `lowpart_subreg` for the base register initialization and remove redundant stores from the store/load sequence. gcc/testsuite/ChangeLog: * gcc.target/i386/pr119884.c: New test. Signed-off-by: Konstantinos Eleftheriou --- Changes in v4: - Merged previ

[COMMITTED PATCH v4 2/3] sbitmap: Add bitmap_all_bits_in_range_p function

lt of `bitmap_bit_in_range_p` with the `any_inverted` parameter set to false. (bitmap_bit_in_range_p): New function. (bitmap_all_bits_in_range_p): New function. * sbitmap.h (bitmap_all_bits_in_range_p): New function. Signed-off-by: Konstantinos Eleftheriou --- Changes

[COMMITTED PATCH v4 0/3] asf: Fix ICE on emit_move_insn [PR119884]

et as the load. Changes in v1: - Add a check for the register modes to match before calling `emit_mov_insn`. Konstantinos Eleftheriou (3): sbitmap: Rename bitmap_bit_in_range_p to bitmap_any_bit_in_range_p sbitmap: Add bitmap_all_bits_in_range_p function asf: Fix calling of emit_move_in

Re: [PATCH] expmed: Prevent non-canonical subreg generation in store_bit_field [PR118873]

Hi Richard, thanks for the response. On Mon, May 26, 2025 at 11:55 AM Richard Biener wrote: > > On Mon, 26 May 2025, Konstantinos Eleftheriou wrote: > > > In `store_bit_field_1`, when the value to be written in the bitfield > > and/or the bitfield itself have vector modes,