committed, thanks!
On Tue, Jan 31, 2023 at 9:00 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/vsra_vv-1.C: New test.
> * g++.target/riscv/rvv/base/vsra_vv-2.C: New test.
> * g++.target/riscv/rvv/base/vsra_vv-3.C: New test.
>
> > Thank you so much. Kito helped me fix it already.
> > RVV instruction patterns can have CSE optimizations now.
> What was the issue?
VL and VTYPE isn't listed in fixed register so CSE feel that isn't
cheap (See CHEAP_REGNO in cse.cc),
but actually it's kind of mistake sett for VL and VTYPE reg
committed, also updated mask for ALL_REGS, thanks.
On Fri, Feb 3, 2023 at 12:59 PM Monk Chiang wrote:
>
> Avoid VL_REGS, VTYPE_REGS join register allocation.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
> * config/riscv/riscv.cc: Ditto.
> ---
>
committed, thanks!
On Wed, Feb 1, 2023 at 6:11 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vsra_vx-1.c: New test.
> * gcc.target/riscv/rvv/base/vsra_vx-2.c: New test.
> * gcc.target/riscv/rvv/base/vsra_vx-3.c: New test.
>
committed, thanks!
On Wed, Feb 1, 2023 at 6:10 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vsrl_vx-1.c: New test.
> * gcc.target/riscv/rvv/base/vsrl_vx-2.c: New test.
> * gcc.target/riscv/rvv/base/vsrl_vx-3.c: New test.
>
committed, thanks!
On Wed, Feb 1, 2023 at 6:18 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/vsrl_vx-1.C: New test.
> * g++.target/riscv/rvv/base/vsrl_vx-2.C: New test.
> * g++.target/riscv/rvv/base/vsrl_vx-3.C: New test.
>
committed, thanks!
On Wed, Feb 1, 2023 at 6:20 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/vsra_vx-1.C: New test.
> * g++.target/riscv/rvv/base/vsra_vx-2.C: New test.
> * g++.target/riscv/rvv/base/vsra_vx-3.C: New test.
>
committed, thanks!
On Wed, Feb 1, 2023 at 9:48 AM wrote:
>
> From: Ju-Zhe Zhong
>
> Current constraint configuration will generate:
> vadd.vv v0,v24,v25,v0.t
> vsll.vx v0,v24,a5,v0.t
>
> They are incorrect according to RVV ISA.
> This patch fix this obvious issue.
>
> gcc/ChangeLog:
>
>
committed, thanks!
On Wed, Feb 1, 2023 at 6:08 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/predicates.md (pmode_reg_or_uimm5_operand): New
> predicate.
> * config/riscv/riscv-vector-builtins-bases.cc: New class.
> * config/riscv/riscv-vector-bu
committed, thanks!
On Wed, Feb 1, 2023 at 6:15 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test.
>
> ---
> .../riscv/rvv/base/shift_vx_constraint-1.c| 133 ++
> 1 file changed, 133 inserti
gcc/ChangeLog:
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
(DWARF_FRAME_REGISTERS): New.
(DWARF_REG_TO_UNWIND_COLUMN): New.
libgcc/ChangeLog:
* config.host (riscv*-*-*): Add config/riscv/value-unwind.h.
* config/riscv/value-unwind.h: New.
---
gcc/con
Committed, thanks :)
On Fri, Feb 3, 2023 at 5:45 PM Jin Ma via Gcc-patches
wrote:
>
> The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain
> potential risks:
>
> When the architecture adds pre-processing to `define_insn "adddi3"`, such as
> `define_expend "adddi3"`, the g
committed :)
On Sun, Feb 12, 2023 at 10:42 PM wrote:
>
> LGTM
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-02-12 19:33
> To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong
> CC: Kito Cheng
> Subject: [PATCH] RISC-V:
Committed, Thanks for fixing my stupid bug :P
On Wed, May 25, 2022 at 9:26 PM Simon Cook wrote:
>
> This solves an issue where rv32i, etc. are canonicalized to rv32imafd
> since the g->i addition of 'm', 'a', 'f', 'd' is not actually gated by
> whether the input was rv32g/rv64g.
>
> gcc/ChangeLo
LGTM, thanks :)
On Thu, May 26, 2022 at 10:31 AM Palmer Dabbelt wrote:
>
> gcc/ChangeLog
>
> * doc/invoke.texi (RISC-V): Document -mtune=thead-c906.
>
> Signed-off-by: Palmer Dabbelt
> ---
> gcc/doc/invoke.texi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc
Back ported to releases/gcc-11 and releases/gcc-12 branch :)
On Thu, May 26, 2022 at 5:33 AM Palmer Dabbelt wrote:
>
> On Wed, 25 May 2022 07:00:11 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> > Committed, Thanks for fixing my stupid bug :P
>
> IMO this is a good candidate for a backport.
>
> >
Hi Simon:
Good catch, those cache operations should take an address operand.
On Thu, May 26, 2022 at 7:58 PM Simon Cook wrote:
>
> Hi,
>
> I've just tried using these builtins now these have landed in trunk, and
> I have a question about the cbo builtins.
>
> Looking at the code being generate
Committed, thanks!
On Fri, May 27, 2022 at 10:37 AM Vineet Gupta wrote:
>
> Commit 9ddd44b58649d1d ("RISC-V: Provide `fmin'/`fmax' RTL pattern") added
> tests which check for hard float instructions which obviously fails on
> soft-float ABI builds.
>
> And my recent commit b646d7d279ae ("RISC-V:
I just hesitated for a few days about backporting this, but I think
it's OK to back port because
1. Simple enough
2. Good for general RISC-V core
Committed with your latest testsuite fix.
Thanks!
On Wed, May 25, 2022 at 3:38 AM Vineet Gupta wrote:
>
>
>
> On 5/24/22 00:59,
OK to back port, thanks!
On Thu, Jun 2, 2022 at 4:46 PM Philipp Tomsich wrote:
>
> OK for backport?
>
> Thanks,
> Phil.
>
> On Fri, 13 May 2022 at 22:23, Philipp Tomsich
> wrote:
>
> > Added the two nits from Kito's review and … Applied to trunk!
> >
> >
> > On Fri, 13 May 2022 at 22:16, Philipp
LGTM
On Mon, May 30, 2022 at 5:52 AM Philipp Tomsich
wrote:
>
> The SINGLE_BIT_MASK_OPERAND() is overly restrictive, triggering for
> bits above 31 only (to side-step any issues with the negative SImode
> value 0x8000/(-1ull << 31)/(1 << 31)). This moves the special
> handling of this SImode
On Mon, Jun 6, 2022 at 3:29 PM wrote:
>
> From: yulong
>
> We changed the RTL mode and builtins format about zicbom and zicboz
> subextensions.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed
> "RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
> *
On Tue, Jun 7, 2022 at 4:04 PM wrote:
>
> From: yulong
>
> We changed builtins format about zicbom and zicboz subextensions and added
> test cases.
> diff with the previous version:
> 1.We deleted the RLT mode's second input operand.
> 2.We modified the type of builtins from RISCV_BUILTIN_DIRECT
On Wed, May 25, 2022 at 5:47 AM Philipp Tomsich
wrote:
>
> The current method of treating shifts of extended values on RISC-V
> frequently causes sequences of 3 shifts, despite the presence of the
> 'zero_extendsidi2_shifted' pattern.
>
> Consider:
> unsigned long f(unsigned int a, unsigned lo
LGTM, you can commit that without [3/3] if you like :)
On Wed, May 25, 2022 at 5:47 AM Philipp Tomsich
wrote:
>
> When encountering a prescaled (biased) value as a candidate for
> sh[123]add.uw, the combine pass will present this as shifted by the
> aggregate amount (prescale + shift-amount) with
LGTM
On Wed, May 25, 2022 at 5:48 AM Philipp Tomsich
wrote:
>
> Provide an easy way to constrain for constants that are a a single,
> consecutive run of ones.
>
> gcc/ChangeLog:
>
> * config/riscv/predicates.md (consecutive_bits_operand):
> Implement new predicate.
>
> Signed-o
> OK for backport?
OK, it seems no issue after a week :)
>
> On Thu, 2 Jun 2022 at 21:23, Philipp Tomsich wrote:
> >
> > Thanks, applied to trunk!
> >
> > On Thu, 2 Jun 2022 at 15:17, Kito Cheng wrote:
> > >
> > > LGTM
> > >
> &
so I prefer to use another pseudo here if possible.
That's also what AArch64/ARM/x86 port did - use new pseudo as tmp if possible.
On Tue, Jun 7, 2022 at 6:50 PM Philipp Tomsich wrote:
>
> On Tue, 7 Jun 2022 at 12:24, Kito Cheng wrote:
> >
> > On Wed, May 25, 202
I also prefer adding a -mabi=auto option rather than change existing behavior.
On Wed, Jun 8, 2022 at 5:06 PM pc.wang via Gcc-patches
wrote:
>
> Thanks for your opinion! I did these just because LLVM has already done the
> same thing and I wanted to make GCC with the same behavior of LLVM. The o
LGTM, *f_quiet4_default and
*f_quiet4_snan has set their own
length and the only user of this setting is
*cstore4, but apparently the length if 4 for that
not 8.
Thanks!
On Thu, Jun 9, 2022 at 9:36 PM Maciej W. Rozycki wrote:
>
> The default length for floating-point compare operations is overri
Thanks :)
On Thu, Jun 9, 2022 at 9:35 PM Maciej W. Rozycki wrote:
>
> Consistently use a tab rather than a space as the separator between the
> assembly instruction mnemonic and its operand with FSFLAGS instructions
> produced with the unordered FP comparison RTL insns.
>
> gcc/
>
Committed with a minor commit log fix, thanks!
>
> In rv32 regression test, this cases will report an error:
>
> "cc1: error: ABI requires '-march=rv32'"
>
> Add '-mabi' option will fix this.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/pr105666.c: New options.
^^^ here should be a
LGTM, thanks for correcting the comments !
On Wed, Jun 15, 2022 at 7:47 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The current description of RISCV_CORE() does not match the
> implementation. This commit provides a fix for that.
>
> gcc/ChangeLog:
>
> * config/riscv/ris
LGTM, thanks!
On Wed, Jun 15, 2022 at 7:48 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
> The C906 is shipped for quite some time (it is the core of the Allwinner D1).
> Note, that the tuning struct for t
Hi Andreas:
Fixed via
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d6b423882a05d7b4f40ae1e9d942c9c4c13761b7,
thanks!
On Fri, Jun 17, 2022 at 4:34 PM Andreas Schwab wrote:
>
> ../../gcc/config/riscv/bitmanip.md: In function 'rtx_insn*
> gen_split_44(rtx_ins\
> n*, rtx_def**)':
> ../../gcc/conf
Generally I agree we should fix that by GCC driver rather than ld
emulation, but I think this should be reverted with the -L path fix,
otherwise that will break multilib on GNU toolchain for linux
immediately?
On Wed, Jun 15, 2022 at 4:00 PM Fangrui Song via Gcc-patches
wrote:
>
> This reverts co
Committed, thanks!
On Wed, Jun 8, 2022 at 10:20 AM wrote:
>
> From: yulong
>
> We changed builtins format about zicbom and zicboz subextensions and modified
> test cases.
> diff with the previous version:
> 1.We modified the FUNCTION_TYPE from RISCV_VOID_FTYPE_SI/DI to
> RISCV_VOID_FTYPE_VOID_
ut this hack add an extra use of fflags to prevent FFLAGS getting
CSEed, patch attached.
From 1116422bb5a69d8361f5c5bc334a122fecbaa306 Mon Sep 17 00:00:00 2001
From: Kito Cheng
Date: Fri, 24 Jun 2022 00:41:55 +0800
Subject: [PATCH] model fflags
---
gcc/config/riscv/riscv.h | 12 +-
No feedback for 2 weeks, and we already verified this with our
internal CI system for a while, so I go ahead committed to trunk now.
On Fri, Mar 5, 2021 at 12:48 PM Kito Cheng wrote:
>
> From: Sinan Lin
>
> Third operand of cpymem pattern is unsigned HOST_WIDE_INT, however we
>
Hi Marcus:
Thank you for digging this issue out, I would suggest you sent v4
patch which only v3 + riscv_subword fix, and then merge into master
first, and then sent separate patch for that issue, not sure what your
fix, but I guess it might fix some code for IRA/LRA, so I think has a
separate pat
Hi Marcus:
Verified with spike for rv32be and rv64be.
Committed to trunk, appreciate your work on this, RISC-V big-endian
support just reached a great milestone today!
On Sat, Mar 20, 2021 at 3:50 AM Marcus Comstedt wrote:
>
> New update of the RISC-V big endian support.
>
> Changes since v3:
>
committed with few tweaks.
On Wed, Mar 24, 2021 at 11:21 AM Kito Cheng wrote:
>
> ---
> htdocs/gcc-11/changes.html | 32 +++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.htm
Thanks, committed :)
On Mon, Jun 21, 2021 at 8:44 PM Jojo R via Gcc-patches
wrote:
>
> gcc/
> * config/riscv/riscv.c (thead_c906_tune_info): New.
> * config/riscv/riscv.c (riscv_tune_info_table): Use new tune.
> ---
> gcc/config/riscv/riscv.c | 14 ++
> 1 file
> So the idea here is just to define the extension so that it gets defined
> in the ISA strings and passed through to the assembler, right?
That will also define arch test marco:
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro
On Mon,
> @@ -464,6 +464,60 @@
>[(set_attr "type" "arith")
> (set_attr "mode" "DI")])
>
> +(define_expand "add3"
> + [(set (match_operand:GPR 0 "register_operand" "=r,r")
> + (plus:GPR (match_operand:GPR 1 "register_operand" " r,r")
> + (match_operand:GPR
> > I would like to have a unified option interface,
> > maybe -m[no-]inline-str[n]cmp and -minline-str[n]cmp-limit.
>
> For the basic option (-m[no-]inline-str[n]cmp), I would punt to
> -fno-builtin-str[n]cmp.
-fno-bulitin-* will also suppress middle-end optimization for those builtins.
see:
htt
LGTM, thanks :)
On Wed, Nov 23, 2022 at 7:21 AM Jeff Law wrote:
>
> As Jaiwei noted, many (all?) of the rvv/base/spill tests started failing
> after the introduction of shrink-wrapping.
>
>
> The core issue is we're expecting the frame to have a constant size, but
> it doesn't. So when using the
Actually, I am strongly support those stuff keep merge to trunk until
February, my goal is intrinsic support for vector, but not including any
vectorization like SLP or Loop vectorization, the most critical part is the
vsetvli which is the mode switching, and its almost done.
Those part is kind of
> >>> Yeah, I personally want to support RVV intrinsics in GCC13. As RVV
> >>> intrinsic is going to release soon next week.
> >>
> >> OK, that's fine with me -- I was leaning that way, and I think Jeff only
> >> had a weak opposition. Are there any more changes required outside the
> >> RISC-V ba
LGMT, and as we discussed in another patch[1], I support RVV related
stuff to keep merge for this moment
and we agreed that it is not ideal but acceptable, so committed to trunku :)
[1]
https://patchwork.ozlabs.org/project/gcc/patch/20221128141406.242953-1-juzhe.zh...@rivai.ai/
On Tue, Nov 29, 2
LGTM, and committed to trunk!
On Tue, Nov 29, 2022 at 4:54 PM Kito Cheng wrote:
>
> > >>> Yeah, I personally want to support RVV intrinsics in GCC13. As RVV
> > >>> intrinsic is going to release soon next week.
> > >>
> > >> OK, that&#
OK, thanks :)
On Fri, Dec 2, 2022 at 5:21 PM Alexandre Oliva via Gcc-patches
wrote:
>
>
> Like other platforms, riscv hits the uninitialized warning because the
> optimizations don't eliminate the nonviable path that would enable it
> to be omitted.
>
> Regstraped on x86_64-linux-gnu, also tested
OK, thanks!
On Fri, Dec 2, 2022 at 5:24 PM Alexandre Oliva via Gcc-patches
wrote:
>
>
> On riscv64, despite being lp64, we choose two IV candidates as on arm,
> which prevents some of the expected sinking. Add an xfail for it.
>
> Regstraped on x86_64-linux-gnu, also tested with crosses to riscv
wondering
> what the reason was to downgrade current FMV.X.W and FMW.W.X instructions
> to their older FMV.S.W and FMV.W.S variants here:
>
> On Wed, 10 Aug 2022, Kito Cheng wrote:
>
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 5a0adffb5
Hi ShiHua:
Thanks for the fix, committed with Andrew's comment and minor fix for
commit comment.
On Thu, Dec 23, 2021 at 3:41 PM Andrew Pinski via Gcc-patches
wrote:
>
> On Wed, Dec 22, 2021 at 11:37 PM wrote:
> >
> > From: LiaoShihua
> >
> > because riscv32 not support __int128, so sk
Committed
On Fri, Dec 3, 2021 at 11:51 PM Kito Cheng wrote:
>
> RISC-V spec only allow alphabetical name for extension before, however
> vector extension add several extension named with digits, so we try to
> extend the naming rule.
>
> Ref:
> https://github.com/riscv/risc
Committed with minor changelog fix
On Fri, Dec 3, 2021 at 11:52 PM Kito Cheng wrote:
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.c (riscv_implied_info): Add
> vector extensions.
> (riscv_ext_version_table): Add version info for
Committed with commit log tweak:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=02880e7803b19c357718abd2f0d567b4a761f318
On Wed, Mar 15, 2023 at 11:06 AM juzhe.zh...@rivai.ai
wrote:
>
> Yes, I have write access. However, I am new to commit patch to GCC trunk.
> I didn't figure out how to commit pa
Committed with git log tweak:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c413abed869e7e34a86855a015413418f3c6b595
On Mon, Mar 13, 2023 at 3:52 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Co-authored-by: kito-cheng
> Co-authored-by: kito-cheng
>
> This patch fixed a bunc
committed as
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=116a8678840f9f52ec14639ff07e302a8c429f32
with few comment tweak.
On Wed, Mar 22, 2023 at 1:06 PM wrote:
>
> From: Ju-Zhe Zhong
>
> This patch fix PR109228
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228
>
> gcc/ChangeLog:
>
>
Committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=cd0c433e5faba9a18f64881cd761a53a530aa798
with comment tweak.
On Wed, Mar 22, 2023 at 10:50 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
> (e
LGTM, but pending this to the GCC 14 queue.
On Wed, Mar 22, 2023 at 8:16 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Current expansion of vmsge will make RA produce redundant vmv1r.v.
>
> testcase:
> void f1 (void * in, void *out, int32_t x)
> {
> vbool32_t mask = *(vbool32_t*)in;
> asm volatil
committd as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a481eed8fd01837cdf011ea9a17853505080a888
with comment tweaks
On Mon, Mar 20, 2023 at 12:30 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (eliminate_insn): Fix bugs.
> (insert_vsetv
committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0e2715176df3787d1470d7b9bde26b1b5e16e1e2
On Mon, Mar 20, 2023 at 8:51 AM juzhe.zh...@rivai.ai
wrote:
>
> The last patch. Kito is still keep testing with pressure tests.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Jeff Law
> Date: 2023-03-20 0
committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6f6eba35b9f06d35ff7bea81969fe905a5584bdc
On Fri, Mar 10, 2023 at 4:09 PM wrote:
>
> From: Ju-Zhe Zhong
>
> vfrsub_vf_m.cpp: In function 'int main()':
> vfrsub_vf_m.cpp:5:43: error: invalid argument to built-in function
>5 | vbool3
Nice catch, committed to the trunk!
On Tue, Mar 21, 2023 at 3:39 PM Songhe Zhu wrote:
>
> The arch 'rv32imac' will not be created when excuting
> './multilib-generator rv32imc-ilp32--a'
>
> The output is:
> MULTILIB_OPTIONS = march=rv32imc mabi=ilp32
> MULTILIB_DIRNAMES = rv32imc ilp32
> MULTILIB
committed, thanks for the reminder :)
On Mon, Mar 13, 2023 at 9:40 AM Li, Pan2 via Gcc-patches
wrote:
>
> Kindly reminder for this PR. Thank you all in advance.
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, March 8, 2023 7:31 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juz
Committed 2 weeks ago but apparently I didn't send mail to say that,
thanks Vineet.
On Thu, Mar 2, 2023 at 3:56 AM Philipp Tomsich wrote:
>
> On Wed, 1 Mar 2023 at 20:53, Vineet Gupta wrote:
> >
> > This showed up as dynamic icount regression in SPEC 531.deepsjeng with
> > upstream
> > gcc (vs.
HI Jiawei:
Thanks for the fix!
Two comments:
- Could you add testcase like
https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/arch-12.c
- And I would prefer those check happened in riscv_subset_list::parse
@gcc/common/config/riscv/riscv-common.cc
On Sun, Mar 26, 2023 at
OK for trunk, thanks :)
On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> This patch adds missing mode specifiers for XTheadMemPair INSNs.
>
> gcc/ChangeLog:
> PR target/109296
> * config/riscv/thead.md: Add mis
RVV intrinsic has defined a macro to identity the version of RVV
intrinsic spec, we missed that before, thanksful we are catch this
before release.
gcc/ChangeLog:
PR target/109312
* config/riscv/riscv-c.cc (riscv_ext_version_value): New.
(riscv_cpu_cpp_builtins): Define __
I would prefer those checking happened in
riscv_subset_list::parse@gcc/common/config/riscv/riscv-common.cc that
could be reused when we adding target attribute.
And I plan integrate the arch-canonicalize script to just reusing
whole arch string parser in GCC 14, so it would be great to have all
ch
k one char when the pointer moving, So I still keep the
> implement
> by check the extenstison with target. Maybe we can add new check function in
> the new
> version :)
>
>
> > -原始邮件-
> > 发件人: "Kito Cheng"
> > 发送时间: 2023-03-27 16:15:00 (星期一
Applied to trunk :)
於 2023年3月28日 週二，22:34寫道：
> LGTM。
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-03-28 22:26
> To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong;
> jeffreyalaw
> CC: Kito Cheng
> Subject: [PATCH
x extension, so we just need to check f with zfinx extension
> as the base case.
>
> Co-Authored by: Kito Cheng
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> * New check.
>
> gcc/testsuite/ChangeLog:
&g
gcc/ChangeLog:
PR target/109328
* config/riscv/t-riscv: Add missing dependencies.
Co-authored-by: Andrew Pinski
---
gcc/config/riscv/t-riscv | 43
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/gcc/config/riscv/t-riscv b/
Committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=802ab7d0db5b5aa46edc8d82526d97258c599927
, thanks
On Wed, Mar 29, 2023 at 10:48 AM wrote:
>
> From: Juzhe-Zhong
>
> Co-authored-by: kito-cheng
> Co-authored-by: kito-cheng
>
> This path fix ICE of ternary int
Commit as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=db4f7a9b47d148b5074ac15910124c746fb7a96f
with more commit log
On Wed, Mar 29, 2023 at 10:43 AM wrote:
>
> From: Juzhe-Zhong
>
> bug.C:144:2: error: unrecognizable insn:
> 144 | }
> | ^
> (insn 684 683 685 26 (set (reg:SI 513)
>
ok, thanks!
On Tue, Apr 4, 2023 at 5:01 PM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> The following patch unbreaks riscv bootstrap, where it previously failed
> on -Werror=format-diag warning promoted to error.
>
> Ok for trunk?
>
> Or shall it say e.g.
> "%<-march=%s%>: % extension conflic
LGTM, thanks :)
On Thu, Apr 6, 2023 at 5:46 PM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> I've noticed
> make: Circular build/genrvv-type-indexer.o <- gtype-desc.h dependency dropped.
>
> The following patch fixes that. The RTL_BASE_H variable includes a lot of
> headers which the generato
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..90c69b52bb4 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -43,6 +43,7 @@
> #include "optabs.h"
> #include "tm-constrs.h"
> #include "rtx-vector-builder.h"
> +#include
You included asm output by accidently :P
On Thu, Apr 6, 2023 at 10:45 PM wrote:
>
> From: Juzhe-Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/rvv.exp: Add testing for RVV
> auto-vectorization.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
>
Is changes for riscv-vsetvl.cc necessary for autovec? or is it
additional optimization for the autovec use case? I would suggest
splitting that if it's later one.
And plz split out fixed-vlmax part into separated patch, that would be
easier to review.
On Thu, Apr 6, 2023 at 10:44 PM wrote:
>
> F
Generally LGTM, just one more comment :)
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..aad046240ee 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl)
> }
> }
>
> > Do you need to save/restore the vector configuration before and after
> > clearing the vector registers?If so, that seems to be missing. If
> > not, it seems like a comment explaining why would be useful.
>
> I'll add some comments in the code and want to explain here first.
> We need not
Let me give more explanation why RISC-V vector need so many modes than AArch64.
The following will use "RVV" as an abbreviation for "RISC-V Vector"
instructions.
There are two key points here:
- RVV has a concept called LMUL - you can understand that as register
grouping, we can group up to 8 ad
get/riscv/zero-scratch-regs-1.c: New test.
> > * gcc.target/riscv/zero-scratch-regs-2.c: New test.
> > * gcc.target/riscv/zero-scratch-regs-3.c: New test.
> >
> > Signed-off-by: Yanzhang Wang
> > Co-authored-by: Pan Li
> > Co-authore
Hi Richard:
> > In order to model LMUL in backend, we have to the combination of
> > scalar type and LMUL; possible LMUL is 1, 2, 4, 8, 1/2, 1/4, 1/8 - 8
> > different types of LMUL, and we'll have QI, HI, SI, DI, HF, SF and DF,
> > so basically we'll have 7 (LMUL type) * 7 (scalar type) here.
>
>
> > The concept of fractional LMUL is the same as the concept of AArch64's
> > partial SVE vectors,
> > so they can only access the lowest part, like SVE's partial vector.
> >
> > We want to spill/restore the exact size of those modes (1/2, 1/4,
> > 1/8), so adding dedicated modes for those partial
OK for trunk, but plz improve the coverage of the testcase, e.g.
vint16mf4_t has fixed too but not tested in testcase.
On Wed, Apr 12, 2023 at 7:09 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Fix supporting data type according to RVV ISA.
> For vint64m*_t, we should only allow them in zve64* instead of
Thanks for the quick response! verified and pushed to trunk.
On Wed, Apr 12, 2023 at 9:56 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Fix supporting data type according to RVV ISA.
> For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b
> (>=64b).
> Ideally, we should make error
Ok, thanks :)
Palmer Dabbelt 於 2023年4月13日 週四，23:12寫道：
> The RVV test harness currently sets the ISA according to the target
> tuple, but doesn't also set the ABI. This just sets the ABI to match
> the ISA, though we should really also be respecting the user's specific
> ISA to test.
>
> gcc/test
Thanks for catch this, I didn't enable multilib for linux toolchain
for a while,
I guess we should implement TARGET_COMPUTE_MULTILIB for linux targets
to simplify the damm multilib files, but I agree it's too late in the
release cycle, so let's fix that in this way for now.
So LGTM and OK for trun
OK, thanks for the patch :)
On Fri, Apr 14, 2023 at 11:27 AM Li, Pan2 via Gcc-patches
wrote:
>
> Thanks juzhe, update new version [PATCH v3] for even more checks.
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Friday, April 14, 2023 10:46 AM
> To: Li, Pan2 ; gcc-patches
> Cc: Kito.cheng ; Wang,
Wait, take second round review:
> * All extensions were being prefixed with an underscore, which leads to
> some odd combinations like "rv32gc_v", this just adds underscores to
> the multi-letter extensions.
> * The input base ISAs were being canonicalized, which resulted in some
> odd multi
ent: Friday, April 14, 2023 2:47 PM
> To: Kito Cheng
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
> ; Wang, Yanzhang
> Subject: RE: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut.
>
> You're very welcome!
>
> Looks vmorn(v,v) doesn't per
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-2.c: Adjust include way
for riscv_vector.h
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: Add missing
-mabi.
---
gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-2.c | 2 +-
gcc/testsuite/gcc.tar
Document which version of RISC-V vector intrinsics has implemented in
GCC.
gcc/ChangeLog:
* doc/extend.texi (Target Builtins): Add RISC-V Vector
Intrinsics.
(RISC-V Vector Intrinsics): Document GCC implemented which
version of RISC-V vector intrinsics and its refer
Thanks, applied to trunk :)
On Tue, Apr 18, 2023 at 5:27 PM Jin Ma wrote:
>
> The current order of gcc and binutils parsing extensions is inconsistent.
>
> According to latest risc-v spec, the canonical order in which extension names
> must
> appear in the name string specified in Table 29.1 is
I would prefer drop this patch from this patch series since I believe
https://patchwork.ozlabs.org/project/gcc/patch/20230414014518.15458-1-juzhe.zh...@rivai.ai/
is the right fix for this issue.
On Tue, Apr 18, 2023 at 2:40 AM Michael Collison wrote:
>
> From: Kevin Lee
>
> Kevin Lee
> gcc/Chan
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