> @@ -464,6 +464,60 @@
> [(set_attr "type" "arith")
> (set_attr "mode" "DI")])
>
> +(define_expand "add<mode>3"
> + [(set (match_operand:GPR 0 "register_operand" "=r,r")
> + (plus:GPR (match_operand:GPR 1 "register_operand" " r,r")
> + (match_operand:GPR 2 "addi_operand" " r,I")))]
Is it possible to just define a predicate that accepts
register_operand and CONST_INT_P,
and then handle all cases in add<mode>3 pattern?
My point is put all check in one place:
e.g.
check TARGET_ZBA && const_arith_shifted123_operand (operands[2],
<MODE>mode) in add<mode>3
rather than check TARGET_ZBA in addi_operand and use sh[123]add in
add<mode>3 without check.
and that also means we need to sync addi_opearnad and add<mode>3
once we have extension XX could improve addi codegen.
> + ""
> +{
> + if (arith_operand (operands[2], <MODE>mode))
> + emit_insn (gen_riscv_add<mode>3 (operands[0], operands[1], operands[2]));
> + else if (const_arith_2simm12_operand (operands[2], <MODE>mode))
const_arith_2simm12_operand only used once, could you inline the condition here?
> + {
> + /* Split into two immediates that add up to the desired value:
> + * e.g., break up "a + 2445" into:
> + * addi a0,a0,2047
> + * addi a0,a0,398
> + */
> +
> + HOST_WIDE_INT val = INTVAL (operands[2]);
> + HOST_WIDE_INT saturated = HOST_WIDE_INT_M1U << (IMM_BITS - 1);
> +
> + if (val >= 0)
> + saturated = ~saturated;
> +
> + val -= saturated;
> +
> + rtx tmp = gen_reg_rtx (<MODE>mode);
> + emit_insn (gen_riscv_add<mode>3 (tmp, operands[1], GEN_INT
> (saturated)));
> + emit_insn (gen_riscv_add<mode>3 (operands[0], tmp, GEN_INT (val)));
> + }
> + else if (<MODE>mode == word_mode
> + && const_arith_shifted123_operand (operands[2], <MODE>mode))
Same for const_arith_shifted123_operand.
> + {
> + /* Use a sh[123]add and an immediate shifted down by 1, 2, or 3. */
> +
> + HOST_WIDE_INT val = INTVAL (operands[2]);
> + int shamt = ctz_hwi (val);
> +
> + if (shamt > 3)
> + shamt = 3;
> +
> + rtx tmp = gen_reg_rtx (<MODE>mode);
> + emit_insn (gen_rtx_SET (tmp, GEN_INT (val >> shamt)));
> +
> + /* We don't use gen_riscv_shNadd here, as it will only exist for
> + <X:mode>. Instead we build up its canonical form directly. */
> + rtx shifted_imm = gen_rtx_ASHIFT (<MODE>mode, tmp, GEN_INT (shamt));
> + rtx shNadd = gen_rtx_PLUS (<MODE>mode, shifted_imm, operands[1]);
> + emit_insn (gen_rtx_SET (operands[0], shNadd));
> + }
> + else
> + FAIL;
Seems add<mode>3 FAIL will cause problems, we need either add something like:
operands[2] = force_reg (<MODE>mode, operands[2]);
emit_insn (gen_rtx_SET (operands[0],
gen_rtx_PLUS (<MODE>mode,
operands[1], operands[2])));
Or just gcc_unreachable () if we keep using addi_operand to guard this pattern.
