Re: [PATCH] PR target/98878 - Incorrect multilib list for riscv*-rtems

Thanks Jim, committed with your revision of comment :) On Fri, Feb 5, 2021 at 11:28 AM Jim Wilson wrote: > > On Thu, Feb 4, 2021 at 2:02 AM Kito Cheng wrote: >> >> * gcc.c (print_multilib_info): Check all required argument is >> provided >> by de

Re: [PATCH 0/2] RISC-V big endian support

d $ ../configure --prefix=`pwd`/install --with-arch=rv64gc --with-multilib-generator="rv64gc-lp64--" $ make report SIM=spike -j`nproc` On Sat, Jan 30, 2021 at 3:54 AM Marcus Comstedt wrote: > > > Hi Kito, > > Kito Cheng writes: > > > You can add a check in config

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Marcus: Thanks for the quick update, I am testing your V2 patch now, the result seems really great now, some of fail case seems like not cause by big-endian patch, I am reviewing and comparing the fail case with the little-endian build. > Should I make a PR against riscv-newlib on GitHub, or w

Re: [PATCH v2 0/5] RISC-V big endian support

Seems like only 3 fail are related to big-endian, you don't need to worry about other fails. FAIL: gcc.c-torture/execute/string-opt-5.c FAIL: gcc.target/riscv/shift-and-1.c scan-assembler-not andi FAIL: gcc.target/riscv/shift-and-2.c scan-assembler-not andi On Tue, Feb 23, 2021 at 10:38 AM

Re: add rv64im{,c,fc} multilibs

Hi Alexandre: We've added a new configure option to allow you to override that without changing source code. For example: --with-multilib-generator="rv32i-ilp32--c;rv32im-ilp32--c;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f-rv32imafdc-;rv64im-lp64--;rv64imc-lp64--;rv64imfc-lp64f--;rv64imac-

Re: [PATCH] config.sub, config.guess : Import upstream 2021-01-25.

Committed, thanks! On Tue, Feb 23, 2021 at 4:18 PM Richard Biener wrote: > > On Tue, 23 Feb 2021, Kito Cheng wrote: > > > Hi > > > > Does it update config.sub and config.guess, I know it's already > > stage 4, but the config.* stuff update should be harmless

Re: [PATCH v2 0/5] RISC-V big endian support

compile { target { riscv64*-*-* } } } */ -/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O -mlittle-endian" } */ /* Test for si3_mask_1. */ extern int k; On Tue, Feb 23, 2021 at 3:23 PM Marcus Comstedt wrote: > > > Hi Kito, > > Kito

Re: [PATCH v3 6/6] RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md

Hi Jim: Could you take a look for this patch, I am not sure it's the right change or not for big-endian, On Thu, Feb 25, 2021 at 6:39 AM Marcus Comstedt wrote: > > These all intend the least significant subpart of the register. > Use the same endian-neutral "subreg_lowpart_operator" predicate th

Re: [PATCH] RISC-V: Implment __builtin_thread_pointer

Hi Matthias: Sure, backported to gcc 10 branch, let's wait 10.3 :) On Mon, Mar 1, 2021 at 4:17 PM Matthias Klose wrote: > > On 7/8/20 9:59 PM, Jim Wilson wrote: > > On Tue, Jul 7, 2020 at 2:52 AM Kito Cheng wrote: > >> gcc/ChangeLog: > >>

Re: [PATCH] RISC-V: Allow unaligned accesses in cpymemsi expansion

Hi Christoph: Generally LGTM, only 1 minor comment. > @@ -3292,8 +3294,17 @@ riscv_expand_block_move (rtx dest, rtx src, rtx length) >unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); >unsigned HOST_WIDE_INT factor, align; > > - align = MIN (MIN (MEM_ALIGN (src), MEM_ALIG

Re: [PATCH] RISC-V: Enable overlap-by-pieces in case of fast unaliged access

HI Christoph: Could you submit v3 patch which is v1 with overlap_op_by_pieces field, testcase from v2 and add a few more comments to describe the field? And add an -mtune=ultra-size to make it able to test without change other behavior? Hi Palmer: Are you OK with that? On Sat, Aug 14, 2021 at

Re: [PATCH] RISC-V: Enable overlap-by-pieces in case of fast unaliged access

> > Could you submit v3 patch which is v1 with overlap_op_by_pieces field, > > testcase from v2 and add a few more comments to describe the field? > > > > And add an -mtune=ultra-size to make it able to test without change > > other behavior? > > > > Hi Palmer: > > > > Are you OK with that? > > I'm

Re: RISC-V: fix a typo in riscv.h

Hi Yeting: Could you provide a test case for that? On Mon, Sep 14, 2020 at 3:15 PM Yeting Kuo via Gcc-patches wrote: > > Hi all, > > The patch fixes a typo that would make some errors in fast-unaligned-access > targets. > > RISC-V: fix a typo in riscv.h > > 2020-09-14 Yeting Kuo > >

Re: [PATCH] RISC-V: Define __riscv_cmodel_medany for PIC mode.

Thanks, committed with more comments in code :) On Tue, Sep 29, 2020 at 3:35 AM Jim Wilson wrote: > > On Thu, Sep 24, 2020 at 10:46 PM Kito Cheng wrote: > > > > - According the conclusion in RISC-V C API document, we decide to deprecat > >the

Re: [PATCH] RISC-V: Derive ABI from -march if -mabi is not present.

Hi Andreas: Thanks for your review, writing the document is my weakness ...:P On Tue, Oct 6, 2020 at 3:34 PM Andreas Schwab wrote: > > On Okt 06 2020, Kito Cheng wrote: > > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > > index f623467b7637..c6ba738aa0b7 100

Re: [PATCH] RISC-V: Derive ABI from -march if -mabi is not present.

Hi Maciej: Thanks for sharing your experience on MIPS, that sounds like just opposite derived directions to this scheme. > The MIPS port used to have `-mcpu=' as well, which used to be roughly > equivalent to modern `-mtune='; from your description I gather `-mcpu=' is > going to be roughly equi

Re: [PATCH] RISC-V missing __builtin_lceil and __builtin_lfloor

LGTM, thanks, I guess I just missed this before Palmer Dabbelt 於 2022年9月17日 週六 23:07 寫道： > On Mon, 15 Aug 2022 17:44:35 PDT (-0700), kev...@rivosinc.com wrote: > > Hello, > > Currently, __builtin_lceil and __builtin_lfloor doesn't generate an > > existing instruction fcvt, but rather calls ceil

Re: [PATCH] RISC-V modified add3 for large stack frame optimization [PR105733]

Could you provide some data including code size and performance? add is frequently used patten, so we should more careful when changing that. Kevin Lee 於 2022年9月19日 週一，18:07寫道： > Hello GCC, > Started from Jim Wilson's patch in > > https://github.com/riscv-admin/riscv-code-speed-optimization/blob

Re: [PATCH] RISC-V: Support poly move manipulation and selftests.

Committed. thanks! On Thu, Sep 15, 2022 at 4:29 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Change "static void" to "void". > * config.gcc: Add riscv-selftests.o > * config/riscv/predicates.md: Allow const_poly_int. >

Re: [PATCH] RISC-V: Suppress riscv-selftests.cc warning.

Committed, but squashed changes to "RISC-V: Support poly move manipulation and selftests." instead of a standalone commit. On Sat, Sep 17, 2022 at 9:00 AM wrote: > > From: Ju-Zhe Zhong > > This patch is a fix patch for: > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601643.html > > S

Re: [PATCH] RISC-V: Add RVV machine modes.

Committed, thanks! On Thu, Sep 15, 2022 at 7:40 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes. > (ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks. > (ADJUST_ALIGNMENT): Adjust alignment.

Re: [PATCH] RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand

Committed with ChangeLog and minor naming tweaking. > But I'm not sure if the current checking of local symbol can be simplified > a bit. Isn't the first line enough for GET_CODE == const case too ? SYMBOL_REF_P not work for CONST, SYMBOL_REF_P is just checking GET_CODE is SYMBOL_REF, and SYMBOL

Re: [PATCH] RISC-V: Add ABI-defined RVV types.

Committed with few minor style tweaks :) On Tue, Sep 27, 2022 at 5:27 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv-vector-builtins.o. > * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV > builtin function. > * config/riscv

Re: [V2 PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc.

Committed, but I decided to take v1 and disable that by default to prevent breaking the existing code :) On Tue, Sep 13, 2022 at 5:37 PM jiawei wrote: > > From: Jiawei > > Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option, > it will add csr-check in .option section and pass

Re: [PATCH v3] RISC-V: remove deprecate pic code model macro

Committed, and added ChangeLog, remember to add that next time :) On Sat, Sep 24, 2022 at 2:08 AM Vineet Gupta wrote: > > On 9/2/22 14:05, Vineet Gupta wrote: > > Came across this deprecated symbol when looking around for > > -mexplicit-relocs handling in code > > > > Signed-off-by: Vineet Gupta

Re: [PATCH] RISC-V: Introduce RVV header to enable builtin types

Committed, thanks :) On Fri, Sep 30, 2022 at 2:59 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv_vector.h. > * config/riscv/riscv-builtins.cc: Add RVV builtin types support. > * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): New functio

Re: [PATCH] RISC-V: Default to tuning for the thead-c906

-1 for this, default enable fast unaligned access could cause many problems, and lots of RISC-V cores don't support HW unaligned access (Rocket-base RISC-V core, most SiFive core, and most Andes core IIRC), change this to default means package from RISC-V linux distro might contain unaligned access

Re: [PATCH] RISC-V: Add missing vsetvl instruction type.

Committed, thanks :) On Mon, Oct 10, 2022 at 9:44 PM wrote: > > From: Ju-Zhe Zhong > > When implementing built-in framework, I notice I missed > vsetvl instruction type, so add it in a single patch > preparing for the following patches. > > gcc/ChangeLog: > > * config/riscv/riscv.md: Add

Re: [PATCH] RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name".

Committed, thanks :) On Mon, Oct 10, 2022 at 9:58 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): > Move from config/riscv/riscv-vector-builtins.h. > (DEF_RVV_TYPE): Change USER_NAME to NAME. > (r

Re: [PATCH] RISC-V: Refine riscv-vector-builtins.o include files and makefile.

I would suggest we do not include those header files unless we really need that. On Tue, Oct 11, 2022 at 2:32 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc: Change include files same as > ARM SVE. > * config/riscv/t-riscv: Refine

Re: [PATCH 4/5 V1] RISC-V:Implement testcases for Crypto extension

Just one general review comment for this patch: - Add newline at end of this file to prevent "\ No newline at end of file" in the git commit log - I saw you've skip -g and -flto, I guess that because that cause fail since -g or -flto might add few more line to make the scan-assembler-times, I would

Re: [PATCH 4/5 V1] RISC-V:Implement testcases for Crypto extension

> > diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c > > b/gcc/testsuite/gcc.target/riscv/zbkb64.c > > new file mode 100644 > > index 000..2cd76a29750 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c > > @@ -0,0 +1,21 @@ > > +/* { dg-do compile } */ > > +/* { dg-opti

Re: [PATCH] RISC-V:Add support for ZMMUL extension

LGTM for GCC 13, I'll commit that once stage 1 is open again. On Mon, Feb 14, 2022 at 10:26 AM wrote: > > From: LiaoShihua > > ZMMUL extension is Multiply only extension for RISC-V.It implements the > multiplication subset of the M extension. > The encodings are identical to those o

Re: [RFC v2] RISCV: Combine Pass Clobber Ops

Hi Patrick: There is few direction in my mind: 1. Model the C extension right in riscv.md 2. Write peephole2 pattern. 3. Implement a RISC-V specific register renaming pass. 1. Model the C extension right in riscv.md Currently we rely the GNU as to compress the instruction to C extension, and ac

Re: [PATCH] riscv: Allow -Wno-psabi to turn off ABI warnings [PR91229]

Hi Jakub: LGTM, Thanks! On Tue, Mar 15, 2022 at 6:57 PM Jakub Jelinek via Gcc-patches wrote: > > Hi! > > While checking if all targets honor -Wno-psabi for ABI related warnings > or messages, I found that almost all do, except for riscv. > In the testsuite when we want to ignore ABI related mess

Re: [PATCH] RISC-V: Handle combine extension in canonical ordering.

Hi Shi-Hua: Thanks, generally it's LGTM, just a few coding style issues. I've fixed that and committed this time, but just let you know where you should update your coding style. And you could use git clang-format and use /contrib/clang-format as format file to save your time to indent that. ht

Re: [PATCH] RISC-V: Implement ZTSO extension.

Hi Shi-Hua: Thanks, this patch is LGTM, but I would defer that until stage 1, because the binutils part isn't merget yet. On Tue, Mar 15, 2022 at 5:10 PM wrote: > > From: LiaoShihua > > ZTSO is the extension of tatol store order model. > This extension adds no new instructions to th

Re: [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases

I would suggest rename those __builtin_riscv_* to __builtin_riscv_cmo_*, that's less confusing, __builtin_riscv_zero just seems like it will return a zero value. On Fri, Mar 4, 2022 at 10:52 AM wrote: > > From: yulong-plct > > This commit adds testcases about CMO instructions. > 7 > 8 gcc/t

Re: [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases

> You meant cbo_zero, right? > CMO was only the task-group name, but the extensions ended up having "cbo" > in their name… Yeah, named with an extension name makes more sense, thank you for pointing that out. Either __builtin_riscv_cbo_zero or __builtin_riscv_zicboz_cbo_zero is fine to me since I

Re: [PATCH] RISC-V: Implement ZTSO extension.

Hi Palmer: Cool, so I keep that on the GCC 13 queue :) On Tue, Mar 22, 2022 at 10:41 AM Palmer Dabbelt wrote: > > On Mon, 21 Mar 2022 19:39:24 PDT (-0700), kito.ch...@sifive.com wrote: > > Hi Palmer: > > > > I guess the problem is binutils isn't included and it's too close to the > > GCC release

Re: 回复：[PATCH] Asan changes for RISC-V.

Arm 32, x86 (32) and mips has support for Asan[1], so we can `reference` how they implement that, but I guess the problem is we need someone to do that. [1] https://github.com/llvm/llvm-project/blob/main/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake#L28 On Thu, Apr 21, 2022 at 7:54 AM Pal

Re: [PATCH] Asan changes for RISC-V.

Hi Joshua: > Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is > still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in > to reconfigure, there are compiling errors. Is it because # libsanitizer not supported rv32, but it will break the rv64 multi-

Re: [PATCH] riscv: fix -Wformat-diag errors.

Thanks Martin! On Wed, Jan 19, 2022 at 12:23 AM Martin Liška wrote: > > Pushed as pre-approved by Jeff. The patch fixes -Wformat-diag warnings. > > Martin > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_subset_list::add): > Wrap keywords with quotes and remove

Re: [PATCH] RISC-V: Fix use-after-free error in `parse_multiletter_ext'

LGTM, thanks :) On Wed, Jan 19, 2022 at 12:59 AM Maciej W. Rozycki wrote: > > Avoid undefined arithmetic involving a pointer to a heap allocation that > has been freed and move a problematic calculation ahead of the following > call to `free' in `riscv_subset_list::parse_multiletter_ext', removin

Re: [PATCH] RISC-V: Document the degree of position independence that medany affords

LGTM, thanks for adding those comments :) On Wed, Jan 19, 2022 at 1:21 AM Palmer Dabbelt wrote: > > The code generated by -mcmodel=medany is defined to be > position-independent, but is not guaranteed to function correctly when > linked into position-independent executables or libraries. See the

Re: [PATCH] RISC-V: Update testcases info with new implement info

Committed, thanks! On Wed, Jan 19, 2022 at 5:18 PM Martin Liška wrote: > > On 1/19/22 10:15, shi...@iscas.ac.cn wrote: > > |From: LiaoShihua After commit > > 591b6e00d1bfe12932ca31530d5859f95db8a35a " riscv: fix -Wformat-diag errors > > ", some strings in implement was changed. This patch upda

Re: [PATCH v2] doc: RISC-V: Document the `-misa-spec=' option

Thanks, LGTM :) On Sat, Feb 5, 2022 at 7:56 AM Maciej W. Rozycki wrote: > > We have recently updated the default for the `-misa-spec=' option, yet > we still have not documented it nor its `--with-isa-spec=' counterpart > in the GCC manuals. Fix that. > > gcc/ > * doc/install.tex

Re: [PATCH] RISC-V: Always pass -misa-spec to assembler [PR104219]

Committed to trunk :) On Fri, Feb 4, 2022 at 8:56 PM Martin Liška wrote: > > May I please PING this? > > Thanks, > Martin > > On 1/25/22 14:04, Kito Cheng wrote: > > Add -misa-spec to OPTION_DEFAULT_SPECS to make sure -misa-spec will > > always pass that int

Re: [PATCH] RISC-V: Add target machine headers as a dependency for riscv-sr.o

OK to trunk, thanks for fixing this issue, I hit that issue before but I didn't figure out what happened...since that issue will disappear when I clean build :p On Tue, Feb 1, 2022 at 5:52 AM Maciej W. Rozycki wrote: > > Make riscv-sr.o depend on target machine headers, removing spurious test > f

Re: [PATCH] RISC-V/testsuite: Run target testing over all the usual optimization levels

Hi Maciej: Thanks for doing this, OK to trunk. On Tue, Feb 1, 2022 at 7:04 AM Maciej W. Rozycki wrote: > > Use `gcc-dg-runtest' test driver rather than `dg-runtest' to run the > RISC-V testsuite as several targets already do. Adjust test options > across individual test cases accordingly where

Re: [PATCH] doc: invoke: RISC-V: Clean up the -mstrict-align wording

LGTM, thanks :) On Tue, Feb 8, 2022 at 12:30 PM Palmer Dabbelt wrote: > > The polarity of do/do not was reversed for this option when compored to > the rest of them. This seems to have been copied from PowerPC, when the > polarity of the arguments in the docs was reversed (presumably to match >

Re: [PATCH] doc: invoke: RISC-V: Clean up the -memit-attribute wording

Hi Palmer: Seems like...you update the wrong part? you are updating -mmcount-ra-address/-mno-mcount-ra-address rather than -memit-attribute/ -mno-emit-attribute ? On Tue, Feb 8, 2022 at 12:30 PM Palmer Dabbelt wrote: > > The previous wording makes it sound like "do not emit" is a > clarification

Re: [PATCH] RISC-V: Add target machine headers as a dependency for riscv-sr.o

Hi Maciej: OK for release branches, thanks! On Tue, Feb 8, 2022 at 8:24 PM Maciej W. Rozycki wrote: > > On Mon, 7 Feb 2022, Kito Cheng wrote: > > > OK to trunk, thanks for fixing this issue, I hit that issue before but > > I didn't figure out what happened...since

Re: [PATCH 5/5 V1] RISC-V:Implement architecture extension test macros for Crypto extension

I would suggest implementing that in riscv_subset_list::parse so that it also affect the ELF attribute emission. On Wed, Feb 23, 2022 at 5:44 PM wrote: > > From: LiaoShihua > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):Add __riscv_zks, > __riscv_zk, __riscv_z

Re: [PATCH 3/5 V1] RISC-V:Implement intrinsics for Crypto extension

Those header files have license issues that should relicinced to GPL, and don't put rvk_asm_intrin.h rvk_emu_intrin.h, since they are not too meaningful when we have compiler support. General comment: - Use /* */ rather than //, that gives much more compatibility, that is illegal for c89. - Add a

Re: [PATCH 5/5 V1] RISC-V:Implement architecture extension test macros for Crypto extension

and could you separate this from this patch series, I would like to include this into GCC 12, and defer other stuffs to GCC 13 On Thu, Feb 24, 2022 at 5:55 PM Kito Cheng wrote: > > I would suggest implementing that in riscv_subset_list::parse so that > it also affect the ELF attribute

Re: [PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension

On Wed, Feb 23, 2022 at 5:46 PM wrote: > > From: LiaoShihua > > > gcc/ChangeLog: > > * config/riscv/predicates.md (bs_operand): operand for bs > (rnum_operand): > * config/riscv/riscv.md: include crypto.md > * config/riscv/crypto.md: New file. > > Co-Authored-By: W

Re: [PATCH v1 2/2] RISC-V: Add instruction fusion (for ventana-vt1)

Hi Philipp: Thanks for the patch, I like this approach, that can easily configure different capabilities for each core :) So there are only a few minor comments for this patch. On Mon, Nov 15, 2021 at 5:49 AM Philipp Tomsich wrote: > > From: Philipp Tomsich > > The Ventana VT1 core supports qu

Re: [PATCH v1 0/2] Basic support for the Ventana VT1 w/ instruction fusion

Hi Philipp: This patch set LGTM, feel free to commit once addressed those issues. On Mon, Nov 15, 2021 at 5:48 AM Philipp Tomsich wrote: > > > This series provides support for the Ventana VT1 (a 4-way superscalar > rv64gc_zba_zbb_zbc_zbs core) including support for the supported > instruction fu

Re: [PATCH v1 1/8] bswap: synthesize HImode bswap from SImode or DImode

Hi Philipp: I would suggest add define_expand pattern for bswaphi2 rather than changing expand_unop with following reasons: - There is a comment above this change, and it also tried widen_bswap after this if-block, so I think this patch is kind of violating this comment. /* HImode is speci

Re: [PATCH v1 2/8] RISC-V: costs: handle BSWAP

> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c > index c77b0322869..8480cf09294 100644 > --- a/gcc/config/riscv/riscv.c > +++ b/gcc/config/riscv/riscv.c > @@ -2131,6 +2131,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int > outer_code, int opno ATTRIBUTE_UN >*total =

Re: [PATCH v1 6/8] RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1"

> --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -367,3 +367,16 @@ (define_insn "*bexti" >"TARGET_ZBS" >"bexti\t%0,%1,%2" >[(set_attr "type" "bitmanip")]) > + > +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = > -1 }) > +;; usin

Re: [PATCH v2 0/2] RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc6

I would prefer to accept those patchset even with no builtin function or intrinsic function yet, this not only add the support of -march option, but also introduce the predefined macros like __riscv_zk*, which could be used in *.S file to check if those instructions are available or not. On Wed,

Re: [PATCH v2 0/2] RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc6

Hi SiYu: Committed, thanks! On Thu, Nov 25, 2021 at 12:42 AM Palmer Dabbelt wrote: > > On Wed, 24 Nov 2021 02:00:33 PST (-0800), Kito Cheng wrote: > > I would prefer to accept those patchset even with no builtin function > > or intrinsic function yet, > > this not only a

Re: [PATCH] RISC-V: jal cannot refer to a default visibility symbol for shared object.

Committed, thanks :) On Mon, Nov 29, 2021 at 8:48 PM Nelson Chu wrote: > > This is the original binutils bugzilla report, > https://sourceware.org/bugzilla/show_bug.cgi?id=28509 > > And this is the first version of the proposed binutils patch, > https://sourceware.org/pipermail/binutils/2021-Nove

Re: [PATCH][GCC11] PR tree-optimization/103603 - Directly resolve range_of_stmt dependencies. (Port of PR 103231/103464)

Test result from RISC-V, tested on riscv64-unknown-elf and riscv64-unknown-linux-gnu with no regressions. Thanks :) On Wed, Dec 8, 2021 at 4:19 AM Andrew MacLeod via Gcc-patches wrote: > > The following patch is a slight rework of the 2 patches which flatten > rangers call stack. It needed some

Re: [PATCH] RISC-V: Add new line at end of file.

Most changes has included in this commit: https://github.com/gcc-mirror/gcc/commit/684d238b8cd7e8222d9e66457815f2a63178730b On Wed, Oct 12, 2022 at 9:43 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc: Add new line. > * config/riscv/riscv_vector.

Re: [PATCH] RISC-V: Move function place to make it looks better.

Moving class declaration to theriscv-vector-builtins.cc file is not bad idea since the only user is riscv-vector-builtins.cc, but I don't think moving other code for consistent with ARM's code is reasonable, anyway committed with only class declaration movement, NOTE: I've off-list conversion with

Re: [PATCH] RISC-V: Clang-format vector_type_index.

Committed but combined with another one clang-format fixing :) On Tue, Oct 11, 2022 at 2:36 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.h (DEF_RVV_TYPE): Clang-format > it. > > --- > gcc/config/riscv/riscv-vector-builtins.h | 3 +-- > 1

Re: [PATCH] RISC-V: Clang-format add_vector_attribute function.

Committed, thanks! On Tue, Oct 11, 2022 at 2:22 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc (add_vector_type_attribute): > Clang-format function. > > --- > gcc/config/riscv/riscv-vector-builtins.cc | 4 ++-- > 1 file changed, 2 insert

Re: [PATCH] RISC-V: Remove TUPLE size macro define.

Committed, thanks! On Tue, Oct 11, 2022 at 2:23 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.h: Remove redundant macro. > > --- > gcc/config/riscv/riscv-vector-builtins.h | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/gcc/confi

Re: [PATCH] RISC-V: Refine register_builtin_types function.

Committed with a few minor ChangeLog fixes. On Tue, Oct 11, 2022 at 2:15 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc (GTY): Redefine vector types. > (build_const_pointer): New function. > (register_builtin_type): Ditto.

Re: [PATCH] RISC-V: Fix format[NFC]

Committed :) On Mon, Oct 17, 2022 at 3:31 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/t-riscv: Change Tab into 2 space. > > --- > gcc/config/riscv/t-riscv | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/t-riscv b/gcc/c

Re: [PATCH] RISC-V: Reorganize mangle_builtin_type.[NFC]

Committed :) On Sat, Oct 15, 2022 at 7:03 AM wrote: > > From: Ju-Zhe Zhong > > Hi, this patch fixed my mistake in the previous commit patch. > Since "mangle_builtin_type" is a global function will be called in riscv.cc. > It's reasonable move it down and put them together stay with other global

Re: [PATCH] RISC-V: Add RVV intrinsic basic framework.

Verified, committed to trunk. On Mon, Oct 17, 2022 at 4:21 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add gt files since function_instance is GTY ((user)). > * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV > intrinsic framework. >

Re: [PATCH] RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.

Verified, committed to trunk. On Mon, Oct 17, 2022 at 4:37 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv-vector-builtins-bases.o and > riscv-vector-builtins-shapes.o > * config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro. >

Re: [PATCH] RISC-V: Add type attribute for atomic instructions.

Committed, thanks :) On Fri, Oct 21, 2022 at 1:02 PM Monk Chiang wrote: > > gcc/ChangeLog: > > * config/riscv/riscv.md: Add atomic type attribute. > * config/riscv/sync.md: Add atomic type for atomic instructions. > --- > gcc/config/riscv/riscv.md | 2 +- > gcc/config/riscv/sync

Re: [PATCH] RISC-V: Fix REG_CLASS_CONTENTS.

Committed, thanks for the fix! On Mon, Oct 24, 2022 at 9:39 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv.h (enum reg_class): Fix ALL_REGS. > > --- > gcc/config/riscv/riscv.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/conf

Re: [PATCH] RISC-V: Remove unused TI/TF vector modes.

Committed, thanks :) On Mon, Oct 24, 2022 at 10:06 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF > vector modes. > > --- > gcc/config/riscv/riscv-vector-switch.def | 4 > 1 file changed, 4 deletions(-) >

Re: [PATCH] RISC-V: Replace CONSTEXPR with constexpr

Committed, thanks! On Mon, Oct 24, 2022 at 10:21 AM wrote: > > From: Ju-Zhe Zhong > > Move away from the pre-C++11 compatibility macro CONSTEXPR. > This patch is inspired by aarch64: > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603974.html. > > gcc/ChangeLog: > > * config/ris

Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))

Merged two changes into one patch, and committed to master :) On Mon, Oct 24, 2022 at 10:28 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_legitimize_move): Adjust using > force_reg. > > --- > gcc/config/riscv/riscv.cc | 4 +--- > 1 file changed,

Re: [PATCH] RISC-V: Support --target-help for -mcpu/-mtune

committed. On Fri, Sep 30, 2022 at 10:06 AM Kito Cheng wrote: > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_tunes): New. > (riscv_get_valid_option_values): New. > (TARGET_GET_VALID_OPTION_VALUES): New. > * config/

Re: [PATCH] riscv: fix cross compiler

Ok, thanks for the fix! Martin Liška 於 2022年10月25日 週二 13:02 寫道： > On 10/25/22 07:01, Martin Liška wrote: > > |More riscv_get_valid_option_values out of| > > * Move >

Re: [PATCH] RISC-V: Recognized Svinval and Svnapot extensions

On Tue, Oct 25, 2022 at 9:37 PM Bernhard Reutner-Fischer via Gcc-patches wrote: > > On 25 October 2022 08:17:33 CEST, Monk Chiang wrote: > >gcc/ChangeLog: > > > > >diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > >index 55e0bc0a0e9..63ac56a8ca0 100644 > >--- a/gcc/conf

Re: [PATCH] RISC-V: Add h extension support

Thanks for the review, committed :) On Mon, Oct 24, 2022 at 11:05 PM Jeff Law via Gcc-patches wrote: > > > On 10/24/22 03:55, Kito Cheng wrote: > > `h` was the prefix of multi-letter extension name, but it become a > > extension in later RISC-V isa spec. > > > &

Re: [PATCH] RISC-V: Recognized Svinval and Svnapot extensions

verified and committed On Tue, Oct 25, 2022 at 2:18 PM Monk Chiang wrote: > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_ext_version_table): > Add svinval and svnapot extension. > (riscv_ext_flag_table): Ditto. > * config/riscv/riscv-opts.h (MA

Re: [PATCH] RISC-V: Fix typo.

Committed with title tweak , thanks On Mon, Oct 24, 2022 at 10:24 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo. > > --- > gcc/config/riscv/riscv-modes.def | 46 > 1 file changed, 23 in

Re: [PATCH] RISC-V: Support load/store in mov pattern for RVV modes.

Verified and committed to trunk, thanks! And don't forgot changelog next time :P On Mon, Oct 24, 2022 at 10:09 AM wrote: > > From: Ju-Zhe Zhong > > --- > gcc/config.gcc| 2 +- > gcc/config/riscv/constraints.md | 22 + > gcc/config/riscv/predicate

Re: [PATCH] RISC-V: Fix a mistake in previous patch.

Committed with title tweak, thanks On Tue, Oct 25, 2022 at 9:53 PM wrote: > > From: Ju-Zhe Zhong > > I noticed that I have made a mistake in previous patch: > > https://patchwork.sourceware.org/project/gcc/patch/20220817071950.271762-1-juzhe.zh...@rivai.ai/ > > The previous statement before

Re: [v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension.

Hmmm 2 issue, but I fixed that anyway, otherwise LGTM. > From: Jiawei > > Limit z*inx abi support with 'ilp32','ilp32e','lp64' only. > Use GPR instead FPR when 'zfinx' enable, Only use even registers > in RV32 when 'zdinx' enable. > Enable FLOAT16 when Zhinx/Zhinxmin enabled. > > Co-Authored-By:

Re: [v4 PATCH 0/4] RISC-V: Support z*inx extensions.

works can be find in follow links, binutils and simulator > works already supported on upstream. > https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase > > Thanks for Tariq Kurd, Kito Cheng, Jim Willson, > Jeremy Bennett helped us a lot with this work. > > [1] https://githu

Re: [PATCH v3] RISC-V: Libitm add RISC-V support.

I guess we don't really care about RV32E here, but in case you add a guard for that? #ifdef __riscv_e #error "rv32e unsupported" #endif On Fri, Oct 28, 2022 at 4:39 PM Xiongchuan Tan via Gcc-patches wrote: > > Reviewed-by: Palmer Dabbelt > Acked-by: Palmer Dabbelt > > libitm/ChangeLog: > >

Re: [PATCH] RISC-V: Change constexpr back to CONSTEXPR

Committed, thanks! On Fri, Oct 28, 2022 at 6:47 AM Jeff Law via Gcc-patches wrote: > > > On 10/27/22 08:41, juzhe.zh...@rivai.ai wrote: > > From: Ju-Zhe Zhong > > > > According to > > https://github.com/gcc-mirror/gcc/commit/f95d3d5de72a1c43e8d529bad3ef59afc3214705. > > Since GCC 4.8.6 doesn't

Re: [RFC] RISC-V: Add profile supports.

Could you add some test cases? --- Parsing logic is kind of too adhoc, I would prefer using something like the following code to prevent magic pointer arithmetic like p+6: something like this: Table of all profile names = {"RVA20U64", riscv_profile::RVA20U64, ...} const char *rva20u64[] = {"m"

Re: [PATCH] soft-fp: Update soft-fp from glibc

ping On Wed, Aug 10, 2022 at 10:23 PM Kito Cheng wrote: > > This patch is updating all soft-fp from glibc, most changes are > copyright years update, removing "Contributed by" lines and update URL for > license, and changes other than those update are adding conversion &

Re: [PATCH] soft-fp: Update soft-fp from glibc

Hi Joseph: I saw other soft-fp updates will also ask for some approval on the list too, anyway I know that now :) Thanks! On Tue, Aug 16, 2022 at 10:18 PM Joseph Myers wrote: > > On Tue, 16 Aug 2022, Kito Cheng wrote: > > > ping > > Under our write access policies, "

Re: [PATCH 0/2] RISC-V: Support _Float16 type and implement zfh and zfhmin extension

This patch set has been committed to trunk. On Wed, Aug 10, 2022 at 11:44 PM Kito Cheng wrote: > > This patch set implements Zfh and Zfhmin, adds soft-float for _Float16, and > enables _Float16 type in C++ mode. > > Zfh and Zfhmin are extensions for IEEE half precision, both

Re: [PING][PATCH] RISC-V: Standardize formatting of SFB ALU conditional move

OK, thanks for tweaking this! On Thu, Aug 18, 2022 at 10:40 PM Maciej W. Rozycki wrote: > > On Tue, 26 Jul 2022, Maciej W. Rozycki wrote: > > > Standardize the formatting of SFB ALU conditional move operations from: > > > > beq a2,zero,1f; mv a0,zero; 1: # movcc > > > > to: > > > > be

Re: [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns

I know using more precise constraints might result in better code gen in some situations, but I am Curious what's the difference between the using pattern condition and constraints/predicates in this case? Is there any performance or code gen difference? On Fri, Aug 19, 2022 at 6:07 AM apinski---

Re: [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md

On Fri, Aug 19, 2022 at 6:08 AM apinski--- via Gcc-patches wrote: > > From: Andrew Pinski > > The constraints should be n instead of i. Also there > needs to a check for out of bounds zero_extract for > *bexti. > > gcc/ChangeLog: > > PR target/106632 > PR target/106588 > *

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