Hello,
> Is it ok now?
Ping?
--
Thanks, K
Hello,
MSVC and ICC (currently Windows version, Linux version soon) have
dedicated intrinsics to read/set EFLAGS register ([1], [2]).
Patch introduces these intrinsics and tests for them.
Bootstrapped. New tests pass.
Although gate is closed patch is obvious.
So, is it ok for trunk?
ChangeLog/
Hello,
On 04 Dec 19:59, Kirill Yukhin wrote:
> So, is it ok for trunk?
Small correction. I think it is better to use
popfql/pushfql instead of popf/pushf (however they're
encoded equally).
--
Thanks, K
Hello Uros,
On 04 Dec 20:16, Uros Bizjak wrote:
> Oh, no. We don't want assembly in this century ;)
Whoops, sorry. I was trying to do it with minimal changes.
I've implemented approach you proposed.
Batch in the bottom.
Bootstrapped. New tests pass.
Is it ok now?
ChangeLog/
* config/i38
On 05 Dec 09:01, Uros Bizjak wrote:
> On Thu, Dec 5, 2013 at 8:46 AM, Kirill Yukhin wrote:
> > + emit_insn (gen_push (gen_rtx_REG (CCmode, FLAGS_REG)));
>
> The FLAGS_REG shuold be generated in an integer mode, appropriate for the
> push!
I suppose, `word_mode' is
Hello,
On 05 Dec 05:30, H.J. Lu wrote:
> Kirill, can you take a look why it doesn't work for x86?
Okay, I'll look at this.
--
Thanks, K
Hello,
On 05 Dec 16:40, Kirill Yukhin wrote:
> On 05 Dec 05:30, H.J. Lu wrote:
> > Kirill, can you take a look why it doesn't work for x86?
> Okay, I'll look at this.
I've looked at this. It seems that `CANNOT_CHANGE_MODE_CLASS'
is too conservativ
Hello,
On 09 Dec 14:08, H.J. Lu wrote:
> There are no regressions on Linux/x86-64 with -m32 and -m64.
> Can you check if it improves code quality on x886?
That is exactly what I was talking about. However I wasn't sure
that we can change already defined (and used throughout ports)
target hook.
An
On 09 Dec 14:08, H.J. Lu wrote:
>
> There are no regressions on Linux/x86-64 with -m32 and -m64.
> Can you check if it improves code quality on x886?
As second thought. If Tejas and Richard are right and it is simply incorrect
to check any offsets in this hook, may be we can end up with patch in
On 10 Dec 08:23, H.J. Lu wrote:
> What is wrong to pass the correct offset to
> CANNOT_CHANGE_MODE_CLASS? Backends are free to
> ignore it.
Yes, but as fas as understand this hook as a predicate
saying if it not-safe to change mode1 to mode2 for given
register class. I don't think that offsets sh
On 10 Dec 09:02, H.J. Lu wrote:
> On Tue, Dec 10, 2013 at 8:05 AM, Kirill Yukhin
> wrote:
> > On 09 Dec 14:08, H.J. Lu wrote:
> > NOINLINE float
> > foo32x2_le (float32x2_t x)
> > {
> > +#ifdef __i386__
> > + __builtin_ia32_emms ();
> > +#end
Hello,
On 02 Dec 16:09, Kirill Yukhin wrote:
> Hello,
> On 19 Nov 12:08, Kirill Yukhin wrote:
> > Hello,
> > On 15 Nov 20:06, Kirill Yukhin wrote:
> > > Ping.
> > Ping.
> Ping.
Ping.
Rebased patch in the bottom.
--
Thanks, K
---
gcc/config/i386/i386.c
Hello,
On 02 Dec 16:10, Kirill Yukhin wrote:
> Hello,
> On 19 Nov 12:11, Kirill Yukhin wrote:
> > Hello,
> > On 15 Nov 20:07, Kirill Yukhin wrote:
> > > > Is it ok for trunk?
> > > Ping.
> > Ping.
> Ping.
Ping.
Rebased patch in the bottom.
-
Hello,
On 02 Dec 16:11, Kirill Yukhin wrote:
> Hello,
> On 19 Nov 12:12, Kirill Yukhin wrote:
> > Hello,
> > On 15 Nov 20:08, Kirill Yukhin wrote:
> > > > Is it ok for trunk?
> > > Ping.
> > Ping.
> Ping.
Ping.
Rebased patch in the bottom.
Hello,
On 02 Dec 16:11, Kirill Yukhin wrote:
> Hello,
> On 19 Nov 12:14, Kirill Yukhin wrote:
> > Hello,
> > On 15 Nov 20:09, Kirill Yukhin wrote:
> > > > Is it ok for trunk?
> > > Ping.
> > Ping.
> Ping.
Ping.
Rebased patch in the bottom.
--
Thanks, K
Hello,
On 02 Dec 16:13, Kirill Yukhin wrote:
> Hello,
> On 19 Nov 12:14, Kirill Yukhin wrote:
> > Hello,
> > On 15 Nov 20:10, Kirill Yukhin wrote:
> > > > Is it ok to commit to main trunk?
> > > Ping.
> > Ping.
> Ping.
Ping.
Updated patch in the bo
> Rebased patch in the bottom.
Adding the patch.
--
Thanks, K
---
gcc/config/i386/sse.md | 18 ++
gcc/config/i386/subst.md | 20
2 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e15e1b1..8
Hello,
On 02 Dec 16:15, Kirill Yukhin wrote:
> Hello
> > Ok for trunk?
> Ping?
Ping.
Rebased patch attached.
Thanks, K
p.patch.bz2
Description: BZip2 compressed data
> Patch attached.
>
> Ok for trunk?
>
Just noticed Uros's input about predicates. So, ok with fix of predicate?
Hello Uros,
On 23 Dec 17:46, Uros Bizjak wrote:
> This "round_expand_predicate" is the predicate substitution I was
> referred to in the review of 5/8. Please use it also in insn patterns,
> perhaps renamed as "round_predicate"
This is drawback of substs. We bind given subst attribute to given sub
Hello,
On 23 Dec 17:26, Uros Bizjak wrote:
> On Mon, Dec 23, 2013 at 5:11 PM, Uros Bizjak wrote:
> > So, OK for mainline, but I would kindly ask you to please wait a
> > couple of days for possible Richard's comments
>
> When substituting constraints, please also substitute corresponding
> opera
Hello,
On 18 Dec 18:16, Uros Bizjak wrote:
> the patch is OK (with above mentioned changes) for mainline.
Thanks,
One more nit. It seems that currently vectorizer expects mask_type to
be equal to operand_type, which doesn't hold for AVX-512F.
So, I'll comment out like this:
@@ -34677,6 +36423,3
Hello,
On 18 Dec 17:08, Uros Bizjak wrote:
> Whoa.
>
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
>
> No, not in this patch.
Okay, moved it to 5/8 patch.
--
Thanks, K
Maxim Kuznetsov
Sergey Lega
Anna Tikhonova
Ilya Tocar
Andrey Turetskiy
Ilya Verbin
Kirill Yukhin
Michael Zolotukhin
* config/i386/i386.c (MAX_CLASSES): Increase number of classes.
(
Hello Uroš,
On 18 Dec 18:16, Uros Bizjak wrote:
> +/* Walk through insns sequence or pattern and erase rounding mentions.
> + Main transformation is performed in ix86_erase_embedded_rounding_1. */
> +static rtx
> +ix86_erase_embedded_rounding (rtx pat)
>
> All calls to this function are made wi
Hello,
On 19 Nov 15:36, Uros Bizjak wrote:
> Please also add new command options to g++.dg/other/sse-2.C and
> g++.dg/other/sse-3.C
Done (to i386-[23].C).
> > --mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd @gol
> > +-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -msha -mno-sha @gol
>
> No n
Adding gcc-patches.
On Mon, Dec 30, 2013 at 5:06 PM, Kirill Yukhin wrote:
> Hello,
> It seems that we forgot about kmovw instruction in AVX512 patch series.
>
> Patch in the bottom, is it ok for trunk?
>
> gcc/
>
> * config/i386/avx512fintrin.h (_mm512_kmov): New.
Hello Eric,
On 02 Jan 00:07, Eric Botcazou wrote:
> The change is actually to ix86_data_alignment, not to ix86_constant_alignment:
>
> @@ -26219,7 +26433,8 @@ ix86_constant_alignment (tree exp, int align)
> int
> ix86_data_alignment (tree type, int align, bool opt)
> {
> - int max_align = opti
Hello,
On 03 Jan 09:59, Jakub Jelinek wrote:
> Does it matter which of vmovdqu32 vs. vmovdqu64 is used if no
> masking/zeroing is performed (i.e. vmovdqu32 (%rax), %zmm0 vs.
> vmovdqu64 (%rax), %zmm0) for performance reasons (i.e. isn't there some
> reinterpretation penalty)?
No, there should be no
Guys,
On 04 Jan 10:09, Jakub Jelinek wrote:
> Note I haven't tested the patch at all, perhaps some testcases wouldn't
> match their regexps anymore (but probably the
> gcc.target/i386/avx512f-vmovdqu32-1.c change could go away).
>
> --- gcc/config/i386/sse.md.jj 2014-01-04 09:48:48.0 +0100
Hello Allan,
On 07 Jan 20:54, Allan Sandfeld Jensen wrote:
> On Sunday 29 December 2013, Allan Sandfeld Jensen wrote:
> > The function dispatcher might currently choose functions declared with
> > target("arch=ivybridge") on a Sandy Bridge CPU. This happens because the
> > function is only detected
Hello,
We've [at least] 2 patterns with wrong conditions.
Bootstrapped.
AVX-512 testsuite more complicated.
Few tests are fail, and it seems that not because of
the patch. I am trying to find guilty commit.
Failing this tests: avx512f-vpmovsxbd-2.c and
other *-extension insns.
gcc/
* co
On 10 Jan 13:07, Kirill Yukhin wrote:
> Few tests are fail, and it seems that not because of
> the patch. I am trying to find guilty commit.
I filed PR59754 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59754)
--
Thanks, K
Hello,
It seems that we miss few more intrinsics.
I've also added some missing substed predicates
Also I've fixed bogus rcp14 pattern and removeed
some redundant subst attributes.
Bootstrapped. New & existing tests pass (expcept
for those mentioned in PR about REE).
Is it ok for trunk?
gcc/
Hello,
On 11 Jan 12:42, Uros Bizjak wrote:
> On Fri, Jan 10, 2014 at 5:24 PM, Jakub Jelinek wrote:
> > This means you should ensure aligned_mem will be set for
> > CODE_FOR_avx512f_movntdqa in ix86_expand_special_args_builtin.
Fixed. Updated patch in the bottom.
> > Leaving the rest of review to
Hello,
On 13 Jan 09:35, Jakub Jelinek wrote:
> On Mon, Jan 13, 2014 at 09:15:14AM +0100, Uros Bizjak wrote:
> > On Mon, Jan 13, 2014 at 9:07 AM, Jakub Jelinek wrote:
> > Kirill, is it possible for you to test the patch in the simulator? Do
> > we have a testcase in gcc's testsuite that can be used
Hello,
This patch introduces missing AVX-512PF intrinsics and tests.
It also renames store/load intrinsics according to EAS.
gcc/
* config/i386/avx512fintrin.h (_mm512_loadu_si512): Rename.
(_mm512_storeu_si512): Ditto.
* config/i386/avx512pfintrin.h (_mm512_mask_prefetch_i
ndle avx521vl and noavx512vl.
* config/i386/sse.md (define_insn "vec_dupv2df"): Split
AVX-512 alternative out of SSE.
(define_insn "*vec_concatv2df"): Ditto.
--
Thanks, K
commit 924990a6e8d38b6ebff9dd9a79e285ef81890202
Author: Kirill Yukhin
Date: Mon Aug 3
mmit 64741d31c19d464a1ca4270b775a7b54c1253019
Author: Kirill Yukhin
Date: Tue Aug 4 10:36:10 2015 +0300
Merge SSE 4.1 and AVX ptest patterns. Extend iterator for new one.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 128c5af..f93a5ce 100644
--- a/gcc/config/i386/i3
On 04 Aug 14:10, Uros Bizjak wrote:
> On Tue, Aug 4, 2015 at 1:47 PM, Kirill Yukhin wrote:
> > Hello,
> > - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
> > - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
On 04 Aug 14:06, Uros Bizjak wrote:
> On Tue, Aug 4, 2015 at 1:58 PM, Kirill Yukhin wrote:
> > + (set (attr "btver2_decode")
> > + (if_then_else
> > + (and (eq_attr "alternative" "2")
> > + (ma
On 04 Aug 15:31, Kirill Yukhin wrote:
> On 04 Aug 14:10, Uros Bizjak wrote:
> > On Tue, Aug 4, 2015 at 1:47 PM, Kirill Yukhin
> > wrote:
> > > Hello,
> > > - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
> > > - (set_
Hello,
Is it ok to backport the patch to gcc-5-branch?
--
Thanks, K
> On 04 Aug 15:31, Kirill Yukhin wrote:
>
> commit 1055739cb51648794a01afd85f59efadd14378ed
> Author: Kirill Yukhin
> Date: Mon Aug 3 15:21:06 2015 +0300
>
> Fix vec_concatv2df and vec_dupv2df to
Hello,
On 18 Sep 10:31, Richard Biener wrote:
> On Thu, 17 Sep 2015, Ilya Enkovich wrote:
>
> > 2015-09-16 15:30 GMT+03:00 Richard Biener :
> > > On Mon, 14 Sep 2015, Kirill Yukhin wrote:
> > >
> > >> Hello,
> > >> I'd like to initiate d
b43c76b9b2e1b02
commit c1d01f74051f65e75b0de73b1b43c76b9b2e1b02
Author: Kirill Yukhin
Date: Fri Sep 18 19:00:52 2015 +0300
Fix libgfortran/io/unix.c to allow not stable STAT for non MinGW.
diff --git a/libgfortran/io/unix.c b/libgfortran/io/unix.c
index b86bd67..772725a 100644
--- a/libgfo
cc/config/i386/i386.md (define_split not/xor SWI1248x): Use
iterator instead of fixed modes..
--
Thanks, K
commit fc8c797375b4fc8fc155070ccfcca52497991c48
Author: Kirill Yukhin
Date: Fri Sep 18 16:10:06 2015 +0300
AVX-512. Fix kxnor insn splits.
diff --git a/gcc/config/i386/i386
On 21 Sep 12:53, FX wrote:
> Dear Kirill,
>
> > When libgfortran is configured w/ HAVE_WORKING_STAT undefined
> > *and* current system is not MinGW - FIND_FILE_[DECL|ARGS} still
> > trying to use Windows's handles (id).
>
> Well, if HAVE_WORKING_STAT is not defined, then it means some other mecha
commit ffaaf5ad0460cd5bd85f6fd4b360fb1171eb273e
Author: Kirill Yukhin
Date: Fri Sep 18 14:03:54 2015 +0300
AVX-512. Introduce SKX CPU.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 75807f5..18da001 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -595,7 +595,7 @@ x86_64_archs=&qu
ckdi"): Ditto.
Is it ok for trunk and gcc-5-branch if testing pass?
--
Thanks, K
commit 433bd69b29c62d0c65e5a0772d564b0d930ee8c5
Author: Kirill Yukhin
Date: Fri Sep 18 13:51:26 2015 +0300
AVX-512. Fix patterns for kunpck insns.
diff --git a/gcc/config/i386/i386.md b/gcc/con
Hi Uroš, Jakub,
eOn 21 Sep 16:27, Jakub Jelinek wrote:
> On Mon, Sep 21, 2015 at 05:14:45PM +0300, Kirill Yukhin wrote:
> > Hello,
> > This patch introduces switches necessary for new Intel Server CPU
> > (code-named Skylake).
> >
> > Bootstrapped & regtes
Hello HJ,
On 21 Sep 07:40, H.J. Lu wrote:
> On Mon, Sep 21, 2015 at 7:14 AM, Kirill Yukhin
> wrote:
> > Hello,
> > This patch introduces switches necessary for new Intel Server CPU
> > (code-named Skylake).
> >
> > Bootstrapped & regtested.
>
Hello Uroš,
On 21 Sep 19:19, Uros Bizjak wrote:
> On Mon, Sep 21, 2015 at 6:57 PM, Kirill Yukhin
> wrote:
> > Patch in the bottom. Is it ok?
>
> Comments inline.
>
> > -native"
> > +native skylake-avx512"
>
> Please leave x86-64 and native at
Hello Alexander,
On 18 Sep 17:51, Alexander Fomin wrote:
> Hi,
> On Tue, Sep 08, 2015 at 11:41:50AM +0300, Kirill Yukhin wrote:
> > Hi,
> > So, here you'll emit, e.g. "pandq %xmm16, %xmm17"
> > If think it'll be better to attach AVX-512VL related suffi
n progress
Is it ok for trunk (if regtest pass)?
--
Thanks, K
commit 3a521c3cfd7044008635d1c813320d3667fc1e90
Author: Kirill Yukhin
Date: Tue Sep 22 16:48:50 2015 +0300
AVX-512. Add kshift[lr][bwdq]. Fix iterator.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2f8
Hello,
On 22 Sep 18:14, Kirill Yukhin wrote:
> Hello,
> Patch in the bottom fixes iterator for k insns
> since QI mode is only available for AVX-512DQ.
>
> It also adds support for kshift[rl][bwdq]. This patterns
> will be used for mask load/store autogeneration on which
On 24 Sep 11:20, Uros Bizjak wrote:
> On Thu, Sep 24, 2015 at 11:07 AM, Kirill Yukhin
> wrote:
> > Hello Uroš,
> > I've comitted (into main trunk) patch in the bottom which
> > checks first bit of ecx (instead of ebx) to verify of
> > AVX-512VBMI prese
Hello,
Patch in the bottom improves insns sequences for
strided loads.
E.g. on `-march=skylake-avx512' for this test:
unsigned char yy[1];
unsigned char xx[1];
void
__attribute__ ((noinline)) generateMTFValues (unsigned char s)
{
unsigned char i;
for (i = 0; i < s; i++)
.
--
Thanks, K
commit 5615034caed821c52f0a8c97966e0160f6dd9a5e
Author: Kirill Yukhin
Date: Thu Oct 1 16:57:52 2015 +0300
AVX-512. Mention all AVX-512 switches in invoke.texi.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ebfaaa1..b5f4b81 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc
On 01 Oct 17:51, Kirill Yukhin wrote:
> `make pdf` looks ok.
> Is it ok for trunk and gcc-5-branch (a week after check in to trunk)?
>
> gcc/
> * doc/invoke.texi: Mention -mavx512vl, -mavx512bw, -mavx512dq,
> -mavx521vbmi, -mavx512ifma. Add missing opindex-es.
Check
On 01 Oct 14:11, Kirill Yukhin wrote:
> Bootstrapped. New tests pass (fail w/o the change). Regtesting is in progress.
>
> Is it ok for trunk?
>
> gcc/
> * config/i386/i386.c (expand_vec_perm_even_odd_trunc): New.
> (expand_vec_perm_even_odd
--
Thanks, K
commit 39d9d882ed654e8b40095a24cb05baf661b81f3f
Author: Kirill Yukhin
Date: Fri Oct 2 18:08:33 2015 +0300
AVX-512. Add missing features to cpuinfo.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1ccc33e..1719175 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
get.c: Add check for "skylake-avx512".
--
Thanks, K
commit 230beb0d31a9463c8339975580142298138442f6
Author: Kirill Yukhin
Date: Fri Oct 2 19:03:21 2015 +0300
AVX-512. Add family/model to cpuinfo.c.
diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c
b/gcc/tests
Hello Uroš,
I've merged two patches together and rebased it
on top of gcc-5-branch. The only change I made compared
to trunk version is scheduling set to CPU_NEHALEM since
CPU_HASWELL is not supported in gcc-5.
Bootstrapped.
Is it ok for gcc-5-branch?
gcc/
* config.gcc: Support "skylake
One more missed hunk:
iff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c
b/gcc/testsuite/gcc.target/i386/builtin_target.c
index 9eb397e..cbca6b4 100644
--- a/gcc/testsuite/gcc.target/i386/builtin_target.c
+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -173,6 +173,10 @@ check_feat
Hello,
This obvious patch adds check for AES and PCLMUL cpuids.
gcc/testsuite/
* gcc.target/i386/builtin_target.c: Add check for AES and PCLMUL.
Updated test pass. Checked into main trunk.
--
Thanks, K
commit 6b4c0a8204ec5d311e4fef740ad8834cc4f5f5ff
Author: Kirill Yukhin
Date: Tue
Hi Richard,
On 06 Oct 09:36, Richard Biener wrote:
> The test now execute FAILs for me:
>
> FAIL: gcc.target/i386/builtin_target.c execution test
>
> I have family 6, model 94
Wow, Skylake!
Fixed. AVX-512VBMI bit lives in ecx, not ebx as rest of AVX-512.
gcc/testsuite/
* gcc.target/i386
> > This caused:
> >
> > FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
> >
> > on gcc-5-branch.
> >
>
> vect-perm-odd-1.s: Assembler messages:
> vect-perm-odd-1.s:233: Error: operand type mismatch for `vpor'
> vect-perm-odd-1.s:240: Error: operand type mismatch for `vpor'
>
>
Hi,
On 05 Oct 18:01, Uros Bizjak wrote:
> On Mon, Oct 5, 2015 at 5:54 PM, Alexander Fomin
> wrote:
> > This patch addresses PR target/67849. Given a machine that does not
> > support AVX512VL, following "else" branch for vec_exract_lo insn
> > may result in a split using YMMs from upper-bank, henc
PT, XSAVEC, and XSAVES features.
(struct __processor_model): Set type of __cpu_features array to
uint64_t.
(get_available_features): Add new features. Reorder according
to bit number.
--
Thanks, K
commit 839916b8d017fac166f76c317bdf5c38d5d15ea4
Author: Kirill Yukhin
D
Hi Uroš,
On 06 Oct 17:15, Uros Bizjak wrote:
> On Tue, Oct 6, 2015 at 3:36 PM, Kirill Yukhin wrote:
> > Hello,
> > Patch in the bottom adds missing options to libgcc/config/i386/cpuinfo.c
> > It also updates documentation.
> > As far as number of entries exceeded 32
Hello,
On 06 Oct 15:09, Kirill Yukhin wrote:
> > > This caused:
> > >
> > > FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
> > >
> > > on gcc-5-branch.
> > >
> >
> > vect-perm-odd-1.s: Assembler messages:
Hello,
On 08 Oct 20:31, Alexander Fomin wrote:
> Hi All,
>
> This patch addresses PR target/67895. For some AVX512 instructions
> we've used to emit embedded rounding/SAE specifier in a wrong place.
> The patch fixes its position for vrange* and vcvt?si2s* instructions.
> I've also updated regula
Hello,
On 07 Oct 11:09, Jeff Law wrote:
> On 10/05/2015 07:24 AM, Joseph Myers wrote:
> >On Mon, 5 Oct 2015, Kirill Yukhin wrote:
> >
> >>To enable vectorization of loops w/ calls to math functions it is reasonable
> >>to enable parsing of attribute vector
Hello,
On 14 Oct 13:40, Joseph Myers wrote:
> On Wed, 14 Oct 2015, Kirill Yukhin wrote:
>
> > Is it ok for trunk?
>
> This patch has no documentation. Documentation for new attributes must be
> added to extend.texi.
Fixed. Extra entry to gcc/Changelog:
*
Hi Jakub,
On 15 Oct 16:39, Jakub Jelinek wrote:
> On Thu, Oct 15, 2015 at 05:33:32PM +0300, Kirill Yukhin wrote:
> > --- a/gcc/doc/extend.texi
> > +++ b/gcc/doc/extend.texi
> > @@ -3066,6 +3066,20 @@ This function attribute make a stack protection of
> > the function i
Hello,
Patch in the bottom adds mentioning of new
`march=skylake-avx512' to gcc-6/changes.html.
Is it ok to install?
This switch was backported to gcc-5.
Is it ok to create a new section `GCC 5.3' and put it there
or I need to wait for actual release?
--
Thanks, K
Index: htdocs/gcc-6/changes.ht
On 17 Oct 02:37, Gerald Pfeifer wrote:
> On Fri, 16 Oct 2015, Kirill Yukhin wrote:
> > Is it ok to install?
>
> Yes, just add a "the" before "following".
>
> > This switch was backported to gcc-5.
> > Is it ok to create a new section `GCC 5.3&
Hello,
On 15 Oct 17:47, Kirill Yukhin wrote:
> Hi Jakub,
> On 15 Oct 16:39, Jakub Jelinek wrote:
> > On Thu, Oct 15, 2015 at 05:33:32PM +0300, Kirill Yukhin wrote:
> > > --- a/gcc/doc/extend.texi
> > > +++ b/gcc/doc/extend.texi
> > > @@ -3066,6 +3066,20
Hello Joseph,
On 22 Oct 12:48, Joseph Myers wrote:
> On Thu, 22 Oct 2015, Kirill Yukhin wrote:
>
> > Ping?
>
> You need to update this patch to take account of Marek's fix for bug 67964
> (it was because I was suspicious of the "continue;" in this patch
>
Hi Ilya,
On 08 Oct 18:32, Ilya Enkovich wrote:
> Hi,
>
> This patch adds patterns for vec_cmp optabs. Vector comparison expand code
> was moved from VEC_COND_EXPR expanders into a separate functions. AVX-512
> patterns use more simple masked versions.
>
> Thanks,
> Ilya
> --
> gcc/
>
> 2015-
Hello Joseph,
On 23 Oct 14:16, Joseph Myers wrote:
> On Fri, 23 Oct 2015, Kirill Yukhin wrote:
>
> > > You need to update this patch to take account of Marek's fix for bug
> > > 67964
> > > (it was because I was suspicious of the "continue;" in t
Hello Jakub,
Your inputs fixed.
On 27 Oct 15:15, Jakub Jelinek wrote:
> > diff --git a/gcc/omp-low.c b/gcc/omp-low.c
> > index ad7c017..232dc5c 100644
> > --- a/gcc/omp-low.c
> > +++ b/gcc/omp-low.c
> > @@ -17412,10 +17412,7 @@ public:
> > bool
> > pass_omp_simd_clone::gate (function *)
> > {
Hi Jakub,
On 29 Oct 09:54, Jakub Jelinek wrote:
> On Wed, Oct 28, 2015 at 12:16:04PM +0300, Kirill Yukhin wrote:
> > Bootstrapped. Regtested. Is it ok for trunk?
> >
> >
> > gcc/
> > * omp-low.c (pass_omp_simd_clone::gate): If target allows - ca
Hi Ilya,
On 08 Oct 18:42, Ilya Enkovich wrote:
> Hi,
>
> This patch reflects changes in maskload and maskstore optabs and adds
> patterns for AVX-512.
The patch is OK for trunk.
--
Thanks, K
>
> Thanks,
> Ilya
> --
> 2015-10-08 Ilya Enkovich
>
> * config/i386/sse.md (maskload): Rename
Hello Ilya
On 08 Oct 18:53, Ilya Enkovich wrote:
> Hi,
>
> This patch add patterns for vcond_mask_optab. No new expand code is
> required, existing ix86_expand_sse_movcc is used.
The patch is OK for trunk.
--
Thanks, K
>
> Thanks,
> Ilya
> --
> gcc/ChangeLog:
>
> 2015-10-08 Ilya Enkovich
>
Hello Ilya,
On 10 Nov 13:25, Ilya Enkovich wrote:
> On 19 Oct 15:30, Ilya Enkovich wrote:
> > Hi,
> >
> > This patch adds patterns to be used for vector masks pack/unpack for
> > AVX512. Bootstrapped and tested on x86_64-unknown-linux-gnu. Does it
> > look OK?
The patch is OK for trunk.
--
T
an especially using L, R or U for linear
> %val(), %ref() or %uval() (if references), not using s for linear with
> uniform parameter stride, but instead using ls, Ls, Rs or Us for those?
Yes, we'll update it.
--
Thanks, K
On 10 Nov 09:58, Jakub J
Hello Alan,
On 16 Nov 12:23, Alan Lawrence wrote:
> On 03/11/15 14:27, Alan Lawrence wrote:
> >This migrates the various reduction optabs in sse.md to use the
> >reduce-to-scalar
> >form. I took the straightforward approach (equivalent to the migration code
> >in
> >expr.c/optabs.c) of generating
Hello Andreas, Devid.
On 18 Nov 10:45, Andreas Schwab wrote:
> Kirill Yukhin writes:
>
> > diff --git a/gcc/testsuite/c-c++-common/attr-simd.c
> > b/gcc/testsuite/c-c++-common/attr-simd.c
> > new file mode 100644
> > index 000..b4eda34
> > --- /dev/null
Hello Kyrill,
On 20 Nov 12:15, Kyrill Tkachov wrote:
> >gcc/tessuite/
> > * c-c++-common/attr-simd-3.c: Put xfail (PR68158) on dg-error.
>
> This test fails on bare-metal targets that don't support -fcilkplus or
> -pthread.
> Would you consider moving them to the cilkplus testing directory or
gcc/
* config/i386/i386.md (define_mode_iterator SWI1248_AVX512BW): New.
(define_insn "*k"): Use new iterator.
--
Thanks, K
commit 91b7010c935d35368e0de7524a2c1f4c5ee139ff
Author: Kirill Yukhin
Date: Wed Nov 25 11:23:08 2015 +0300
AVX-512. Allow QI mode k operations using 1
> Masks QI mode size are of extreme importance for AVX-512F,
> so I propose to modify my commit [1] and allow kmovb to be
> generated on non- AVX512DQ targets.
Forgot to put the link
[1] - https://gcc.gnu.org/ml/gcc-patches/2015-09/msg01660.html
--
Thanks, K
b2f7270d33def74a4cc9579def5d6cb950577d
Author: Kirill Yukhin
Date: Thu Nov 26 15:32:47 2015 +0300
AVX-512. Fix vec_extract_hi_ constraints.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e7b517a..680d813 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -753
* c-c++-common/attr-simd-4.c: New test.
* c-c++-common/attr-simd-5.c: New test.
--
Thanks, K
>
> Jakub
commit cf458a0a00214022556498bdda94a07d0af70574
Author: Kirill Yukhin
Date: Mon Nov 30 16:24:39 2015 +0300
[attr-simd] Add notinbranch/inbranch flags.
diff
Hello,
On 30 Nov 13:46, Kirill Yukhin wrote:
> Hello,
> Patch in the bottom splits masked version of vec_extract_hi_
> to block AVX-1512VL insn generation for KNL and cures ICE on
> spec2k6/450.soplex.
>
> Bootstrapped and regtesed.
>
> If no objections - I'll
4f5b84ab30628b34a3
Author: Kirill Yukhin
Date: Tue Dec 1 10:28:17 2015 +0300
AVX-512. Make broadcast from SSE reg AVX-512 only. Force to zmm.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e7b517a..0286e6b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.
Hi Ilya,
On 02 Dec 16:51, Ilya Enkovich wrote:
> Hi,
>
> This patch fixes wrong alignment check in _store_mask
> pattern. Currently we check a register operand instead of a memory
> one. This fixes segfault on 481.wrf compiled at -O3 for KNL target.
> I bootstrapped and tested this patch on x86_
(define_insn "kunpcksi"): Ditto.
(define_insn "kunpckdi"): Ditto.
gcc/testsuite
PR target/68633
* gcc.target/i386/pr68633.c: New test.
--
Thanks, K
commit 2379ca2e6a65c6373dde7c3f0b778216293f229d
Author: Kirill Yukhin
Date: Tue Dec 1 14:38:22 2015 +0
Hello,
On 08 Dec 09:47, Andreas Schwab wrote:
> FAIL: gfortran.dg/pr68627.f -O (test for excess errors)
> Excess errors:
> gfortran: error: unrecognized command line option '-mavx512f'
Thanks for pointing.
I've checked in this as obvious:
gcc/testsuite:
* gfortran.dg/pr68627.f: Limit t
On 08 Dec 13:01, Uros Bizjak wrote:
> On Tue, Dec 8, 2015 at 11:40 AM, Kirill Yukhin
> wrote:
> > Hello,
> > On 08 Dec 09:47, Andreas Schwab wrote:
> >> FAIL: gfortran.dg/pr68627.f -O (test for excess errors)
> >> Excess errors:
> >> gfor
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