Hello,
Patch in the bottom splits masked version of vec_extract_hi_<mode>
to block AVX-1512VL insn generation for KNL and cures ICE on spec2k6/450.soplex.
Bootstrapped and regtesed.
If no objections - I'll commit on Wednesday.
gcc/
* config/i386/sse.md (define_insn "vec_extract_hi_<mode>_maskm"):
Remove "prefix_extra".
(define_insn "vec_extract_hi_<mode>_mask"): New.
(define_insn "vec_extract_hi_<mode>"): Remove masking.
gcc/testsuite/
* gcc.target/i386/avx512vl-vextractf32x4-1.c: Fix scan pattern.
--
Thanks, K
commit 69b2f7270d33def74a4cc9579def5d6cb950577d
Author: Kirill Yukhin <kirill.yuk...@intel.com>
Date: Thu Nov 26 15:32:47 2015 +0300
AVX-512. Fix vec_extract_hi_<mode> constraints.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e7b517a..680d813 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7534,32 +7534,40 @@
&& rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
-(define_insn "vec_extract_hi_<mode><mask_name>"
- [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
"=<store_mask_constraint>")
+(define_insn "vec_extract_hi_<mode>_mask"
+ [(set (match_operand:<ssehalfvecmode> 0 "register_operand" "=v")
+ (vec_merge:<ssehalfvecmode>
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI4F_256 1 "register_operand" "v")
+ (parallel [(const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)]))
+ (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "0C")
+ (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
+ "TARGET_AVX512VL"
+ "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
+ [(set_attr "type" "sselog1")
+ (set_attr "length_immediate" "1")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vec_extract_hi_<mode>"
+ [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xm, vm")
(vec_select:<ssehalfvecmode>
- (match_operand:VI4F_256 1 "register_operand" "v")
+ (match_operand:VI4F_256 1 "register_operand" "x, v")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
- "TARGET_AVX && <mask_avx512vl_condition>"
-{
- if (TARGET_AVX512VL)
- return "vextract<shuffletype>32x4\t{$0x1, %1,
%0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
- else
- return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
-}
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
+ "TARGET_AVX"
+ "@
+ vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}
+ vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}"
+ [(set_attr "isa" "*, avx512vl")
+ (set_attr "prefix" "vex, evex")
+ (set_attr "type" "sselog1")
(set_attr "length_immediate" "1")
- (set (attr "prefix")
- (if_then_else
- (match_test "TARGET_AVX512VL")
- (const_string "evex")
- (const_string "vex")))
(set_attr "mode" "<sseinsnmode>")])
(define_insn_and_split "vec_extract_lo_v32hi"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vextractf32x4-1.c
b/gcc/testsuite/gcc.target/i386/avx512vl-vextractf32x4-1.c
index c01835c..26313f4 100644
--- a/gcc/testsuite/gcc.target/i386/avx512vl-vextractf32x4-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-vextractf32x4-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mavx512vl -O2" } */
-/* { dg-final { scan-assembler-times "vextractf32x4\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vextractf(?:128|32x4)\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vextractf32x4\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vextractf32x4\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
