Re: [PATCH] RISC-V: xtheadfmemidx: Disable if xtheadmemidx is not available

On 12/5/23 08:16, Christoph Müllner wrote: XTheadMemIdx provides register-register offsets for GP register loads/stores. XTheadFMemIdx does the same for FP registers. We've observed an issue with XTheadFMemIdx-only builds, where FP registers have been promoted to GP registers: (insn 26 22 5

Re: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.

On 12/5/23 06:59, Roger Sayle wrote: This patch improves the code generated for bitfield sign extensions on ARC cpus without a barrel shifter. Compiling the following test case: int foo(int x) { return (x<<27)>>27; } with -O2 -mcpu=em, generates two loops: foo:mov lp_count,27

Re: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.

On 12/7/23 09:04, Roger Sayle wrote: Hi Jeff, Doh! Great catch. The perils of not (yet) being able to actually run any ARC execution tests myself. ACK. Shouldn't operands[4] be GEN_INT ((HOST_WIDE_INT_1U << tmp) - 1)? Yes(-ish), operands[4] should be GEN_INT(HOST_WIDE_INT_1U << (tmp

Re: [PATCH V2 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

On 12/7/23 09:59, Christoph Müllner wrote: On Thu, Dec 7, 2023 at 11:18 AM Liao Shihua wrote: In accordance with the suggestions of Christoph Müllner, the following amendments are made Update v1 -> v2: 1. Rename *_intrinsic-* to *_intrinsic-XLEN. 2. Typo fix. 3. Intrinsics with i

Re: [PATCH] testsuite: scev: expect fail on ilp32

On 12/7/23 09:33, Hans-Peter Nilsson wrote: Date: Mon, 4 Dec 2023 12:58:03 +0100 (CET) From: Richard Biener On Sat, 2 Dec 2023, Hans-Peter Nilsson wrote: Date: Fri, 1 Dec 2023 08:07:14 +0100 (CET) From: Richard Biener I read from your messages that the testcases pass on arm*-*-*? Yes: t

Re: [PATCH] RISC-V: Fix AVL propagation ICE for vleff/vlsegff

On 12/7/23 05:15, Robin Dapp wrote: LGTM. Btw your vsetvl patch from yesterday fixes the vectorized strlen/strcmp problems. Those use vleff as first instruction. Definitely good news. jeff

Re: [PATCH] treat argp-based mem as frame related in dse

On 12/6/23 02:27, Jiufu Guo wrote: Hi, The issue mentioned in PR112525 would be able to be handled by updating dse.cc to treat arg_pointer_rtx similarly with frame_pointer_rtx. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30271#c10 also mentioned this idea.

Re: [PATCH] Expand: Pass down equality only flag to cmpmem expand

On 11/28/23 00:43, HAO CHEN GUI wrote: Hi, This patch passes down the equality only flags from emit_block_cmp_hints to cmpmem optab so that the target specific expand can generate optimized insns for equality only compare. Targets (e.g. rs6000) can generate more efficient insn sequence if t

Re: [PATCH 1/5][V3][ifcvt] optimize x=c ? (y op z) : y by RISC-V Zicond like insns

On 12/5/23 01:12, Fei Gao wrote: op=[PLUS, MINUS, IOR, XOR] Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc op rd, rs1, rd Conditional op, if non-zero rd = (rc != 0) ? (rs1 op rs2) : rs1 --> czero.eqz rd, rs2, rc op rd, rs1, rd Co-authored-by: Xiao Zeng

Re: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.

On 12/5/23 06:59, Roger Sayle wrote: This patch improves the code generated for bitfield sign extensions on ARC cpus without a barrel shifter. Compiling the following test case: int foo(int x) { return (x<<27)>>27; } with -O2 -mcpu=em, generates two loops: foo:mov lp_count,27

[committed] Fix length computation for logical shifts on H8

ation opportunities on the H8/SX. A slightly different version of this patch has been tested on the H8 without regressions. Pushed to the trunk, Jeff commit 4ac358c619e364ad767242409765c178da9d83e0 Author: Jeff Law Date: Sun Dec 10 09:32:55 2023 -0700 [committed] Fix length computatio

[committed] Fix length computation of single bit bitfield extraction on H8

ction. Account for that in the length computation. This was spotted when looking at regressions in the generalized signed bitfield extraction pattern. This has been regression tested on the H8 port. Pushing to the trunk, Jeff commit 1f55c5cc698519094f751257db62ff274c015fdc Author: Jeff Law Date:

[committed] Provide patterns for signed bitfield extractions on H8

ested on the H8 port without errors. Installing on the trunk. Jeffcommit 73f6e1fe8835085ccc6de5c5f4428d47e853913b Author: Jeff Law Date: Sun Dec 10 10:29:23 2023 -0700 [committed] Provide patterns for signed bitfield extractions on H8 Inspired by Roger's work on the ARC po

[committed] Support uaddv and usubv on the H8

the bit from CCR into the right position in a GPR and other quirks of the H8. This has been regression tested on the H8 without problems. Pushing to the trunk. Jeffcommit 7fb9454c748632d148a07c275ea1f77b290b0c2d Author: Jeff Law Date: Sun Dec 10 10:41:05 2023 -0700 [committed] Support

Re: [PING] PR112380: Defend against CLOBBERs in RTX expressions in combine.cc

On 12/10/23 07:56, Roger Sayle wrote: I'd like to ping my patch for PR rtl-optimization/112380. https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636203.html Sorry, I'd hoped Segher would chime in. The first simple patch & testcase are OK and can go in immediately. It'll take more ti

Re: [PATCH] multiflags: fix doc warning

On 12/8/23 19:48, Alexandre Oliva wrote: Comply with dubious doc warning that after an @xref there must be a comma or a period, not a close parentheses. Build-testing on x86_64-linux-gnu now. Ok to install? for gcc/ChangeLog * doc/invoke.texi (multiflags): Add period after @xref

Re: [PATCH] -finline-stringops: don't assume ptr_mode ptr in memset [PR112804]

On 12/8/23 19:25, Alexandre Oliva wrote: On aarch64 -milp32, and presumably on other such targets, ptr can be in a different mode than ptr_mode in the testcase. Cope with it. Regstrapped on x86_64-linux-gnu, also tested the new test on aarch64-elf. Ok to install? for gcc/ChangeLog

Re: [PATCH] treat argp-based mem as frame related in dse

On 12/8/23 00:18, Jiufu Guo wrote: Hi, Jeff Law writes: On 12/6/23 02:27, Jiufu Guo wrote: Hi, The issue mentioned in PR112525 would be able to be handled by updating dse.cc to treat arg_pointer_rtx similarly with frame_pointer_rtx. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30271

Re: [PATCH 2/5] [ifcvt] optimize x=c ? (y shift_op z):y by RISC-V Zicond like insns

On 12/5/23 01:12, Fei Gao wrote: op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT] Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc op rd, rs1, rd Conditional op, if non-zero rd = (rc != 0) ? (rs1 op rs2) : rs1 --> czero.eqz rd, rs2, rc op rd, rs1, rd Co

Re: [PATCH 3/5] [ifcvt] optimize x=c ? (y AND z) : y by RISC-V Zicond like insns

On 12/5/23 01:12, Fei Gao wrote: Take the following case for example. CFLAGS: -march=rv64gc_zbb_zicond -mabi=lp64d -O2 long test_AND_ceqz (long x, long y, long z, long c) { if (c) x = y & z; else x = y; return x; } Before patch: and a2,a1,a2 czero.eqz a0,a2,a3

Re: [PATCH 4/5] [ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like insns

On 12/5/23 01:12, Fei Gao wrote: op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND] Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is shift like operation (noce_cond_zero_binary_op_supported)

Re: [PATCH 5/5] [ifcvt] optimize extension for x=c ? (y op z) : y by RISC-V Zicond like insns

On 12/5/23 01:12, Fei Gao wrote: SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered to support SImode in 64-bit machine. Co-authored-by: Xiao Zeng gcc/ChangeLog: * ifcvt.cc (noce_cond_zero_binary_op_supported): add support for extension (noce_bbs_ok_for_cond_zero_arit

Re: [PATCH] -finline-stringops: don't assume ptr_mode ptr in memset [PR112804]

On 12/10/23 15:38, Alexandre Oliva wrote: On Dec 10, 2023, Jeff Law wrote: On 12/8/23 19:25, Alexandre Oliva wrote: On aarch64 -milp32, and presumably on other such targets, ptr can be in a different mode than ptr_mode in the testcase. Cope with it. Regstrapped on x86_64-linux-gnu, also

Re: [PATCH 2/5] [ifcvt] optimize x=c ? (y shift_op z):y by RISC-V Zicond like insns

On 12/10/23 21:01, Fei Gao wrote: On 2023-12-11 04:43  Jeff Law wrote: On 12/5/23 01:12, Fei Gao wrote: op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT] Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc op rd, rs1, rd Conditional op, if non-zero

Re: [PATCH] treat argp-based mem as frame related in dse

On 12/10/23 20:07, Jiufu Guo wrote: I'm having a bit of a hard time convincing myself this is correct though. I can't see how rewriting the load to read the source of the prior store is unsafe. If that fixes a problem, then it would seem like we've gone wrong before here -- perhaps failing

Re: [PATCH] Treat "p" in asms as addressing VOIDmode

On 11/27/23 05:12, Richard Sandiford wrote: check_asm_operands was inconsistent about how it handled "p" after RA compared to before RA. Before RA it tested the address with a void (unknown) memory mode: case CT_ADDRESS: /* Every address operand can be reloaded to f

Re: [PATCH] wrong code on m68k with -mlong-jump-table-offsets and -malign-int (PR target/112413)

On 12/11/23 05:51, Mikael Pettersson wrote: On m68k the compiler assumes that the PC-relative jump-via-jump-table instruction and the jump table are adjacent with no padding in between. When -mlong-jump-table-offsets is combined with -malign-int, a 2-byte nop may be inserted before the jump t

Re: [PATCH] treat argp-based mem as frame related in dse

On 12/11/23 02:26, Jiufu Guo wrote: Hi, Thanks for your quick reply! Jeff Law writes: On 12/10/23 20:07, Jiufu Guo wrote: I'm having a bit of a hard time convincing myself this is correct though. I can't see how rewriting the load to read the source of the prior store is u

Re: [PATCH] untyped calls: enable target switching [PR112334]

On 12/1/23 08:10, Alexandre Oliva wrote: On Dec 1, 2023, Alexandre Oliva wrote: Also tested on arm-eabi, but it's *not* enough (or needed) to fix the PR, there's another bug lurking there, with a separate patch coming up. Here it is. The computation of apply_args_size and apply_re

Re: [PATCH] libgccjit Fix a RTL bug for libgccjit

On 11/20/23 16:54, David Malcolm wrote: On Mon, 2023-11-20 at 16:38 -0700, Jeff Law wrote: On 11/20/23 15:46, David Malcolm wrote: On Fri, 2023-11-17 at 14:09 -0700, Jeff Law wrote: On 11/17/23 14:08, Antoni Boucher wrote: In contrast with the other frontends, libgccjit can be

Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.

On 11/20/23 12:14, Jiawei wrote: Supports RISC-V profiles[1] in -march option. Default input set the profile is before other formal extensions. [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc gcc/ChangeLog: * common/config/riscv/riscv-common.cc (struct riscv_pro

Re: [V2] New pass for sign/zero extension elimination -- not ready for "final" review

On 11/29/23 21:10, Joern Rennecke wrote: I originally computed mmask in carry_backpropagate from XEXP (x, 0), but abandoned that when I realized we also get called for RTX_OBJ things. I forgot to adjust the SIGN_EXTEND code, though. Fixed in the attached revised patch. Also made sure to n

Re: [PATCH DejaGNU 1/1] Support per-test execution timeout factor

On 12/12/23 07:04, Maciej W. Rozycki wrote: Add support for the `test_timeout_factor' global variable letting a test case scale the wait timeout used for code execution. This is useful for particularly slow test cases for which increasing the wait timeout globally would be excessive.

Re: [PATCH GCC 1/1] testsuite: Support test execution timeout factor as a keyword

On 12/12/23 07:04, Maciej W. Rozycki wrote: Add support for the `dg-test-timeout-factor' keyword letting a test case scale the wait timeout used for code execution, analogously to `dg-timeout-factor' used for code compilation. This is useful for particularly slow test cases for which increasi

[PATCH][committed] RISC-V: Add multiarch support on riscv-linux-gnu

This adds multiarch support to the RISC-V port so that bootstraps work with Debian out-of-the-box. Without this patch the stage1 compiler is unable to find headers/libraries when building the stage1 runtime. This is functionally (and possibly textually) equivalent to Debian's fix for the sa

Re: [PATCH][committed] RISC-V: Add multiarch support on riscv-linux-gnu

On 8/22/23 12:03, Palmer Dabbelt wrote: On Tue, 22 Aug 2023 10:39:38 PDT (-0700), Jeff Law wrote: The docs seem to suggest that we should have a multarch-compatible MULTILIB_OSDIRNAMES as we support both multilib and multiarch:    @code{MULTIARCH_DIRNAME} is not used for

[committed] Improve quality of code from LRA register elimination

This is primarily Jivan's work, I'm mostly responsible for the write-up and coordinating with Vlad on a few questions. On targets with limitations on immediates usable in arithmetic instructions, LRA's register elimination phase can construct fairly poor code. This example (from the GCC test

[committed] RISC-V: Fix minor testsuite problem with zicond

ommit 3cd2b73079bac374ce1c542b9c9e354e00a8713d Author: Jeff Law Date: Fri Aug 25 16:23:06 2023 -0600 [committed] RISC-V: Fix minor testsuite problem with zicond I thought I had already fixed this, but clearly if I did, I didn't include it in any upstream commits. Wi

[committed] RISC-V: Make stack_save_restore tests more robust

Spurred by Jivan's patch and a desire for cleaner testresults, I went ahead and make the stack_save_restore tests independent of the precise stack size by using a regexp. Pushed to the trunk. Jeffcommit e1f096a3cc96c71907cfbc7b8baf67a3d863cb6d Author: Jeff Law Date: Fri Aug 25 16:

[committed] RISC-V: Fix xtheadcondmov-indirect.c

b3b13fb1cbad6e5836dee947e85d2954bcacabed Author: Jeff Law Date: Sun Aug 27 12:38:30 2023 -0600 RISC-V: Fix xtheadcondmov-indirect.c The pressure sensitive scheduling change perturbs the output ever so slightly for this test. Seemed easiest to just turn that off rather than generalize the

[committed] RISC-V: Fix spill-12 test

Jivan's recent work on IRA results in more efficient code for this test. This adjusts the expected output for the removal of 5 instructions and conversion of an addi into a simple mv. Pushed to the trunk, Jeffcommit 6567837fd823a93f7f7948a73ff9dc1153592e8c Author: Jeff Law Date: Su

[committed] RISC-V: Fix spill-11.c testsuite failure

Jivan's work also results in using a different save/restore function for the spill-11 test. So the expected output needs minor adjusting. Committed to the trunk. Jeff commit 3745feb19ed072e0865b12a891d7dbf7ba12c337 Author: Jeff Law Date: Sun Aug 27 13:00:13 2023 -0600 RISC-V

[committed] RISC-V: Use splitter to generate zicond in another case

single bit sign extension as the condition to a czero in the desired form. gcc/testsuite * gcc.target/riscv/zicond-xor-01.c: New test. Co-authored-by: Jeff Law diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 25f21d33487..4619220e

Re: [PATCH 01/12] mode-switching: Tweak the macro/hook documentation

On 11/5/23 11:46, Richard Sandiford wrote: I found the documentation for the mode-switching macros/hooks a bit hard to follow at first. This patch tries to add the information that I think would have made it easier to understand. Of course, documentation preferences are personal, and so I co

Re: [PATCH 02/12] mode-switching: Add note problem

On 11/5/23 11:46, Richard Sandiford wrote: optimize_mode_switching uses REG_DEAD notes to track register liveness, but it failed to tell DF to calculate up-to-date notes. Noticed by inspection. I don't have a testcase that fails because of this. gcc/ * mode-switching.cc (optimize_mo

Re: [PATCH 03/12] mode-switching: Avoid quadractic list operation

On 11/5/23 11:47, Richard Sandiford wrote: add_seginfo chained insn information to the end of a list by starting at the head of the list. This patch avoids the quadraticness by keeping track of the tail pointer. gcc/ * mode-switching.cc (add_seginfo): Replace head pointer with

Re: [PATCH 04/12] mode-switching: Fix the mode passed to the emit hook

On 11/5/23 11:47, Richard Sandiford wrote: optimize_mode_switching passes an entity's current mode (if known) to the emit hook. However, the mode that it passed ignored the effect of the after hook. Instead, the mode for the first emit call in a block was taken from the incoming mode, wherea

Re: [PATCH 05/12] mode-switching: Simplify recording of transparency

On 11/5/23 11:47, Richard Sandiford wrote: For a given block, an entity is either transparent for all modes or for none. Each update to the transparency set therefore used a loop like: for (i = 0; i < no_mode; i++) clear_mode_bit (transp[bb->index], j, i);

Re: [PATCH 06/12] mode-switching: Tweak entry/exit handling

On 11/5/23 11:48, Richard Sandiford wrote: An entity isn't transparent in a block that requires a specific mode. optimize_mode_switching took that into account for normal insns, but didn't for the exit block. Later patches misbehaved because of this. In contrast, an entity was correctly mark

Re: [PATCH 07/12] mode-switching: Allow targets to set the mode for EH handlers

On 11/5/23 11:48, Richard Sandiford wrote: The mode-switching pass already had hooks to say what mode an entity is in on entry to a function and what mode it must be in on return. For SME, we also want to say what mode an entity is guaranteed to be in on entry to an exception handler. gcc/

Re: [PATCH 08/12] mode-switching: Pass set of live registers to the needed hook

On 11/5/23 11:48, Richard Sandiford wrote: The emit hook already takes the set of live hard registers as input. This patch passes it to the needed hook too. SME uses this to optimise the mode choice based on whether state is live or dead. The main caller already had access to the required in

Re: [PATCH 09/12] mode-switching: Pass the set of live registers to the after hook

On 11/5/23 11:49, Richard Sandiford wrote: This patch passes the set of live hard registers to the after hook, like the previous one did for the needed hook. gcc/ * target.def (mode_switching.after): Add a regs_live parameter. * doc/tm.texi: Regenerate. * config/epipha

Re: RISC-V patchworks call tomorrow ?

On 11/6/23 18:19, Vineet Gupta wrote: Do we have call tomorrow, given some folks are traveling for RV Summit ? I'll be in the air, so "no" from me. jeff

Re: [PATCH 10/12] mode-switching: Use 1-based edge aux fields

On 11/5/23 11:49, Richard Sandiford wrote: The pass used the edge aux field to record which mode change should happen on the edge, with -1 meaning "none". It's more convenient for later patches to leave aux zero for "none", and use numbers based at 1 to record a change. gcc/ * mode-s

Re: [PATCH 11/12] mode-switching: Add a target-configurable confluence operator

On 11/5/23 11:50, Richard Sandiford wrote: The mode-switching pass assumed that all of an entity's modes were mutually exclusive. However, the upcoming SME changes have an entity with some overlapping modes, so that there is sometimes a "superunion" mode that contains two given modes. We can

Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV

On 11/6/23 15:35, Juzhe-Zhong wrote: RVV is variable length vector but also has 256 bit VLS mode vector. This test is vectorized as: f: vsetivlizero,8,e32,m2,ta,ma vle32.v v2,0(a0) vmv.v.i v4,1 vle16.v v1,0(a1) vmseq.vvv0,v2,v4

Re: [PATCH] test: Fix FAIL of bb-slp-cond-1.c for RVV

On 11/6/23 16:03, Juzhe-Zhong wrote: This patch fixes: FAIL: gcc.dg/vect/bb-slp-cond-1.c -flto -ffat-lto-objects scan-tree-dump-times vect "loop vectorized" 1 FAIL: gcc.dg/vect/bb-slp-cond-1.c scan-tree-dump-times vect "loop vectorized" 1 For RVV, "loop vectorized" appears 2 times instead o

Re: [PATCH] test: Fix XPASS of bb-slp-43.c for RVV

On 11/6/23 20:30, juzhe.zh...@rivai.ai wrote: >> So will this create a FAIL if someone runs the testsuite with the autovec preference set to scalable? No, it won't. Since it is always -fno-vect-cost-model. When a scalable vector doesn't have 256bit vector,  it always XFAIL, for example, AR

Re: [PATCH] test: Fix FAIL of SAD tests for RVV

On 11/6/23 20:36, Juzhe-Zhong wrote: RVV didn't explicitly enable SAD optab but we can vectorize it since loop vectorizer is able to recognize SAD pattern for RVV during analysis. Current scan check of explicit SAD pattern looks odd, it should be more reasonable to check recognition of SAD pa

Re: [PATCH] test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV#

On 11/6/23 20:50, Juzhe-Zhong wrote: RVV didn't explictly enable DIV_POW2 optab but we cen vectorize it. We should check pattern recognition instead of explicit pattern check. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-sdiv-pow2-1.c: Fix dump check. Similar to the sad test -- OK onc

Re: [PATCH] RISC-V: VECT: Remember to assert any_known_not_updated_vssa

On 11/6/23 06:18, Kito Cheng wrote: Oh, you're right! I should have checked the master branch first... and I was even wondering why it wasn't marked as such. Should perhaps cherry pick this for gcc-13-with-riscv-opts? gcc-13-with-riscv-opts mostly maintained by Ventana folks, so maybe ask

Re: [PATCH] Reduce false positives for -Wnonnull for VLA parameters [PR98541]

On 11/6/23 20:58, Hans-Peter Nilsson wrote: From: Martin Uecker Date: Tue, 31 Oct 2023 20:05:09 +0100 Reduce false positives for -Wnonnull for VLA parameters [PR98541] This patch limits the warning about NULL arguments to VLA parameters declared [static n].

Re: [PATCH V2] RISC-V: Early expand DImode vec_duplicate in RV32 system

On 11/6/23 07:12, Juzhe-Zhong wrote: An ICE was discovered in recent rounding autovec support: config/riscv/riscv-v.cc:4314 65 | } | ^ 0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**, rtx_def*, bool) /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RI

Re: [PATCH 10/12] mode-switching: Use 1-based edge aux fields

On 11/7/23 17:35, Richard Sandiford wrote: I could have sworn that there was something that checked that passes left edge aux fields clear, but it looks like I misremembered. So I probably need to stick a clear_aux_for_edges () call above the first main loop (for 12/12) and keep the initiali

Re: [PATCH 07/12] mode-switching: Allow targets to set the mode for EH handlers

On 11/7/23 17:15, Richard Sandiford wrote: Thanks for the reviews. Jeff Law writes: On 11/5/23 11:48, Richard Sandiford wrote: The mode-switching pass already had hooks to say what mode an entity is in on entry to a function and what mode it must be in on return. For SME, we also want to

Re: [PATCH] gcc.dg/Wmissing-parameter-type*: Test the intended warning

On 11/8/23 01:53, Florian Weimer wrote: gcc/testsuite/ChangeLog: * gcc.dg/Wmissing-parameter-type.c: Build with -std=gnu89 to trigger the -Wmissing-parameter-type warning and not the default -Wimplicit warning. Also match against -Wmissing-parameter-type.

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

On 11/8/23 02:40, Richard Sandiford wrote: Lehua Ding writes: Hi, These patchs try to support subreg coalesce feature in register allocation passes (ira and lra). Thanks a lot for the series. This is definitely something we've needed for a while. I probably won't be able to look at it i

Re: [PATCH] testsuite: force PIC/PIE off for pr58245-1.C

On 11/8/23 08:57, Alexandre Oliva wrote: This test expects a single mention of stack_chk_fail, as part of a call sequence, but when e.g. PIE is enabled by default, we output .hidden stack_chk_fail_local, which makes for a count mismatch. Disable PIC/PIE so as to not depend on the configurabl

Re: [PATCH] skip debug stmts when assigning locus discriminators

On 11/8/23 08:51, Alexandre Oliva wrote: c-c++-common/goacc/kernels-loop-g.c has been failing (compare-debug) on i686-linux-gnu since r13-3172, because the implementation enabled debug stmts to cause discriminators to be assigned differently, and the discriminators are printed in the .gkd dum

Re: [committed] RISC-V: Fix INSN costing and more zicond tests

On 11/9/23 07:33, Maciej W. Rozycki wrote: On Fri, 29 Sep 2023, Jeff Law wrote: So this ends up looking a lot like the bits that I had to revert several weeks ago :-) The core issue we have is given an INSN the generic code will cost the SET_SRC and SET_DEST and sum them. But that'

Re: [committed] RISC-V: Fix INSN costing and more zicond tests

On 11/9/23 07:33, Maciej W. Rozycki wrote: On Fri, 29 Sep 2023, Jeff Law wrote: So this ends up looking a lot like the bits that I had to revert several weeks ago :-) The core issue we have is given an INSN the generic code will cost the SET_SRC and SET_DEST and sum them. But that'

Re: [PATCH] minimal support for xtheadv

On 11/9/23 01:38, Yixuan Chen wrote: Hi Kito and Christoph, XYenChi (oriachi...@gmail.com ) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so po

Re: [PATCH v2] DSE: Allow vector type for get_stored_val when read < store

On 11/8/23 23:08, pan2...@intel.com wrote: From: Pan Li Update in v2: * Move vector type support to get_stored_val. Original log: This patch would like to allow the vector mode in the get_stored_val in the DSE. It is valid for the read rtx if and only if the read bitsize is less than the s

Re: [PATCH] RISC-V: VECT: Remember to assert any_known_not_updated_vssa

On 11/6/23 06:01, Maxim Blinov wrote: From: Maxim Blinov This patch is based on and intended for the vendors/riscv/gcc-13-with-riscv-opts branch - please apply if looks OK. Fixes the following ICEs that I'm seeing: FAIL: gcc.dg/vect/O3-pr49087.c (internal compiler error: in vect_transfor

Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

On 11/8/23 04:09, Mary Bennett wrote: +;; XCVELW builtins +(define_insn "riscv_cv_elw_elw_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))] + UNSPECV_CV_ELW))] + + "TARGET_XCVELW && !TARGET_64BIT" + "cv.elw\t

Re: [PATCH] RISC-V: Move cond_copysign from combine pattern to autovec pattern

On 11/9/23 16:33, Juzhe-Zhong wrote: Since cond_copysign has been support into match.pd (middle-end). We don't need to support conditional copysign by RTL combine pass. Instead, we can support it by direct explicit cond_copysign optab. conditional copysign tests are already available in the

Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.

On 11/9/23 15:43, 钟居哲 wrote: Hi. Robin. [ ... ] You may need a development version of binutils to get the zfh/zvfh support and unreleased patches to get zfb/zvfb support. Probably the easiest thing to do would be to look in the gcc.log file at those failures and see what the excess failur

[committed] Improve single bit zero extraction on H8.

momentarily. jeff ps. Yes, supporting extraction of multi-bit fields might be improvable as well. But I've already spent more time on this than I can reasonably justify. commit 57dbc02d261bb833f6ef287187eb144321dd595c Author: Jeff Law Date: Thu Nov 9 17:34:01 2023 -0700 [committed]

Re: [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors

On 11/8/23 04:09, Mary Bennett wrote: gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. Bikeshedding alert... Usually we keep constraint names pretty small. It helps when you've got patterns that may have many constraints.

Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.

On 11/9/23 18:09, juzhe.zh...@rivai.ai wrote: I am already using master branch. The FAIL is: xgcc: fatal error: Cannot find suitable multilib set for '-march=rv64imafdcv_zicsr_zifencei_zfhmin_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvl128b_zvl32b_zvl64b'/'-mabi=lp64d' That's an multilib conf

Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.

On 11/9/23 18:12, juzhe.zh...@rivai.ai wrote: How to fix it ? I am pretty noob on testing CI. Can Robin fix that? It's most likely a problem on your side with how you've configured the toolchain. I don't think this is somethign Robin can fix for you. jeff

Re: [PATCH 12/12] mode-switching: Add a backprop hook

On 11/5/23 11:50, Richard Sandiford wrote: This patch adds a way for targets to ask that selected mode changes be brought forward, through a combination of: (1) requiring a mode in blocks where the entity was previously transparent (2) pushing the transition at the head of a block onto

Re: [PATCH] g++: Rely on dg-do-what-default to avoid running pr102788.cc on non-vector targets

On 11/2/23 17:45, Patrick O'Neill wrote: Testcases in g++.dg/vect rely on check_vect_support_and_set_flags to set dg-do-what-default and avoid running vector tests on non-vector targets. The three testcases in this patch overwrite the default with dg-do run. Removing the dg-do run directive r

Re: [PATCH V3] test: Fix FAIL of pr97428.c for RVV

On 11/7/23 08:18, Juzhe-Zhong wrote: gcc/testsuite/ChangeLog: * gcc.dg/vect/pr97428.c: Add additional compile option for riscv. I don't guess we know if other targets would benefit from this option. The only reference in gcc-testresults to pr97428.c is an armv7 run from 2022. So le

Re: [PATCH] g++: Add require-effective-target to multi-input file testcase pr95401.cc

On 11/3/23 00:18, Patrick O'Neill wrote: On non-vector targets dejagnu attempts dg-do compile for pr95401.cc. This produces a command like this: g++ pr95401.cc pr95401a.cc -S -o pr95401.s which isn't valid (gcc does not accept multiple input files when using -S with -o). This patch adds requ

Re: [PATCH 1/3] attribs: Cache the gnu namespace

On 11/6/23 05:23, Richard Sandiford wrote: Later patches add more calls to get_attribute_namespace. For scoped attributes, this is a simple operation on tree pointers. But for normal GNU attributes (the vast majority), it involves a call to get_identifier ("gnu"). This patch caches the identi

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

On 11/9/23 10:40, Alexander Monakov wrote: On Thu, 9 Nov 2023, Maxim Kuvyrkov wrote: Hi Kewen, Below are my comments. I don't want to override Alexander's review, and if the patch looks good to him, it's fine to ignore my concerns. My main concern is that this adds a new entity -- forcef

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

On 11/9/23 18:57, Kewen.Lin wrote: Hi Maxim and Alexander, Thanks a lot for the review comments! on 2023/11/10 01:40, Alexander Monakov wrote: On Thu, 9 Nov 2023, Maxim Kuvyrkov wrote: Hi Kewen, Below are my comments. I don't want to override Alexander's review, and if the patch looks

Re: [PATCH v3] libiberty: Use posix_spawn in pex-unix when available.

On 10/4/23 12:28, Brendan Shanks wrote: Hi, This patch implements pex_unix_exec_child using posix_spawn when available. This should especially benefit recent macOS (where vfork just calls fork), but should have equivalent or faster performance on all platforms. In addition, the implementatio

Re: [PATCH 2/3] attribs: Consider namespaces when comparing attributes

On 11/6/23 05:24, Richard Sandiford wrote: decl_attributes and comp_type_attributes both had code that iterated over one list of attributes and looked for coresponding attributes in another list. This patch makes those lookups namespace-aware. Tested on aarch64-linux-gnu & x86_64-linux-gnu.

Re: RFA: make scan-assembler* ignore LTO sections (Was: Re: committed [RISC-V]: Harden test scan patterns)

On 11/8/23 09:00, Joern Rennecke wrote: On Fri, 29 Sept 2023 at 14:54, Jeff Law wrote: ... Joern can you post a follow-up manual twiddle so that other ports can follow your example and avoid this problem? THanks, jeff The attached patch makes the scan-assembler* directives ignore the

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

On 11/10/23 03:39, Richard Sandiford wrote: Lehua Ding writes: On 2023/11/10 18:16, Richard Sandiford wrote: Lehua Ding writes: Hi Richard, On 2023/11/8 17:40, Richard Sandiford wrote: Tracking subreg liveness will sometimes expose dead code that wasn't obvious without it. PR89606 has

Re: [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

On 11/8/23 04:09, Mary Bennett wrote: Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Hel

Re: [PATCH 3/3] attribs: Namespace-aware lookup_attribute_spec

On 11/6/23 05:24, Richard Sandiford wrote: attribute_ignored_p already used a namespace-aware query to find the attribute_spec for an existing attribute: const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr)); This patch does the same for other callers in the file. Te

Re: [PATCH] attribs: Use existing traits for excl_hash_traits

On 11/6/23 05:32, Richard Sandiford wrote: Ping. Richard Sandiford via Gcc-patches writes: excl_hash_traits can be defined more simply by reusing existing traits. Tested on aarch64-linux-gnu. OK to install? Richard gcc/ * attribs.cc (excl_hash_traits): Delete. (test_att

Re: [PING 2] [C PATCH] Synthesize nonnull attribute for parameters declared with static

On 10/21/23 05:09, Martin Uecker wrote: C programmers increasingly use static to indicate that pointer parameters are non-null. Clang can exploit this for warnings and optimizations. GCC has some warnings but not all warnings it has for nonnull. Below is a patch to add a nonnull attribute

Re: [RFC 1/2] RISC-V: Add support for _Bfloat16.

On 10/25/23 04:15, Jin Ma wrote: +;; The conversion of DF to BF needs to be done with SF if there is a +;; chance to generate at least one instruction, otherwise just using +;; libfunc __truncdfbf2. +(define_expand "truncdfbf2" + [(set (match_operand:BF 0 "register_operand" "=f") +

Re: [PATCH v3 1/4] ifcvt: handle sequences that clobber flags in noce_convert_multiple_sets

On 10/19/23 13:41, Richard Sandiford wrote: Manolis Tsamis writes: This is an extension of what was done in PR106590. Currently if a sequence generated in noce_convert_multiple_sets clobbers the condition rtx (cc_cmp or rev_cc_cmp) then only seq1 is used afterwards (sequences that emit the

Re: [PATCH v3 1/4] ifcvt: handle sequences that clobber flags in noce_convert_multiple_sets

On 10/20/23 01:04, Robin Dapp wrote: But I'm not sure which cases this code is trying to catch. Is it trying to catch cases where seq2 "spontaneously" uses registers that happen to overlap with cond? If so, then when does that happen? And if it does happen, wouldn't the sequence also have

Re: [PATCH v3 1/4] ifcvt: handle sequences that clobber flags in noce_convert_multiple_sets

On 10/20/23 03:16, Richard Sandiford wrote: Thanks for the context. Robin Dapp writes: Sorry for the slow review. TBH I was hoping someone else would pick it up, since (a) I'm not very familiar with this code, and (b) I don't really agree with the way that the current code works. I'm not

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