Re: [17/n] PR85694: AArch64 support for AVG_FLOOR/CEIL

On Fri, Jun 29, 2018 at 04:24:58AM -0500, Richard Sandiford wrote: > This patch adds AArch64 patterns for the new AVG_FLOOR/CEIL operations. > AVG_FLOOR is [SU]HADD and AVG_CEIL is [SU]RHADD. > > Tested on aarch64-linux-gnu (with and without SVE). OK to install? OK. Thanks, James > 2018-06-29

Re: [PATCH][GCC][AArch64] Simplify movmem code by always doing overlapping copies when larger than 8 bytes.

On Tue, Jun 19, 2018 at 09:09:27AM -0500, Tamar Christina wrote: > Hi All, OK. Thanks, James > Thanks, > Tamar > > gcc/ > 2018-06-19 Tamar Christina > > * config/aarch64/aarch64.c (aarch64_expand_movmem): Fix mode size. > > gcc/testsuite/ > 2018-06-19 Tamar Christina > >

Re: [AArch64][PATCH 1/2] Fix addressing printing of LDP/STP

On Mon, Jun 25, 2018 at 03:48:13AM -0500, Andre Simoes Dias Vieira wrote: > On 18/06/18 09:08, Andre Simoes Dias Vieira wrote: > > Hi Richard, > > > > Sorry for the delay I have been on holidays. I had a look and I think you > > are right. With these changes Umq and Uml seem to have the same >

Re: [AArch64][PATCH 2/2] PR target/83009: Relax strict address checking for store pair lanes

On Mon, Jun 25, 2018 at 03:48:43AM -0500, Andre Simoes Dias Vieira wrote: > On 14/06/18 12:47, Richard Sandiford wrote: > > Kyrill Tkachov writes: > >> Hi Andre, > >> On 07/06/18 18:02, Andre Simoes Dias Vieira wrote: > >>> Hi, > >>> > >>> See below a patch to address PR 83009. > >>> > >>> Tested

Re: [PATCH, GCC, AARCH64] Add support for +profile extension

On Mon, Jul 09, 2018 at 08:20:53AM -0500, Andre Vieira (lists) wrote: > Hi, > > This patch adds support for the Statistical Profiling Extension (SPE) on > AArch64. Even though the compiler will not generate code any differently > given this extension, it will need to pass it on to the assembler in

Re: [PATCH][Aarch64] v2: Arithmetic overflow subv patterns [Patch 3/4]

On Wed, Jun 13, 2018 at 03:06:05AM -0500, Michael Collison wrote: > Updated previous patch: > > https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00508.html > > With coding style feedback from Richard Sandiford: (that also apply to this > patch) > > https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00

Re: [PATCH][Aarch64] v2: Arithmetic overflow addv patterns [Patch 2/4]

On Wed, Jun 13, 2018 at 02:57:45AM -0500, Michael Collison wrote: > Updated with Richard's style and mismatched mode comments. > > Okay for trunk? OK. Thanks, James

Re: [PATCH][GCC][AARCH64] Canonicalize aarch64 widening simd plus insns

On Thu, Jul 19, 2018 at 07:35:22AM -0500, Matthew Malcomson wrote: > Hi again. > > Providing an updated patch to include the formatting suggestions. Please try not to top-post replies, it makes the conversation thread harder to follow (reply continues below!). > On 12/07/18 11:39, Sudakshina Da

Re: [Patch] [Aarch64] PR 86538 - Define __ARM_FEATURE_LSE if LSE is available

On Tue, Jul 24, 2018 at 03:22:02PM -0500, Steve Ellcey wrote: > This is a patch for PR 86538, to define an __ARM_FEATURE_LSE macro > when LSE is available.  Richard Earnshaw closed PR 86538 as WONTFIX > because the ACLE (Arm C Language Extension) does not require this > macro and because he is conc

Re: [PATCH][GCC][AArch64] Set default values for stack-clash and do basic validation in back-end. [Patch (5/6)]

amar Christina > > PR target/86486 > * config/aarch64/aarch64.c (aarch64_override_options_internal): > Add validation for stack-clash parameters and set defaults. > > > -Original Message- > > From: Tamar Christina > > Sent:

Re: [PATCH][GCC][AArch64] Cleanup the AArch64 testsuite when stack-clash is on [Patch (6/6)]

4, we don't support this. > * testsuite/lib/target-supports.exp > (check_effective_target_frame_pointer_for_non_leaf): AArch64 does not > require frame pointer for non-leaf functions. > > > -Original Message- > > From: Tamar Christina > > Sent: Wednesday

Re: [PATCH][AARCH64] PR target/84521 Fix frame pointer corruption with -fomit-frame-pointer with __builtin_setjmp

On Thu, Jul 12, 2018 at 12:01:09PM -0500, Sudakshina Das wrote: > Hi Eric > > On 27/06/18 12:22, Wilco Dijkstra wrote: > > Eric Botcazou wrote: > > > >>> This test can easily be changed not to use optimize since it doesn't look > >>> like it needs it. We really need to tests these builtins proper

Re: [AArch64] Add support for 16-bit FMOV immediates

On Wed, Jul 18, 2018 at 12:47:27PM -0500, Richard Sandiford wrote: > aarch64_float_const_representable_p was still returning false for > HFmode, so we wouldn't use 16-bit FMOV immediate. E.g. before the > patch: > > __fp16 foo (void) { return 0x1.1p-3; } > > gave: > >mov w0, 123

Re: [PATCH][AArch64] Implement new intrinsics vabsd_s64 and vnegd_s64

On Fri, Jul 20, 2018 at 04:37:34AM -0500, Vlad Lazar wrote: > Hi, > > The patch adds implementations for the NEON intrinsics vabsd_s64 and > vnegd_s64. > (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ihi0073/latest/arm-neon-intrinsics-reference-architecture-spec

Re: [gen/AArch64] Generate helpers for substituting iterator values into pattern names

On Fri, Jul 13, 2018 at 04:15:41AM -0500, Richard Sandiford wrote: > Given a pattern like: > > (define_insn "aarch64_frecpe" ...) > > the SVE ACLE implementation wants to generate the pattern for a > particular (non-constant) mode. This patch automatically generates > helpers to do that, speci

Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode

On Thu, Jul 26, 2018 at 11:52:15AM -0500, Sam Tebbs wrote: > > Thanks for making the changes and adding more test cases. I do however > > see that you are only covering 2 out of 4 new > > *aarch64_get_lane_zero_extenddi<> patterns. The > > *aarch64_get_lane_zero_extendsi<> were already existing.

Re: [PATCH] [AArch64, Falkor] Switch to using Falkor-specific vector costs

On Wed, Jul 25, 2018 at 01:10:34PM -0500, Luis Machado wrote: > The adjusted vector costs give Falkor a reasonable boost in performance for FP > benchmarks (both CPU2017 and CPU2006) and doesn't change INT benchmarks that > much. About 0.7% for CPU2017 FP and 1.54% for CPU2006 FP. > > OK for trunk

Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost

On Wed, Jul 25, 2018 at 01:35:23PM -0500, Luis Machado wrote: > Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite > failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating > a sbfiz instruction rather than a load with sign extension. > > No performance cha

[AArch64] Fix categorisation of the frecp* insns.

where possible merge patterns. Tested on aarch64-none-elf with no regression. Thanks, James --- 2013-09-03 James Greenhalgh * config/aarch64/aarch64.md (type): Remove frecpe, frecps, frecpx. (aarch64_frecp): Move to aarch64-simd.md, fix to be a TAR

[Patch AArch64] Obvious - Fix return types for vaddvq_64

The vaddvq_s64 and vaddvq_u64 intrinsics are defined to return 32-bit types. This is clearly wrong, so fix them to return int64_t and uint64_t as expected. Regression tested with a run through aarch64.exp and sanity checked. OK for trunk? Thanks, James --- gcc/ 2013-09-04 James Greenhalgh

[Patch AArch64] Fix register constraints for lane intrinsics.

s, we have not been consistent. Fix that. Tested with aarch64.exp with no regressions. OK for trunk? Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/aarch64/aarch64-simd.md (aarch64_sqdmll_n_internal): Use iterator to ensure correct regis

[AArch64] Fix types of second parameter to qtbl/qtbx intrinsics

I have some similair patches kicking around in my tree, these feel obvious, but I'd like to check that others' share that perspective before I go committing anything! Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/aarch64/arm_neon.h (vqtbl<1,2,3,4

[ARM,AARCH64] Insn type reclassification. Split f_cvt type.

-none-eabi and sanity checked. Bootstrapped in series with other type splitting patches. OK? Thanks, James --- 2013-09-06 James Greenhalgh * config/arm/types.md (type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f. * config/aarch64/aarch64.md (l2): Update with

[Patch ARM AARCH64] Split "type" attributes: fdiv

James --- 2013-09-06 James Greenhalgh * config/arm/types.md: Split fdiv as fsqrt, fdiv. * config/arm/arm.md (core_cycles): Remove fdiv. * config/arm/vfp.md: (*sqrtsf2_vfp): Update for attribute changes. (*sqrtdf2_vfp): Likewise. * config/aa

[Patch AArch64] Fix types for some multiply instructions.

Hi, We don't really need to split the types on these instructions. The ARM backend already has suitable descriptions of things like mla and smlal. Use them. Regression tested on aarch64-none-elf with no regressions. OK? Thanks, James --- 2013-09-06 James Greenhalgh * c

[AArch64, ARM] Rename the FCPYS type to FMOV

-none-eabi with no regressions. OK? Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/arm/types.md (type): Rename fcpys to fmov. * config/arm/vfp.md (*arm_movsi_vfp): Rename type fcpys as fmov. (*thumb2_movsi_vfp): Likewise (*movhf_vfp_neon)

[AArch64] Use "multiple" for type, where more than one instruction is used for a move

with no regressions. OK? Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/aarch64/aarch64.md (*movti_aarch64): Use "multiple" for type where v8type is "move2". (*movtf_aarch64): Likewise. * config/arm/arm.md (thumb1_mo

[AArch64, ARM] Introduce "mrs" type attribute.

the same category as "multiple" in the pipelines. This will give the most consistant behaviour with what came before. Regression tested on aarch64-none-elf and arm-none-eabi with no regressions. OK? Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/arm/t

[AArch64] Use neon__2 where appropriate as "type".

neon_stm_2 describe them adequately. Tested on aarch64-none-elf with no regressions. OK? Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/aarch64/aarch64.md (*movtf_aarch64): Use neon_dm_2 as type where v8type is fpsimd_2. (load_pair): Likewise

[AArch64] Fix parameters to vcvtx_high

James Greenhalgh * config/aarch64/arm_neon.h (vcvtx_high_f32_f64): Fix parameters. diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 5864f2c..47b45f4 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -5756,12

[AArch64] obvious - Fix parameter to vrsqrte_f64

Hi, vrsqrte_f64 is currently defined to take a float64x2_t, but it should take a float64x1_t. I've committed the attached, obvious fix as revision 202407. James --- 2013-09-09 James Greenhalgh * config/aarch64/arm_neon.h (vrsqrte_f64): Fix parameter type. diff --git a/gcc/c

[AArch64] Prevent generic pipeline description from dominating other pipeline descriptions.

g". Regression tested on aarch64-none-elf with no regressions. OK? Thanks, James --- 2013-09-10 James Greenhalgh * config/aarch64/aarch64.md (generic_sched): New. * config/aarch64/aarch64-generic.md (load): Make conditional on generic_sched attribute.

Re: [1/4] Using gen_int_mode instead of GEN_INT

-linux-gnu with no issues and regression tested for aarch64-none-elf with the expected benefits and no regressions. Thanks, James --- gcc/ 2013-09-10 James Greenhalgh PR rtl-optimization/58383 * emit-rtl.c (gen_int_mode): Handle vector modes. diff --git a/gcc/emit-rtl.c b/gcc

Re: [1/4] Using gen_int_mode instead of GEN_INT

On Tue, Sep 10, 2013 at 08:09:42PM +0100, Richard Sandiford wrote: > Sorry for the breakage. gen_int_mode and GEN_INT really are only for > scalar integers though. (So is plus_constant.) Vector constants should > be CONST_VECTORs rather than CONST_INTs. > > I think the gcc.target/aarch64/vect-f

[AArch64] Implement vmul_lane_<16,32,64> intrinsics in C

ld not match. mul3_elt_to_64v2df is needed as, when the output is a 64-bit scalar there is no need for a vec_duplicate before the multiply. Regression tested on aarch64-none-elf with no regressions. Thanks, James Greenhalgh --- gcc/ 2013-09-13 James Greenhalgh * config/aarch64/aarch64-s

[AArch64] Implement vset_lane intrinsics in C

64-none-elf and a new testcase added to ensure these intrinsics generate the expected instruction. OK? Thanks, James --- gcc/ 2013-09-13 James Greenhalgh * config/aarch64/arm_neon.h (__aarch64_vset_lane_any): New. (__aarch64_vset_lane_<8,16,32,64>): Likewise.

[AArch64] Implement vcopy intrinsics.

;): Implement optimally. gcc/testsuite 2013-09-13 James Greenhalgh * gcc.target/aarch64/vect_copy_lane_1.c: New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f13cd5b7cdbdff95bbc378a76a6dd05de031487d..9703dd934a2f8335ffc5086e8a421db609fe0236

Re: [AArch64] Implement vset_lane intrinsics in C

On Fri, Sep 13, 2013 at 07:39:08PM +0100, Andrew Pinski wrote: > I don't think this works for big-endian due to the way ARM decided the > lanes don't match up with array entry there. Hi Andrew, Certainly for the testcase I've added in this patch there are no issues. Vector indexing should work c

Re: [AArch64] Fix parameters to vcvtx_high

*ping* Cheers, James On Fri, Sep 06, 2013 at 04:06:08PM +0100, James Greenhalgh wrote: > > Hi, > > vcvtx_high_f32_f64 should have two parameters, a float32x2 which > provides the lower half of the target vector, and a float64x2 > which will be converted to the higher half of

Re: [AArch64] Implement vset_lane intrinsics in C

On Fri, Sep 13, 2013 at 10:47:01PM +0100, Andrew Pinski wrote: > On Fri, Sep 13, 2013 at 11:57 AM, James Greenhalgh > wrote: > > Should return '1' whatever your endianness. Throwing together a quick > > test case, that is the case for current trunk. Do you have a

Re: [AArch64] Implement vset_lane intrinsics in C

On Mon, Sep 16, 2013 at 10:29:37AM +0100, James Greenhalgh wrote: > The little endian compiler would lay memory out as: > >0x0 ...0x8 > | 0b | 0a | 1b | 1a | 2b | 2a | 3b | 3a | > > And the big endian compiler would lay out memo

Re: [PATCH][AARCH64]Replace gen_rtx_PLUS with plus_constant

On Fri, Sep 20, 2013 at 03:40:59PM +0100, Renlin Li wrote: > Thank you, can you please commit it for me? > > Kind regards, > Renlin Li > > On 09/20/13 15:26, Marcus Shawcroft wrote: > > On 20 September 2013 15:18, Renlin Li wrote: > > > >> 2013-09-20 Renlin Li > >> > >> * config/aarch64/

Re: [PATCH][AARCH64]Replace gen_rtx_PLUS with plus_constant

On Sat, Sep 21, 2013 at 09:34:34AM +0100, James Greenhalgh wrote: > On Fri, Sep 20, 2013 at 03:40:59PM +0100, Renlin Li wrote: > > Thank you, can you please commit it for me? > > > > Kind regards, > > Renlin Li > > > > On 09/20/13 15:26, Marcus Shawcroft

Re: [PATCH] Refactor type handling in get_alias_set, fix PR58513

After asking Richard Earnshaw to explain -fPIC and dynamic linking to me, I've committed this (now obvious) patch as r202947. Thanks, James --- gcc/testsuite/ 2013-09-26 James Greenhalgh * g++.dg/vect/pr58513.cc (op): Make static.diff --git a/gcc/testsuite/g++.dg/vect/pr58513.cc

Re: [PATCH] Make jump thread path carry more information

On Fri, Sep 27, 2013 at 04:32:10PM +0100, Jeff Law wrote: > If you could pass along a .i file it'd be helpful in case I want to look > at something under the debugger. I've opened http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58553 to save everyone's inboxes. Let me know if I can do anything else

[ARM, AArch64] Make aarch64-common.c files more robust.

that, removing segmentation faults I see when tuning for Cortex-A15 and Cortex-A7. Tested on aarch64-none-elf and arm-none-eabi with no regressions. OK? Thanks, James --- gcc/ 2013-09-30 James Greenhalgh * config/arm/aarch-common.c (arm_early_load_addr_dep): Add sanity che

[PATCH] [AArch64] Refactor Advanced SIMD builtin initialisation.

Hi, This patch refactors the initialisation code for the Advanced SIMD builtins under the AArch64 target. The patch has been regression tested on aarch64-none-elf. OK for aarch64-branch? (If yes, someone will have to commit this for me as I do not have commit rights) Thanks, James Greenhalgh

[PATCH] [AArch64] Add vcond, vcondu support.

Hi, This patch adds support for vcond and vcondu to the AArch64 backend. Tested with no regressions on aarch64-none-elf. OK for aarch64-branch? (If so, someone will have to commit for me, as I do not have commit rights.) Thanks James Greenhalgh --- 2012-09-11 James Greenhalgh

RE: [PATCH] [AArch64] Add vcond, vcondu support.

o, someone will have to commit for me, as I do not > > have commit rights.) > > > > Thanks > > James Greenhalgh > > > > --- > > 2012-09-11 James Greenhalgh > > Tejas Belagod > > > > * config/aarch64/aarch64-simd.md > > (aarch64_s

RE: [PATCH] [AArch64] Refactor Advanced SIMD builtin initialisation.

ion. > > On 05/10/12 16:52, James Greenhalgh wrote: > > > > Hi, > > > > This patch refactors the initialisation code for the Advanced > > SIMD builtins under the AArch64 target. The patch has been > > regression tested on aarch64-none-elf. > > > &g

[Patch] Add myself to MAINTAINERS as Write After Approval

Hi, This patch adds me to the Write After Approval section of MAINTAINERS. Regards, James Greenhalgh -- 2012-10-26 James Greenhalgh * MAINTAINERS (Write After Approval): Add myself. wap.patch Description: wap.patch

RE: [PATCH] [AArch64] Add vcond, vcondu support.

o, someone will have to commit for me, as I do not > > have commit rights.) > > > > Thanks > > James Greenhalgh > > > > --- > > 2012-09-11 James Greenhalgh > > Tejas Belagod > > > > * config/aarch64/aarch64-simd.md > > (aarch64_s

[AArch64] Fix early-clobber operands to vtbx[1,3]

aarch64.exp with no problems. OK? Thanks, James --- 2013-10-11 James Greenhalgh * config/aarch64/arm_neon.h (vtbx<1,3>_8): Fix register constriants. diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 482d7d0..f7c9db6 100644 --- a/gcc/

Re: [AArch64] Fix early-clobber operands to vtbx[1,3]

On Fri, Oct 11, 2013 at 07:52:48PM +0100, Marcus Shawcroft wrote: > > 2013-10-11 James Greenhalgh > > > > * config/aarch64/arm_neon.h > > (vtbx<1,3>_8): Fix register constriants. > > > > OK? > > OK, and back port to 4.8 please. > /Mar

[ARM/AARCH64] Remodel type attribute values for Neon Instructions.

line models. Thanks, James --- James Greenhalgh (10): [ARM] [1/10] Add new types to describe Neon insns. [AArch64] [Neon types 2/10] Update Current type attributes to new Neon Types. [ARM] [Neon types 3/10] Update Current type attributes to new Neon Types. [AArch64] [Neon types 4/10]

[ARM] [1/10] Add new types to describe Neon insns.

one_lane_q neon_mcr neon_from_gp, f_mcr neon_mcr_2_mcrr neon_from_gp_q, f_mcrr neon_mrc neon_to_gp, f_mrc neon_mrrc neon_to_gp_q, f_mrrc Bootstrapped in series, and sanity checked. Thanks, James --- gcc 2013-10-15 James Greenhalgh * config/arm/types.md: Add new types for

[AArch64] [Neon types 2/10] Update Current type attributes to new Neon Types.

/ 2013-10-15 James Greenhalgh * config/aarch64/aarch64.md (movtf_aarch64): Update type attribute. (load_pair): Update type attribute. (store_pair): Update type attribute. * config/aarch64/iterators.md (q): New. diff --git a/gcc/config/aarch64/aarch64.md b/gcc

[ARM] [Neon types 9/10] Remove old neon types

Hi, Now that we have proted the pipeline models, this patch removes the old neon types. Bootstrapped on a chromebook in series and sanity checked. Thanks, James --- gcc/ 2013-10-15 James Greenhalgh * config/arm/types: Remove old neon types. diff --git a/gcc/config/arm/types.md b

[ARM] [Neon types 10/10] Remove neon-schedgen.ml

Hi, After refactoring all the Neon "type" attributes, neon-schedgen.ml is out of date and only serves to distract. This patch removes the script. I've run a bootstrap for arm just to ensure that no funky Make machinery remains. OK? Thanks, James --- 2013-10-15 J

[ARM] [Neon types 8/10] Cortex-A7 neon pipeline model

Hi, This patch updates the A7 pipeline for the new Neon types. Sanity checked and tested with some neon intrinsics code to see schedule quality. Thanks, James --- gcc/ 2013-10-15 James Greenhalgh * config/arm/cortex-a7.md (cortex_a7_neon_type): New

[AArch64] Fix output template for Scalar Neon->Neon register move.

this. aarch64.exp came back clean and the correct instruction form is now generated. OK? Thanks, James --- 2013-10-14 James Greenhalgh * config/aarch64/aarch64.md (*mov_aarch64): Fix output template for DUP (element) Scalar. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/c

[AArch64] Fix types for vcvt_n intrinsics.

Hi, I spotted that the types of arguments to these intrinsics are wrong, which results in all sorts of fun issues! Fixed thusly, regression tested with aarch64.exp on aarch64-none-elf with no issues. OK? Thanks, James --- 2013-10-17 James Greenhalgh * config/aarch64/arm_neon.h

Re: [Patch tree-ssa] RFC: Enable path threading for control variables (PR tree-optimization/54742).

On Fri, Oct 18, 2013 at 11:55:08AM +0100, Richard Biener wrote: > I suppose with Jeffs recent work on jump-threading through paths > this case in handled and the patch in this thread is obsolete or can > be reworked? Yes, this patch is now obsolete, Jeff's solution is much more elegant :-) Thanks

[AArch64] Fix size of memory store for the vst_lane intrinsics

--- gcc/ 2013-10-29 James Greenhalgh * config/aarch64/arm_neon.h (__ST2_LANE_FUNC): Better model data size. (__ST3_LANE_FUNC): Likewise. (__ST4_LANE_FUNC): Likewise. diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 787ff15..7a63ea1

Re: [PATCH] Introducing SAD (Sum of Absolute Differences) operation to GCC vectorizer.

On Fri, Nov 01, 2013 at 02:03:52AM +, Cong Hou wrote: > 3. Add the document for SAD_EXPR. I think this patch should also document the new Standard Names usad and ssad in doc/md.texi? Your Changelog is missing the change to doc/generic.texi. Thanks, James

Re: [PATCH] Introducing SAD (Sum of Absolute Differences) operation to GCC vectorizer.

On Fri, Nov 01, 2013 at 04:48:53PM +, Cong Hou wrote: > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 2a5a2e1..8f5d39a 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -4705,6 +4705,16 @@ wider mode, is computed and added to operand 3. > Operand 3 is of a mode equal or > wi

Re: [PATCH] Try to avoid vector mode punning in SET_DEST on i?86

On Thu, Oct 31, 2013 at 04:49:47PM +, Jakub Jelinek wrote: > 2013-10-31 Jakub Jelinek > > * optabs.c (expand_vec_perm): Avoid vector mode punning > SUBREGs in SET_DEST. > * expmed.c (store_bit_field_1): Likewise. > * config/i386/sse.md (movdi_to_sse, vec_pac

Re: [PATCH] Introducing SAD (Sum of Absolute Differences) operation to GCC vectorizer.

On Mon, Nov 04, 2013 at 06:30:55PM +, Cong Hou wrote: > On Mon, Nov 4, 2013 at 2:06 AM, James Greenhalgh > wrote: > > On Fri, Nov 01, 2013 at 04:48:53PM +, Cong Hou wrote: > >> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > >> index 2a5a2e1..8f5d39a 100

[Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

it, and run a set of benchmarks to show no regressions on Cortex-A57 or Cortex-A53. The patch fixes some regressions caused by the more agressive vectorization in GCC6, so I'd like to propose it to go in even though we are in Stage 4. OK? Thanks, James --- gcc/ 2016-01-20 James Greenh

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote: > Hi, Wilco. > > On 01/06/2016 06:04 AM, Wilco Dijkstra wrote: > >>Here's what I had in mind when I inquired about distinguishing FCMP from > >>FCCMP. As you can see in the patch, Exynos is the only target that > >>cares about it, b

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Thu, Jan 21, 2016 at 11:13:29AM +, Wilco Dijkstra wrote: > James Greenhalgh wrote: > > If we don't have any targets which care about the fccmps/fccmpd split in > > the code base, do we really need it? Can we just follow the example of > > fcsel? > > I

Re: [AARCH64][ACLE][NEON] Implement vcvt*_s64_f64 and vcvt*_u64_f64 NEON intrinsics.

On Wed, Jan 13, 2016 at 05:44:30PM +, Bilyan Borisov wrote: > This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector > intrinsics, where R is ['',a,m,n,p]. Since these intrinsics are > identical in semantics to the corresponding scalar variants, they are > implemented in terms of

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

On Thu, Jan 21, 2016 at 01:58:31PM -0600, Evandro Menezes wrote: > Hi, James. > > On 01/21/16 03:24, James Greenhalgh wrote: > >On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote: > >>On 01/06/2016 06:04 AM, Wilco Dijkstra wrote: > >>>>Here

[Patch Obvious] gcc.dg/vect/bb-slp-pr68892.c requires vectorization of doubles

Hi, As title. This testcase fails on arm-none-linux-gnueabihf, because we don't have vectorization of doubles there. Committed as obvious as revision 232731. Thanks, James --- 2016-01-22 James Greenhalgh * gcc.dg/vect/bb-slp-pr68892.c: Require vect_double. diff --git

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Jan 11, 2016 at 12:04:43PM +, James Greenhalgh wrote: > > Hi, > > I've seen a couple of large performance issues caused by expanding > the high-precision reciprocal square root for Cortex-A57, so I'd like > to turn it off by default. > > This is goo

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Jan 11, 2016 at 11:53:39AM +, James Greenhalgh wrote: > > Hi, > > I'd like to switch the logic around in aarch64.c such that > -mlow-precision-recip-sqrt causes us to always emit the low-precision > software expansion for reciprocal square root. I have two reas

Re: [AARCH64][ACLE][NEON] Implement vcvt*_s64_f64 and vcvt*_u64_f64 NEON intrinsics.

On Thu, Jan 21, 2016 at 12:32:07PM +, James Greenhalgh wrote: > On Wed, Jan 13, 2016 at 05:44:30PM +, Bilyan Borisov wrote: > > This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector > > intrinsics, where R is ['',a,m,n,p]. Since these intrin

Re: [PATCH, AArch64] Fix for PR67896 (C++ FE cannot distinguish __Poly{8,16,64,128}_t types)

On Wed, Jan 20, 2016 at 09:27:41PM +0100, Roger Ferrer Ibáñez wrote: > Hi James, > > > This patch looks technically correct to me, though there is a small > > style issue to correct (in-line below), and your ChangeLogs don't fit > > our usual style. > > thank you very much for the useful comments

Re: [PATCH][AArch64] Add vector permute cost

On Tue, Dec 15, 2015 at 11:35:45AM +, Wilco Dijkstra wrote: > > Add support for vector permute cost since various permutes can expand into a > complex > sequence of instructions. This fixes major performance regressions due to > recent changes > in the SLP vectorizer (which now vectorizes m

[Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

-- `sqrdmlsh v2.4h,v4.4h,v23.h[5]' This patch teaches GCC to avoid registers outside of this range when appropriate, in the same fashion as we do for other instructions with this limitation. Tested on an internal testsuite targeting Neon intrinsics. OK? Thanks, James --- 2016-01-25 James Green

Re: [PATCH, aarch64] Fix pr69305 -- addti miscompilation

On Sun, Jan 24, 2016 at 03:19:35AM -0800, Richard Henderson wrote: > As Jakub notes in the PR, the representation for add_compare and > sub_compare were wrong. And several of the add_carryin patterns > were duplicates. > > This adds a CC_Cmode for which only the Carry bit is valid. > > The patch

Re: [PATCH 4/4][AArch64] Cost CCMP instruction sequences to choose better expand order

On Mon, Jan 25, 2016 at 08:09:39PM +, Wilco Dijkstra wrote: > Andreas Schwab wrote: > > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler-times \tcmp\tw[0-9]+, 0 4 > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler adds\t > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler-times fccmpe\t.

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Jan 25, 2016 at 11:21:25AM +, James Greenhalgh wrote: > On Mon, Jan 11, 2016 at 11:53:39AM +0000, James Greenhalgh wrote: > > > > Hi, > > > > I'd like to switch the logic around in aarch64.c such that > > -mlow-precision-recip-sqrt caus

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Jan 25, 2016 at 11:20:46AM +, James Greenhalgh wrote: > On Mon, Jan 11, 2016 at 12:04:43PM +0000, James Greenhalgh wrote: > > > > Hi, > > > > I've seen a couple of large performance issues caused by expanding > > the high-precision reciprocal s

Re: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS

ove is applied. Thanks, James > James Greenhalgh wrote: > > On Wed, Dec 16, 2015 at 01:05:21PM +, Wilco Dijkstra wrote: > > > James Greenhalgh wrote: > > > > On Tue, Dec 15, 2015 at 10:54:49AM +, Wilco Dijkstra wrote: > > > > > ping > > >

Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

On Wed, Jan 20, 2016 at 03:22:11PM +, James Greenhalgh wrote: > > Hi, > > In a number of cases where we try to create vectors we end up spilling to the > stack and then filling. This is one example distilled from a couple of > micro-benchmrks where the issue shows up.

Re: [aarch64] Improve TImode constant moves

On Sun, Jan 24, 2016 at 02:54:32AM -0800, Richard Henderson wrote: > This looks to be an incomplete transition of the aarch64 backend to > CONST_WIDE_INT. I haven't checked to see if it's a regression from > gcc5, but I suspect not, since there should have been similar checks > for CONST_DOUBLE. >

Re: [PATCH 4/4][AArch64] Cost CCMP instruction sequences to choose better expand order

On Thu, Jan 28, 2016 at 02:33:20PM +, James Greenhalgh wrote: > On Mon, Jan 25, 2016 at 08:09:39PM +, Wilco Dijkstra wrote: > > Andreas Schwab wrote: > > > > > FAIL: gcc.target/aarch64/ccmp_1.c scan-assembler-times \tcmp\tw[0-9]+, 0 4 > > > FAIL:

Re: [PATCH AArch64]Force register scaling out of mem ref and comment why

On Thu, Feb 04, 2016 at 10:11:53AM +, Bin Cheng wrote: > Hi, > There is a performance regression caused by my previous change to > aarch64_legitimize_address, in which I forced constant offset out of memory > ref if the address expr is in the form of "reg1 + reg2 << scale + const". > The intent

Re: [PATCH][AArch64] PR target/69161: Don't use special predicate for CCmode comparisons in expressions that require matching modes

On Fri, Jan 29, 2016 at 02:27:34PM +, Kyrill Tkachov wrote: > Hi all, > > In this PR we ICE during combine when trying to propagate a comparison into a > vec_duplicate, > that is we end up creating the rtx: > (vec_duplicate:V4SI (eq:CC_NZ (reg:CC_NZ 66 cc) > (const_int 0 [0]))) > > T

Re: [PATCH] Fix jit crash on aarch64, mips

On Thu, Feb 04, 2016 at 10:31:27AM -0500, David Malcolm wrote: > The jit testsuite was showing numerous segfaults and fatal > errors for trunk on aarch64; typically on the 2nd iteration of each > test, with errors like: > test-volatile.c.exe: fatal error: pass ‘rnreg’ not found but is referenced

Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

On Tue, Feb 02, 2016 at 10:29:29AM +, James Greenhalgh wrote: > On Wed, Jan 20, 2016 at 03:22:11PM +0000, James Greenhalgh wrote: > > > > Hi, > > > > In a number of cases where we try to create vectors we end up spilling to > > the > > stack and then

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On Mon, Feb 01, 2016 at 02:00:01PM +, James Greenhalgh wrote: > On Mon, Jan 25, 2016 at 11:20:46AM +0000, James Greenhalgh wrote: > > On Mon, Jan 11, 2016 at 12:04:43PM +0000, James Greenhalgh wrote: > > > > > > Hi, > > > > > > I've s

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On Mon, Feb 01, 2016 at 01:59:34PM +, James Greenhalgh wrote: > On Mon, Jan 25, 2016 at 11:21:25AM +0000, James Greenhalgh wrote: > > On Mon, Jan 11, 2016 at 11:53:39AM +0000, James Greenhalgh wrote: > > > > > > Hi, > > > > > > I'd like

Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

On Tue, Jan 26, 2016 at 04:04:47PM +, James Greenhalgh wrote: > > Hi, > > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction > available when compiling with -march=armv8.1-a are only usable with > a register number in the range 0 to 15 for operand 3,

[Patch] Gate vect-mask-store-move-1.c correctly, and actually output the dump

/native) and x86 with no issues. OK? Thanks, James --- 2016-02-08 James Greenhalgh * gcc.dg/vect/vect-mask-store-move-1.c: Add dump option, and gate check on x86_64/i?86. diff --git a/gcc/testsuite/gcc.dg/vect/vect-mask-store-move-1.c b/gcc/testsuite/gcc.dg/vect/vect-mask-store

Re: [Patch] Gate vect-mask-store-move-1.c correctly, and actually output the dump

ut: https://gcc.gnu.org/ml/gcc-testresults/2016-02/msg00824.html Thanks, James > > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/vect-mask-store-move-1.c: Gate dump with x86 target. > > 2016-02-08 16:07 GMT+03:00 James Greenhalgh : > > > > Hi, > > > > As far as I

Re: [Patch] Gate vect-mask-store-move-1.c correctly, and actually output the dump

On Mon, Feb 08, 2016 at 03:24:14PM +0100, Richard Biener wrote: > On Mon, Feb 8, 2016 at 2:40 PM, James Greenhalgh > wrote: > > On Mon, Feb 08, 2016 at 04:29:31PM +0300, Yuri Rumyantsev wrote: > >> Hi James, > >> > >> Thanks for reporting this issue. &

Re: [PATCH][AArch64] Only update assembler .arch directive when necessary

On Thu, Feb 04, 2016 at 01:50:31PM +, Kyrill Tkachov wrote: > Hi all, > > As part of the target attributes and pragmas support for GCC 6 I changed the > aarch64 port to emit a .arch assembly directive for each function that > describes the architectural features used by that function. This is

Re: [PATCH][AArch64] Only update assembler .arch directive when necessary

On Wed, Feb 10, 2016 at 10:32:16AM +, Kyrill Tkachov wrote: > Hi James, > > On 10/02/16 10:11, James Greenhalgh wrote: > >On Thu, Feb 04, 2016 at 01:50:31PM +, Kyrill Tkachov wrote: > >>Hi all, > >> > >>As part of the target attributes a

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