On Mon, Jan 4, 2021 at 4:59 PM Hongtao Liu wrote:
>
> On Mon, Jan 4, 2021 at 4:49 PM Jakub Jelinek wrote:
> >
> > On Mon, Jan 04, 2021 at 01:56:44PM +0800, Hongtao Liu via Gcc-patches wrote:
> > > +(define_insn_and_split "*sse2_pmovskb_zexthisi&quo
On Tue, Jan 5, 2021 at 3:20 PM Uros Bizjak wrote:
>
> On Tue, Jan 5, 2021 at 8:04 AM Uros Bizjak wrote:
> > >
> > > +(define_split
> > > + [(set (match_operand:SI 0 "register_operand")
> > > +(zero_extend:SI
> > > + (not:HI
> > > +(subreg:HI
> > > + (uns
> >>
> >> Note there's a data dependency between them. insn 7 feeds insn 9. When
> >> there's a data dependency, combiner patterns are usually the better
> >> choice than peepholes. I think you'd be looking to match something
> >> likethis (from the . combine dump):
> >>
Using combiner patterns
Hi:
ix86_expand_fp_vec_cmp/ix86_expand_int_vec_cmp are used by vec_cmpmn
for vector comparison to vector mask, but ix86_expand_sse_cmp(which is
called in upper 2 functions.) may return integer mask whenever integer
mask is available, so convert integer mask back to vector mask if
needed.
gcc/Cha
On Wed, Jan 6, 2021 at 10:39 PM Jakub Jelinek wrote:
>
> On Wed, Jan 06, 2021 at 02:49:13PM +0800, Hongtao Liu wrote:
> > ix86_expand_fp_vec_cmp/ix86_expand_int_vec_cmp are used by vec_cmpmn
> > for vector comparison to vector mask, but ix86_expand_sse_cmp(which is
>
On Tue, Dec 29, 2020 at 3:01 PM sunil.k.pandey via Gcc-regression
wrote:
>
> On Linux/x86_64,
>
> 12ae2bc70846a2be8255eaa41322cd1a5a7b7350 is the first bad commit
> commit 12ae2bc70846a2be8255eaa41322cd1a5a7b7350
> Author: Hongyu Wang
> Date: Fri Dec 25 09:25:39 2020 +0800
>
> Fix standard
On Thu, Jan 7, 2021 at 9:43 PM Uros Bizjak via Gcc-patches
wrote:
>
> 2021-01-07 Uroš Bizjak
>
> No functional changes.
>
> gcc/
> * config/i386/i386.md (insn): Merge from plusminus_insn, shift_insn,
> rotate_insn and optab code attributes.
> Update all uses to merged code attribute
Hi:
d->flag is always 0 for builtins located in
BDESC_FIRST (comi,COMI,...)
...
BDESC_END (COMI, PCMPESTR)
So the condition can be deleted, so did BUILTIN_DESC_SWAP_OPERANDS.
Regtested and bootstrapped on x86_64-linux-gnu{-m32,}.
gcc/ChangeLog:
PR target/98612
* config/i386/
ping.
On Thu, Jan 7, 2021 at 1:22 PM Hongtao Liu wrote:
>
> On Wed, Jan 6, 2021 at 10:39 PM Jakub Jelinek wrote:
> >
> > On Wed, Jan 06, 2021 at 02:49:13PM +0800, Hongtao Liu wrote:
> > > ix86_expand_fp_vec_cmp/ix86_expand_int_vec_cmp are used by vec_cmpmn
>
Hi:
If SRC had been assigned a mode narrower than the copy, we can't link
DEST into the chain even they have same
hard_regno_nregs(i.e. HImode/SImode in i386 backend).
i.e
kmovw %k0, %edi
vmovd %edi, %xmm2
vpshuflw$0, %xmm2, %xmm0
kmovw %k0, %r8d
On Mon, Jan 18, 2021 at 6:18 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > If SRC had been assigned a mode narrower than the copy, we can't link
> > DEST into the chain even they have same
> > hard_regno_nregs(i.e. HIm
On Mon, Jan 18, 2021 at 6:43 PM Hongtao Liu wrote:
>
> On Mon, Jan 18, 2021 at 6:18 PM Richard Sandiford
> wrote:
> >
> > Hongtao Liu via Gcc-patches writes:
> > > Hi:
> > > If SRC had been assigned a mode narrower than the copy, we can't link
&
On Mon, Jan 18, 2021 at 7:10 PM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Mon, Jan 18, 2021 at 6:18 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > Hi:
> >> > If SRC had been assig
On Wed, Jan 20, 2021 at 12:10 AM Richard Sandiford
wrote:
>
> Jakub Jelinek via Gcc-patches writes:
> > On Tue, Jan 19, 2021 at 12:38:47PM +, Richard Sandiford via Gcc-patches
> > wrote:
> >> > actually only the lower 16bits are needed, the original insn is like
> >> >
> >> > .294.r.ira
> >>
On Wed, Jan 20, 2021 at 12:35 PM Hongtao Liu wrote:
>
> On Wed, Jan 20, 2021 at 12:10 AM Richard Sandiford
> wrote:
> >
> > Jakub Jelinek via Gcc-patches writes:
> > > On Tue, Jan 19, 2021 at 12:38:47PM +, Richard Sandiford via
> > > Gcc-patches
> OK with those changes and the one that HJ asked for.
>
This is the patch I'm checking in, thanks for the review.
> Thanks,
> Richard
--
BR,
Hongtao
From b806e0cece62620e31a4a861208d37616059a212 Mon Sep 17 00:00:00 2001
From: liuhongt
Date: Mon, 18 Jan 2021 16:55:32 +0800
Subject: [PATCH] [
Thanks for the review.
On Fri, Jun 12, 2020 at 11:28 AM Jeff Law wrote:
>
> On Fri, 2020-06-05 at 13:46 +0800, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> >
> > +/* Optimize vector MUL generation for V8QI, V16QI and V32QI
> > + under TARGET_AVX512BW
Hi:
Basically i "copy" this optimization from clang i386 backend, Refer
to pr95524 for details.
Bootstrap is ok, regression test on i386/x86-64 backend is ok.
gcc/ChangeLog:
PR target/95524
* gcc/config/i386/i386-expand.c
(ix86_expand_vec_shift_qihi_constant): New funct
On Mon, Jun 15, 2020 at 9:48 PM Jakub Jelinek wrote:
>
> On Mon, Jun 15, 2020 at 09:29:29PM +0800, Hongtao Liu via Gcc-patches wrote:
> > Basically i "copy" this optimization from clang i386 backend, Refer
> > to pr95524 for details.
> > Bootstrap is ok, regr
Sorry,i mistakenly deleted local mail for
https://gcc.gnu.org/pipermail/gcc-patches/2020-June/548174.html, so i
send an another email.
> What I mean is that op2 is a CONST_INT, which in theory can have any
> HOST_WIDE_INT values.
> By assigning that to unsigned int variable, you are effectively
>
On Tue, Nov 24, 2020 at 4:27 AM Jeff Law wrote:
>
>
>
> On 11/4/20 2:19 AM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > When programmers explicitly use mask loaded intrinsics, don't
> > transform the instruction to vpblend{b,w,d,q} since If mem_addr poin
Hi:
I'm learning about this patch, and I see one place that might be
slighted improved.
+ poly_int64 size = (top - bot);
+
+ /* Assert the edge of each variable is aligned to the HWASAN tag granule
+size. */
+ gcc_assert (multiple_p (top, HWASAN_TAG_GRANULE_SIZE));
+
On Mon, Nov 23, 2020 at 11:54 PM Richard Biener wrote:
>
> On Mon, 23 Nov 2020, Tamar Christina wrote:
>
> > Hi All,
> >
> > This patch adds support for
> >
> > * Complex Addition with rotation of 90 and 270.
> >
> > Addition with rotation of the second argument around the Argand plane.
> >
On Tue, Nov 24, 2020 at 9:00 PM Jakub Jelinek wrote:
>
> On Tue, Nov 24, 2020 at 10:36:49AM +0800, Hongtao Liu via Gcc-patches wrote:
> > > > * gcc.target/i386/pr97642-2.c: New test.
> > > So in the BZ Jakub asked for the all-ones mask case to be specially
>
Thanks for the review.
BTW, the patch is already installed because uros helped to review this
patch in another thread
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/558682.html
On Thu, Nov 26, 2020 at 3:15 AM Jeff Law wrote:
>
>
>
> On 11/11/20 1:03 AM, Hongtao Liu via Gcc-p
On Wed, Nov 25, 2020 at 7:37 PM Jakub Jelinek wrote:
>
> On Wed, Nov 25, 2020 at 07:32:44PM +0800, Hongtao Liu wrote:
> > Update patch:
> > 1. ix86_expand_special_args_builtin is used for expanding mask load
> > intrinsics, this function will always convert the constan
Hi:
This patch is about to delete dead code in ix86_expand_special_args_builtin.
Bootstrap and regression test are ok.
gcc/ChangeLog:
* config/i386/i386-expand.c
(ix86_expand_special_args_builtin): Delete last_arg_constant.
From 948756dae8f67bf766714d9ecc064b4eea9952cd Mon Sep
On Thu, Nov 26, 2020 at 4:11 PM Uros Bizjak wrote:
>
> > Hi:
> > This patch is about to delete dead code in
> > ix86_expand_special_args_builtin.
> >
> > Bootstrap and regression test are ok.
> >
> > gcc/ChangeLog:
> > * config/i386/i386-expand.c
> > (ix86_expand_special_args_b
Add no strict aliasing to function CALC, since there are
"long long tmp = (*(long long *) &src1[i]) ^ (*(long long *) &src2[i]);"
in function CALC.
modified gcc/testsuite/gcc.target/i386/avx512dq-vandnpd-2.c
@@ -9,6 +9,7 @@
#include "avx512f-mask-type.h"
void
+__attribute__ ((optimize ("no
Hi:
This patch is quite similar like what jakub did in
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/560151.html
but for target avx512bw.
.i.e. for -mavx512bw -mavx512vl transform code from
vpsubusw%xmm1, %xmm0, %xmm0
vpxor %xmm1, %xmm1, %xmm1
vpcmpw
On Mon, Nov 30, 2020 at 9:46 PM Jakub Jelinek wrote:
>
> On Mon, Nov 30, 2020 at 09:11:10PM +0800, Hongtao Liu wrote:
> > +;; PR96906 - optimize vpsubusw compared to 0 into vpcmpleuw or vpcmpnltuw.
> > +(define_split
> > + [(set (match_operand: 0 "register_o
Hi:
There're many pairs of define_insn/define_expand that are very similar
to each other except mode iterator and condition. For these patterns
VI12_AVX512VL are used under condition TARGET_AVX512BW, and
VI48_AVX512VL are used under condition TARGET_AVX512F.
This patch is about to introduce a new
On Wed, Dec 2, 2020 at 8:28 AM Jeff Law wrote:
>
>
>
> On 11/30/20 10:17 PM, Hongtao Liu via Gcc-patches wrote:
> > Hi:
> > There're many pairs of define_insn/define_expand that are very similar
> > to each other except mode iterator and condition. For these
On Thu, Dec 3, 2020 at 3:11 AM Jeff Law wrote:
>
>
>
> On 11/25/20 9:47 PM, Hongtao Liu wrote:
> > On Wed, Nov 25, 2020 at 7:37 PM Jakub Jelinek wrote:
> >> On Wed, Nov 25, 2020 at 07:32:44PM +0800, Hongtao Liu wrote:
> >>> Update patch:
> >>>
On Thu, Dec 3, 2020 at 2:22 AM Jakub Jelinek wrote:
>
> On Tue, Dec 01, 2020 at 12:49:03PM +0800, Hongtao Liu via Gcc-patches wrote:
> > +bool neq_p = INTVAL (operands[4]) >> 2;
> > +/* LE: 2, NLT: 5, NLE: 6, LT: 1 */
> > +rtx cmp_predicate = ne
On Tue, Dec 8, 2020 at 6:23 PM Jakub Jelinek wrote:
>
> On Mon, Nov 30, 2020 at 06:16:06PM +0800, Hongtao Liu via Gcc-patches wrote:
> > Add no strict aliasing to function CALC, since there are
> >
> > "long long tmp = (*(long long *) &src1[i]) ^ (*(long long *)
On Wed, Dec 9, 2020 at 5:22 PM Prathamesh Kulkarni via Gcc-patches
wrote:
>
> On Wed, 9 Dec 2020 at 00:29, sunil.k.pandey wrote:
> >
> > On Linux/x86_64,
> >
> > 3a6e3ad38a17a03ee0139b49a0946e7b9ded1eb1 is the first bad commit
> > commit 3a6e3ad38a17a03ee0139b49a0946e7b9ded1eb1
> > Author: Pratha
>
> > On Mon, 7 Dec 2020 at 17:37, Hongtao Liu wrote:
> > >
> > > On Mon, Dec 7, 2020 at 7:11 PM Prathamesh Kulkarni
> > > wrote:
> > > >
> > > > On Mon, 7 Dec 2020 at 16:15, Hongtao Liu wrote:
> > > > >
> > > &g
Hi:
For rtx like
(vec_select:V2SI (subreg:V4SI (inner:V2SI) 0)
(parallel [(const_int 0) (const_int 1)]))
it could be simplified as inner.
Bootstrap is ok, regression test on i386 backend is ok.
gcc/ChangeLog
PR rtl-optimization/97249
* simplify-rtx.c (sim
On Wed, Oct 14, 2020 at 4:01 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Tue, Oct 13, 2020 at 04:40:53PM +0800, Hongtao Liu wrote:
> > For rtx like
> > (vec_select:V2SI (subreg:V4SI (inner:V2SI) 0)
> >(parallel [(const_int 0) (const_int 1)]))
On Wed, Oct 14, 2020 at 5:21 PM Uros Bizjak wrote:
>
> On Wed, Oct 14, 2020 at 11:04 AM Hongyu Wang wrote:
> >
> >
> >
> > Uros Bizjak 于2020年10月14日周三 下午4:42写道：
> >>
> >> On Wed, Oct 14, 2020 at 10:34 AM Hongyu Wang
> >> wrote:
> >> >
> >> > >
> >> > > Please also add -muintr to g++.dg/other/i3
On Thu, Oct 15, 2020 at 1:37 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Wed, Oct 14, 2020 at 01:43:45PM +0800, Hongtao Liu wrote:
> > On Wed, Oct 14, 2020 at 4:01 AM Segher Boessenkool
> > wrote:
> > > On Tue, Oct 13, 2020 at 04:40:53PM +0800, Hongtao
On Thu, Oct 15, 2020 at 4:14 PM Hongtao Liu wrote:
>
> On Thu, Oct 15, 2020 at 1:37 AM Segher Boessenkool
> wrote:
> >
> > Hi!
> >
> > On Wed, Oct 14, 2020 at 01:43:45PM +0800, Hongtao Liu wrote:
> > > On Wed, Oct 14, 2020 at 4:01 AM Segher Boessenkool
On Thu, Oct 15, 2020 at 8:38 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > + /* Simplify vec_select of a subreg of X to just a vec_select of X
> > + when X has same component mode as vec_select. */
> > + int l2;
> >
Hi:
It's implemented as below:
V setg (V v, int idx, T val)
{
V idxv = (V){idx, idx, idx, idx, idx, idx, idx, idx};
V valv = (V){val, val, val, val, val, val, val, val};
V mask = ((V){0, 1, 2, 3, 4, 5, 6, 7} == idxv);
v = (v & ~mask) | (valv & mask);
return v;
}
Bootstrap is fine, reg
On Mon, Oct 19, 2020 at 5:07 PM Richard Biener
wrote:
>
> On Mon, Oct 19, 2020 at 10:21 AM Hongtao Liu wrote:
> >
> > Hi:
> > It's implemented as below:
> > V setg (V v, int idx, T val)
> >
> > {
> > V idxv = (V){idx, idx, idx, idx, idx,
On Mon, Oct 19, 2020 at 5:55 PM Richard Biener
wrote:
>
> On Mon, Oct 19, 2020 at 11:37 AM Hongtao Liu wrote:
> >
> > On Mon, Oct 19, 2020 at 5:07 PM Richard Biener
> > wrote:
> > >
> > > On Mon, Oct 19, 2020 at 10:21 AM Hongtao Liu wrote:
> &g
On Mon, Oct 19, 2020 at 11:31 PM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Thu, Oct 15, 2020 at 8:38 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > + /* Simplify vec_s
On Mon, Oct 19, 2020 at 11:38 PM Vladimir Makarov wrote:
>
>
> On 2020-10-11 8:58 p.m., Hongtao Liu wrote:
> > Hi:
> >This is done in 2 steps:
> >1. Extend special memory constraint to handle non MEM_P cases, i.e.
> > (vec_duplicate:V4SF (mem:SF (addr)))
On Tue, Oct 20, 2020 at 10:57 PM Vladimir Makarov wrote:
>
>
> On 2020-10-20 1:33 a.m., Hongtao Liu wrote:
> > On Mon, Oct 19, 2020 at 11:38 PM Vladimir Makarov
> > wrote:
> >>
> >> On 2020-10-11 8:58 p.m., Hongtao Liu wrote:
> >>> Hi:
>
On Wed, Oct 21, 2020 at 12:42 AM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> >> > + && (GET_MODE_NUNITS (mode)).is_constant (&l1)
> >> > + && (GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0
> >> > +
On Wed, Oct 21, 2020 at 5:07 AM Segher Boessenkool
wrote:
>
> On Tue, Oct 20, 2020 at 11:20:48AM +0800, Hongtao Liu wrote:
> > + unsigned HOST_WIDE_INT subreg_offset = 0;
> > + if (GET_CODE (trueop0) == SUBREG
> > +
Hi:
Bootstrap is ok, so is i386/x86-64 regression test.
gcc/ChangeLog:
PR target/97506
* config/i386/i386-expand.c (ix86_expand_sse_movcc): Move
op_true to dest directly When op_true equals op_false,
gcc/testsuite/ChangeLog:
PR target/97506
* gcc.target
On Wed, Oct 21, 2020 at 5:07 PM Jakub Jelinek wrote:
>
> On Wed, Oct 21, 2020 at 02:29:07PM +0800, Hongtao Liu via Gcc-patches wrote:
> > gcc/ChangeLog:
> >
> > PR target/97506
> > * config/i386/i386-expand.c (ix86_expand_sse_movcc): Move
> >
On Wed, Oct 21, 2020 at 11:04 PM Vladimir Makarov wrote:
>
>
> On 2020-10-20 10:11 p.m., Hongtao Liu wrote:
> >
> > Changed, and it passed the i386/x86-64 regression test.
> >
> > Update patch.
> >
> Thank you, Hongtao. This patch is ok for the tr
On Thu, Oct 22, 2020 at 12:36 AM Segher Boessenkool
wrote:
>
> On Wed, Oct 21, 2020 at 04:43:29PM +0100, Richard Sandiford wrote:
> > Hongtao Liu writes:
> > > + poly_uint64 nunits
> > > + = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0)));
>
Hi:
Sorry for Incomplete test for my last patch at
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555948.html.
This patch should fix invalid address introduced by special memory constraint.
Bootstrap is ok, regression test is ok for make check
RUNTESTFLAGS="--target_board='unix{-m32,}
Hi:
For inline asm, there could be an operand like (not (mem:)), it's
not a valid operand for normal memory constraint.
Bootstrap is ok, regression test is ok for make check
RUNTESTFLAGS="--target_board='unix{-m32,}'"
gcc/ChangeLog
PR target/97540
* ira.c: (ira_setup_alts): Ext
ping^1
On Tue, Oct 20, 2020 at 3:36 PM Richard Biener
wrote:
>
> On Tue, Oct 20, 2020 at 4:35 AM Hongtao Liu wrote:
> >
> > On Mon, Oct 19, 2020 at 5:55 PM Richard Biener
> > wrote:
> > >
> > > On Mon, Oct 19, 2020 at 11:37 AM Hongtao Liu wrote:
>
On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > For inline asm, there could be an operand like (not (mem:)), it's
> > not a valid operand for normal memory constraint.
> > Bootstrap is ok, r
On Thu, Oct 29, 2020 at 2:46 AM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu via Gcc-patches writes:
> >> > Hi:
> >> > For inline asm, th
On Wed, Oct 28, 2020 at 8:24 PM Uros Bizjak wrote:
>
> On Wed, Oct 28, 2020 at 10:54 AM Hongyu Wang wrote:
> >
> > Hi Uros,
> >
> > Thanks for the example. We've update the patterns with new expanders
> > and predicates like vzeroall.
> > Now the generated insn for "encodekey128u32" is like
> >
On Tue, Oct 27, 2020 at 7:13 PM Richard Sandiford
wrote:
>
> Hongtao Liu via Gcc-patches writes:
> > Hi:
> > For inline asm, there could be an operand like (not (mem:)), it's
> > not a valid operand for normal memory constraint.
> > Bootstrap is ok, r
On Fri, Oct 14, 2022 at 4:00 PM Haochen Jiang via Gcc-patches
wrote:
>
> From: Hongyu Wang
>
> Hi all,
>
> This patch aimed to add Intel AMX-FP16 ISA according to newly
> released Intel Architecture Instruction Set Extensions and Future Features.
>
> The document comes following:
> https://www.in
On Fri, Nov 4, 2022 at 4:14 PM Haochen Jiang via Gcc-patches
wrote:
>
> From: "Hu, Lin1"
>
> Hi all,
>
> This patch aimed to add initial Granite Rapids support for GCC.
> It needs to be checked in after prefetchit0/t1 patch.
>
> The information for Granite Rapids comes following:
> https://www.in
* gcc.target/i386/x86gprintrin-4.c: Ditto.
> * gcc.target/i386/x86gprintrin-5.c: Ditto.
> * gcc.target/i386/prefetchi-1.c: New test.
> * gcc.target/i386/prefetchi-2.c: Ditto.
> * gcc.target/i386/prefetchi-3.c: Ditto.
> * gcc.target/i386/pre
On Sun, Nov 6, 2022 at 9:00 PM Kong, Lingling via Gcc-patches
wrote:
>
> Hi
>
> The patch is to add flag -mprefer-remote-atomic to control whether to
> generate raoint insn for atomic operations.
> Ok for trunk?
Ok with below 2 little adjustments.
>
> BRs,
> Lingling
>
> gcc/ChangeLog:
>
>
On Sun, Nov 6, 2022 at 8:56 PM Kong, Lingling via Gcc-patches
wrote:
>
> Hi,
> The patches aimed to add Intel RAO-INT.
>
> The information is based on newly released
> Intel Architecture Instruction Set Extensions and Future Features.
>
> The document comes following:
> https://www.intel.com/conte
On Mon, Nov 7, 2022 at 9:41 AM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/i386-common.cc
> (processor_names): Add grandridge.
> (processor_alias_table): Ditto.
> * common/config/i386/i386-cpuinfo.h:
> (enum processor_typ
On Mon, Nov 7, 2022 at 10:25 PM Richard Biener via Gcc-patches
wrote:
>
> On Wed, Nov 2, 2022 at 4:37 AM Hongyu Wang wrote:
> >
> > Hi, this is the updated patch of
> > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604345.html,
> > which uses targetm.loop_unroll_adjust as gate to enable
On Tue, Nov 8, 2022 at 9:17 AM liuhongt wrote:
>
> Memory attribute auto detection will check operand 2 for type sselog,
> and check operand 1 for type sselog1. For below 2 insns, there's no
> operand 2. Change type to sselog1.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for
On Tue, Nov 8, 2022 at 6:07 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Fri, Nov 04, 2022 at 03:46:32PM +0800, Haochen Jiang via Gcc-patches wrote:
> > We will take back the patches which add a new parameter on original
> > builtin_prefetch and implement instruction prefetch on that.
> >
> > Al
On Wed, Nov 9, 2022 at 3:15 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> As Hongtao said, the fail on pentiumpro is caused by missing ISA check
> since we are using emit_insn () through new builtins and it won't check
> if the TARGET matches. Previously, the builtin in middle-end will c
ported to sphinx, so you need to
adjust changes in invoke.texi to new sphinx files.
>
> Hongtao Liu via Gcc-patches 于2022年11月8日周二 11:05写道：
> >
> > On Mon, Nov 7, 2022 at 10:25 PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > On Wed, Nov 2, 2022 at 4:3
On Thu, Nov 10, 2022 at 2:04 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> This patch aims to mention newly added Intel ISA and march support.
>
> Ok for trunk?
Ok.
>
> BRs,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 50 ++
> 1 file changed, 50
On Fri, Nov 11, 2022 at 10:47 PM Tamar Christina via Gcc-patches
wrote:
>
> Hi All,
>
> The current i386 implementation of the TARGET_CAN_CHANGE_MODE_CLASS is
> currently
> not useful before re-alloc.
>
> In particular before regalloc optimization passes query the hook using
> ALL_REGS,
> but be
On Fri, Nov 11, 2022 at 10:45 AM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> For all AMX related ISAs, we have a potential dependency on AMX-TILE
> or we even won't have the basic support on AMX.
>
> This patch added those dependency. Ok for trunk?
Ok.
>
> BRs,
> Haochen
>
> gcc/ChangeLog
On Mon, Nov 14, 2022 at 3:57 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Mon, Nov 14, 2022 at 8:52 AM Jakub Jelinek wrote:
> >
> > Hi!
> >
> > Working virtually out of Baker Island.
> >
> > Given
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10
> > the following patch implements atomi
On Mon, Nov 14, 2022 at 5:04 PM Hongtao Liu wrote:
>
> On Mon, Nov 14, 2022 at 3:57 PM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Mon, Nov 14, 2022 at 8:52 AM Jakub Jelinek wrote:
> > >
> > > Hi!
> > >
> > > Working virtually out of
Hi:
I'm from https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606040.html.
> }
>
>/* See if we can get a better vector mode before extracting. */
> diff --git a/gcc/optabs.cc b/gcc/optabs.cc
> index
> cff37ccb0dfc3dd79b97d0abfd872f340855dc96..f338df410265dfe55b6896160090a453cc6a
On Tue, Nov 15, 2022 at 4:51 PM Tamar Christina wrote:
>
> > -Original Message-
> > From: Hongtao Liu
> > Sent: Tuesday, November 15, 2022 8:36 AM
> > To: Tamar Christina
> > Cc: Richard Sandiford ; Tamar Christina via
> > Gcc-patches ; nd ;
> &
On Fri, Nov 11, 2022 at 10:47 PM Tamar Christina via Gcc-patches
wrote:
>
> Hi All,
>
> The current i386 implementation of the TARGET_CAN_CHANGE_MODE_CLASS is
> currently
> not useful before re-alloc.
>
> In particular before regalloc optimization passes query the hook using
> ALL_REGS,
> but be
On Mon, Nov 14, 2022 at 10:14 AM Hongtao Liu wrote:
>
> On Fri, Nov 11, 2022 at 10:47 PM Tamar Christina via Gcc-patches
> wrote:
> >
> > Hi All,
> >
> > The current i386 implementation of the TARGET_CAN_CHANGE_MODE_CLASS is
> > currently
> > not
On Fri, Nov 11, 2022 at 5:09 PM Cui,Lili via Gcc-patches
wrote:
>
> From: Lili Cui
>
> Hi Hontao,
>
> This patch is to enable 256 move by pieces for ALDERLAKE and AVX2.
> Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
>
> OK for master?
Ok.
>
>
> gcc/Changelog:
>
> * confi
On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford
wrote:
>
> Tamar Christina writes:
> >> -Original Message-----
> >> From: Hongtao Liu
> >> Sent: Tuesday, November 15, 2022 9:37 AM
> >> To: Tamar Christina
> >> Cc: Richard Sa
On Thu, Nov 17, 2022 at 5:39 PM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford
> > wrote:
> >>
> >> Tamar Christina writes:
> >> >> -Original Message-
> >> >> F
On Thu, Nov 17, 2022 at 9:59 PM Richard Sandiford
wrote:
>
> Hongtao Liu writes:
> > On Thu, Nov 17, 2022 at 5:39 PM Richard Sandiford
> > wrote:
> >>
> >> Hongtao Liu writes:
> >> > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford
> &
On Fri, Nov 18, 2022 at 3:50 PM Jakub Jelinek wrote:
>
> On Fri, Nov 18, 2022 at 09:45:22AM +0800, liuhongt via Gcc-patches wrote:
> > This should fix incorrect error when call those builtin with
> > -mavxneconvert and w/o -mavx512bf16 -mavx512vl.
> >
> > Bootstrapped and regtested on x86_64-pc-li
On Tue, Apr 18, 2023 at 3:07 PM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA_AVX512BITALG_SET):
> Change OPTION_MASK_ISA_AVX512F_SET
> to OPTION_MASK_ISA_AVX512BW_SET.
> (OPTION_MASK_ISA_A
On Tue, Apr 18, 2023 at 3:07 PM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA_AVX512VBMI2_SET): Change OPTION_MASK_ISA_AVX512F_SET
> to OPTION_MASK_ISA_AVX512BW_SET.
> (OPTION_MASK_ISA_AVX512F_UNSE
On Tue, Apr 18, 2023 at 2:52 PM Hu, Lin1 via Gcc-patches
wrote:
>
> Hi, all
>
> The patch aims to optimize vshuf{i,f}{32x4,64x2} ymm and vperm{i,f}128.
> And it has regtested on x86_64-pc-linux-gnu. OK for trunk?
Ok.
>
> Thanks.
> Lin
>
> vshuf{i,f}{32x4,64x2} ymm and vperm{i,f}128 ymm are 3 clk.
On Tue, Apr 18, 2023 at 3:13 PM Hu, Lin1 via Gcc-patches
wrote:
>
> More details: Intrinsics guide add these 128/256-bit intrinsics as follow:
> https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=reduce_&ig_expand=5814.
>
> So we intend to enable these intrinsics for GC
On Tue, Apr 18, 2023 at 3:15 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> For vpblendm{b,w}, they actually do not have constant parameters.
> Therefore, there is no need for them been wrapped in __OPTIMIZE__.
>
> Also, we should check TARGET_AVX512VL for 128/256 bit vectors in patterns.
On Tue, Apr 18, 2023 at 3:18 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> Currently in GCC, the 128 bit intrin for instruction vpclmulqdq is
> under PCLMUL ISA. Because there is no dependency between ISA set PCLMUL
> and VPCLMULQDQ, The 128 bit intrin is not available when we just use
>
On Wed, Apr 19, 2023 at 9:54 AM Hongtao Liu wrote:
>
> On Tue, Apr 18, 2023 at 3:18 PM Haochen Jiang via Gcc-patches
> wrote:
> >
> > Hi all,
> >
> > Currently in GCC, the 128 bit intrin for instruction vpclmulqdq is
> > under PCLMUL ISA. Because there
On Tue, Apr 18, 2023 at 2:57 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> Currently in i386, we have several ISAs share builtin between each other
> which is handled in ix86_check_builtin_isa_match with if condition clauses.
>
> The patterns for these clauses are quite similar so it wil
On Tue, Apr 18, 2023 at 3:19 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> Currently in GCC, the 128 bit intrin for instruction vaes{end,dec}{last,}
> is under AES ISA. Because there is no dependency between ISA set AES
> and VAES, The 128 bit intrin is not available when we use compiler
On Thu, Apr 6, 2023 at 1:07 PM Liu, Hongtao via Gcc-patches
wrote:
>
>
>
> > -Original Message-
> > From: Vladimir Makarov
> > Sent: Wednesday, April 5, 2023 8:59 PM
> > To: Jeff Law ; Liu, Hongtao
> > ; gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH] Check hard_regno_mode_ok before sett
On Thu, Apr 20, 2023 at 8:46 AM liuhongt wrote:
>
> 1547 /* If this insn loads a parameter from its stack slot, then it
> 1548 represents a savings, rather than a cost, if the parameter is
> 1549 stored in memory. Record this fact.
> 1550
> 1551 Similarly if we're loading other const
On Mon, May 1, 2023 at 3:37 AM Jeff Law wrote:
>
>
>
> On 4/19/23 21:58, liuhongt via Gcc-patches wrote:
> > Use swap_communattive_operands_p for canonicalization. When both value
> > has same operand precedence value, then first bit in the mask should
> > select first operand.
> >
> > The canonic
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