Martin Jambor wrote:
> Hi,
>
> On Tue, Mar 20, 2012 at 08:16:04PM +0100, Georg-Johann Lay wrote:
>> Martin Jambor wrote:
>>> Hi,
>>>
>>> this is another iteration of my attempts to fix expansion of
>>> misaligned memory accesses on strict-align
Steven Bosscher wrote:
> On Tue, Mar 20, 2012 at 8:54 PM, Georg-Johann Lay wrote:
>> Dropping the first patch which does not work because at expand-time there
>> must not be pre-/post-modify addressing :-(
>
> Have you tried to fix that, instead? Or at least ask around a bit
http://gcc.gnu.org/viewcvs?view=revision&revision=185685
Applied as obvious.
Johann
Backport from mainline r185259.
PR other/52545
* output.h (SECTION_EXCLUDE, SECTION_MACH_DEP): Don't use
SECTION_MACH_DEP reserved bits for SECTION_EXCLUDE.
Georg-Johann Lay wrote:
> This patch adds memory barriers to
>
> __builtin_avr_nop
> __builtin_avr_sei
> __builtin_avr_cli
> __builtin_avr_wdr
> __builtin_avr_sleep
> __builtin_avr_delay_cycles
>
> so that their code cannot be dragged over memory accesses.
>
>
http://gcc.gnu.org/viewcvs?view=revision&revision=185696
Backported these address-space tests from trunk.
http://gcc.gnu.org/viewcvs?view=revision&revision=185697
Backported these from trunk to 4.7.
Johann
libgcc/
Backport from 2012-03-07 mainline r185033.
PR target/52507
* config/avr/lib1funcs.S (__movmemx_hi): Fix loop label in RAM-part.
Backport from 2012-03-07 m
http://gcc.gnu.org/viewcvs?view=revision&revision=185793
http://gcc.gnu.org/viewcvs?view=revision&revision=185794
This adds LTO tests to avr-torture.exp:
* gcc.target/avr/torture/avr-torture.exp (AVR_TORTURE_OPTIONS):
Add "-Os -flto" to list.
Johann
This implements TARGET_BUILTIN_DECL which is needed to make
LTO work with target-specific built-ins.
struct avr_builtin_description gets a new field .fndecl which is
initialized during avr_init_builtins and looked up in new hook
avr_builtin_decl.
The built-ins are initialized in such a way that t
This patch fixes a problem with the -mtiny-stack option:
Architectures avr2 and avr25 mix targets with 8-bit SP and 16-bit SP so that
-mtiny-stack is no good for multilib selection:
If a frame pointer has to be set up from an 8-bit SP it is a difference if
there is no SP_H or of the SP is just tr
Backported from trunk to 4.7:
PR52737 - -mtiny-stack shall not influence multilib selection
http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=185908
PR52692 - Add support for avr-specific built-ins + LTO
http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=185911
http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=185912
Reverts the changes for
PR51002 - SP_H register used even on targets without SP_H
PR51002 has been re-scheduled for 4.7
> This patch takes a different approach to fixing PR52543 than does the
> patch in
>
> http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00641.html
>
> This patch transforms the lower-subreg pass(es) from unconditionally
> splitting wide moves, zero extensions, and shifts, so that it now takes
> in
-``XMEGA'' devices with more than 128@tie{}KiB of program memory and
-more than 64@tie{}KiB of RAM.
-@*@var{mcu}@tie{}= @code{atxmega128a1}, @code{atxmega128a1u}.
-
-@end table
-
+@include avr-mmcu.texi
@item -maccumulate-args
@opindex maccumulate-args
Index: config/avr/gen-avr-mmcu-texi.c
=
Fixed this typo in PSImode reads via *(X+const)
http://gcc.gnu.org/viewcvs?view=revision&revision=186588
http://gcc.gnu.org/viewcvs?view=revision&revision=186589
Committed as obvious.
Johann
PR target/53033
* config/avr/avr.c (avr_out_load_psi): Fix assembler template for
Denis Chertykov schrieb:
This patch adds a new file ./gcc/doc/avr-mmcu.texi that lists all valid
-mmcu= settings and replaces the respective text in invoke.texi by
@include avr-mmcu.texi
Up to now, there is no complete list of -mmcu= options, and a list is
hard to maintain by hand because it c
This implements HARD_REGNO_CALL_PART_CLOBBERED.
Ok to apply?
Johann
PR target/53065
* config/avr/avr.h (HARD_REGNO_CALL_PART_CLOBBERED): New hook define.
Index: config/avr/avr.h
===
--- config/avr/avr.h (revision 186
Committed as obvious.
http://gcc.gnu.org/viewcvs?view=revision&revision=186775
Johann
PR testsuite/52641
PR tree-optimizations/52891
* gcc.c-torture/compile/pr52891-2.c: Fix test for 16-bit int.
Denis Chertykov wrote:
> Let's wait for
> http://gcc.gnu.org/ml/gcc-patches/2011-10/msg01874.html
As that patch is now upstream, here the updated version.
Difference to the prior implementation of AS1 is:
o If no LPMX instruction is available and more than 2 bytes
have to be loaded, a libgcc
Subtracting 0x20 to get the SFR address from a RAM address is scattered all
over the backend. The patch makes - PRINT_OPERAND_PUNCT_VALID_P and uses %- to
subtract the SFR offset instead of hard coded magic number 0x20 all over the
place. The offset is stored in a new field base_arch_s.sfr_offset
This implements assembler drop-in replacement for 64-bit division/remainder.
The original libgcc implementation is extremely resource gulping because it
uses inline in several places and DImode is resource gulping, anyway.
With the patch the sizes (accumulated over all modules with same name) are
Denis Chertykov wrote:
> 2011/11/20 Georg-Johann Lay <.>:
>> Subtracting 0x20 to get the SFR address from a RAM address is scattered all
>> over the backend. The patch makes - PRINT_OPERAND_PUNCT_VALID_P and uses %-
>> to
>> subtract the SFR offset instead of
After updating my local copy I get new runtime FAILs in the test suite because
of the following sequence, e.g. from gcc.c-torture/execute/990527-1.c:
sbiw r28,1 ; 12 addhi3_clobber/1[length = 1]
ldi r24,lo8(9) ; 24 *movhi/5[length = 2]
clr r25
This adds support for DImode insns that don't operate byte-wise like NEG,
COMPARE, PLUS, MINUS, ASHIFT, LSHIFTRT, ASHIFTRT, ROTATE.
The crucial point is that there is no movdi, with the following reasoning as
cited from new avr-dimode.md:
;; The purpose of this file is to provide a light-weight D
Richard Henderson schrieb:
On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
;; The caveat is that if there are insns for some mode, there must also be a
;; respective move insn that describes reloads. Therefore, this
;; implementation uses an accumulator-based model with two hard-coded
This is a small extension to -mlog
* Print double_int with %D or %X
* Print supported sub-options with ?
* Fix thinko in avr_log_set_avr_log that ignored -mdeb.
Ok for trunk?
Johann
PR target/50566
* config/avr/avr-protos.h (avr_log_t): Add field .builtin.
* config/avr/a
Committed as obvious:
http://gcc.gnu.org/viewcvs?view=revision&revision=181700
Johann
--
Index: ChangeLog
===
--- ChangeLog (revision 181699)
+++ ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2011-11-24 Georg-Johann
Georg-Johann Lay wrote:
> Denis Chertykov wrote:
>> 2011/11/20 Georg-Johann Lay <.>:
>>> Subtracting 0x20 to get the SFR address from a RAM address is scattered all
>>> over the backend. The patch makes - PRINT_OPERAND_PUNCT_VALID_P and uses
>>> %-
This adds two built-in functions that facilitate moving bits.
The two built-ins work the same way; there is a 16-bit version and a 8-bit
version.
The first operand specifies a mapping to apply to the second operand:
The n-th nibble of the mapping specifies the image of the n-th bit.
Typical use
For devices with 8-bit SP reading the high byte SP_H of SP will get garbage.
The patch uses CLR instead of IN SP_H to "read" the high part of SP.
There are two issues with this patch:
== 1 ==
I cannot really test it because for devices that small running test suite
does not give usable results.
Georg-Johann Lay wrote:
> For devices with 8-bit SP reading the high byte SP_H of SP will get garbage.
>
> The patch uses CLR instead of IN SP_H to "read" the high part of SP.
>
> There are two issues with this patch:
>
> == 1 ==
>
> I cannot really t
Ian Lance Taylor wrote:
> Georg-Johann Lay writes:
>
>> So if a frontend can define address spaces and it is a generic feature, the
>> question is how to get the name of an address space in a generic, language
>> independent way.
>
> We could decide that all fro
Richard Henderson wrote:
> On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
>> ;; The caveat is that if there are insns for some mode, there must also be a
>> ;; respective move insn that describes reloads. Therefore, this
>> ;; implementation uses an accumulator-based mode
Denis Chertykov wrote:
2011/11/29 Georg-Johann Lay:
I attached a patch but I fail to find the right configure options for
gcc/binutils as the testsuite complains
./avr/bin/ld: bad -plugin option
Configured gcc with --enable-lto and binutils 2.21 with --enable-plugin.
Maybe the patch can be
Nick Clifton wrote:
> Hi Denis, Hi Anatoly, Hi Eric,
>
> The patch below fixes the current problem building gcc for the avr-elf
> toolchain by providing a local copy of the c_addr_space_name
> function. I am not sure if the space names are correct, but at least
> this allows me to build t
Georg-Johann Lay wrote:
> For devices with 8-bit SP reading the high byte SP_H of SP will get garbage.
>
> The patch uses CLR instead of IN SP_H to "read" the high part of SP.
>
> There are two issues with this patch:
>
> == 1 ==
>
> I cannot really t
Joerg Wunsch wrote:
> As Georg-Johann Lay wrote:
>
>> There is ATtiny4313 (and maybe others) that have 8-bit SP and 0x100 RAM.
>> As RAM starts at 0x60, I wonder what the meaning of SP is?
>
> I think this is simply a bug in the datasheet. The device description
>
Richard Earnshaw wrote:
> On 29/11/11 09:42, Matthew Gretton-Dann wrote:
>> All,
>>
>> Whilst developing the Cortex-A15 integer pipeline patch it was noted
>> that the MD_INCLUDES variable in config/arm/t-arm has not been kept
>> up-to-date.
>>
>> The attached patch fixes this, and rearranges the
Denis Chertykov wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off per default)
[ ] Set it on per default
As soon as the direction is clear, I'll post a follow-up patch to
add the mis
Joerg Wunsch wrote:
> As Georg-Johann Lay wrote:
>
>> Then avr-mcus.def adopted this bug from the manual for ATtiny4313 at least:
>>
>> AVR_MCU ("attiny4313", ARCH_AVR25, "__AVR_ATtiny4313__", 1 /* short_sp,
>> should
>> be 0 ? */, 0, 0x00
Denis Chertykov wrote:
> 2011/11/29 Georg-Johann Lay :
>> Ian Lance Taylor wrote:
>>> Georg-Johann Lay writes:
>>>
>>>> So if a frontend can define address spaces and it is a generic feature, the
>>>> question is how to get the name of an addres
http://gcc.gnu.org/viewcvs?view=revision&revision=181933
Committed the following, obvious fix to a test case that assumed
sizeof(int) = 4:
Johann
--- trunk/gcc/testsuite/gcc.c-torture/execute/vector-subscript-1.c
2011/12/02
17:44:28181932
+++ trunk/gcc/testsuite/gcc.c-torture/ex
Denis Chertykov wrote:
> 2011/11/29 Georg-Johann Lay:
>> For devices with 8-bit SP reading the high byte SP_H of SP will get garbage.
>>
>> The patch uses CLR instead of IN SP_H to "read" the high part of SP.
>>
>> There are two issues with this patch:
Georg-Johann Lay schrieb:
Denis Chertykov wrote:
Georg-Johann Lay:
I attached a patch but I fail to find the right configure options for
gcc/binutils as the testsuite complains
./avr/bin/ld: bad -plugin option
Maybe the patch can be pre-approved so that the others can proceed with their
Georg-Johann Lay wrote:
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg02574.html
As this is a blocker and I am blocked myself by a collect2 issue:
Eric, Denis, could one of you test the patch and apply it if it is okay?
It is PR51409.
In addition, please add PR49868 to the ChangeLog. Thanks
Denis Chertykov wrote:
> 2011/11/29 Georg-Johann:
>> Ian Lance Taylor wrote:
>>> Georg-Johann Lay:
>>>
>>>> So if a frontend can define address spaces and it is a generic feature, the
>>>> question is how to get the name of an address space in a g
Georg-Johann Lay wrote:
> Denis Chertykov wrote:
>
>>>>> The only question that remains is what the -m64 option should be like?
>>>>>
>>>>> [ ] Omit it altogether
>>>>> [ ] Leave it as is (off per default)
>>>>> [ ]
In principle, test case pr45830.c works for target avr, but there is an issue
with the -ftree-switch-conversion optimization activated at higher optimization
levels: It transforms code size into .data usage and thus exceeds AVRs' RAM
size because of big CSWTCH lookup tables located in RAM.
The pat
I allowed me to apply the following change:
http://gcc.gnu.org/viewcvs?view=revision&revision=182109
Assumptions like sizeof(int)==4 or sizeof(void*)==4 are the most frequent cause
for annoying false FAILing C test cases.
Besides that: Why are there new test cases in gcc.c-torture?
As far as I
Jakub Jelinek wrote:
> On Thu, Dec 08, 2011 at 01:54:17PM +0100, Georg-Johann Lay wrote:
> The test should be using
> typedef __INT16_TYPE__ int16_t;
> typedef __INT32_TYPE__ int32_t;
> instead of what you are proposing.
Ah, thanks for the hint! Looks way better now.
Johann
This are assembler implementations for Dimode multiplication.
Tested without regressions, the only change in the test suite I get is for
gcc.c-torture/execute/arith-rand-ll.c execution, -O0
UNTESTED -> PASS
because the former vanilla C implementation ran into timeout.
Ok for trunk?
Johann
This is obvious patch for PR51425: SBIC/SBRC instructions are generated by insn
combine, but insn combine tries zero_extract:QI not zero_extract:HI as in good
old times.
Thus, use QIHI iterator.
Besides fixing this optimization flaw, it enables other developers to reproduce
PR51374: If the patt
Andrew Pinski wrote:
> Hi,
> After SSA-expand, the code which did the optimization for
> (a&(1<>C)&1 became not working because BIT_AND_EXPR
> would no longer be in there. This patch fixes the problem by using
> get_def_for_expr to get the BIT_AND_EXPR.
>
> OK? Bootstrapped and tested on x86_6
Jakub Jelinek wrote:
> On Fri, Dec 09, 2011 at 01:50:37PM +0100, Georg-Johann Lay wrote:
>> No, not OK.
>>
>> This leads to unacceptable code for devices that cannot shift easily like,
>> e.g.
>> AVR. This target can only shift by 1 and shifts with big offsets ha
http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00474.html
Georg-Johann Lay wrote:
> In principle, test case pr45830.c works for target avr, but there is an issue
> with the -ftree-switch-conversion optimization activated at higher
> optimization
> levels: It transforms code size into
This adds missing 24-Bit multiplication.
Besides implementing __mulpsi3 in libgcc the patch adds some minor tweaks to
multiply with small numbers and to represent the reduced register footprint of
asm implementations.
With this patch PR50931 is complete from the target side.
(But there is still a
This is fix for the RP. Is uses (reg:QI 28) instead of building SUBREG of frame
pointer.
Johann
PR target/51050
* config/avr/avr.c (expand_epilogue): Don't build SUBREG of fp.
(avr_prologue_setup_frame): Ditto.
Index: gcc/config/avr/avr.c
==
This fixes PR51345: lib1funcs.S accesses SPH register even on devices that
don't have it.
There are 2 issues with SPH here:
* Reading non-existent SFR
* Assuming SPH = 0 lead to smaller code for devices without SPH
Devices with 8-bit SP are the ones that need size optimizations most
This patch
http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00471.html
Georg-Johann Lay wrote:
> Georg-Johann Lay wrote:
>> Denis Chertykov wrote:
>>
>>>>>> The only question that remains is what the -m64 option should be like?
>>>>>>
>>>>>&
Joerg Wunsch wrote:
> As Georg-Johann Lay wrote:
>
>> With the patch it looks like so:
>>
>> .
>> ./tiny-stack
>> ./avr25
>> ./avr25/tiny-stack
>> ./avr3
>> ./avr31
>> ./avr35
>> ./avr4
>> ./avr5
>> ./avr51
>> .
Implements target hooks
TARGET_PRINT_OPERAND
TARGET_PRINT_OPERAND_ADDRESS
TARGET_PRINT_OPERAND_PUNCT_VALID_P
Ok?
Johann
* config/avr/avr-protos.h (print_operand): Remove.
(print_operand_address): Remove.
* config/avr/avr.h (PRINT_OPERAND): Remove.
(PRINT_OPERAND_
Joseph S. Myers schrieb:
On Thu, 15 Dec 2011, Georg-Johann Lay wrote:
Index: gcc/config/avr/genmultilib.awk
===
--- gcc/config/avr/genmultilib.awk (revision 0)
+++ gcc/config/avr/genmultilib.awk (revision 0)
@@ -0,0
Joseph S. Myers wrote:
> On Sun, 18 Dec 2011, Georg-Johann Lay wrote:
>
>>> This new file needs to have the standard copyright and license notices.
>>> It's desirable to generate such notices in the output files as well.
>> What is the right copyright for
Anatoly Sokolov schrieb:
Hi.
This patch removes obsolete REGISTER_MOVE_COST and MEMORY_MOVE_COST
Why are they obsolete?
The internals do not say they are obsolete and the PRINT_* hoohs
documentation does not mention a replacement. There is not even a
documentation for target hooks
TA
Denis Chertykov wrote:
> 2011/12/19 Georg-Johann Lay :
>> Joseph S. Myers wrote:
>>> On Sun, 18 Dec 2011, Georg-Johann Lay wrote:
>>>
>>>>> This new file needs to have the standard copyright and license notices.
>>>>> It's desirable t
Committed the following change because -mbranch-cost was declared twice in
avr.opt:
http://gcc.gnu.org/viewcvs?view=revision&revision=182798
Johann
This is fix for ISR prologue that "cleared" zero reg with
mov __zero_reg__,__zero_reg__
The right way is
clr __zero_reg__
of course. As CLR does change cc0 notice_update_cc needs to be adapted.
Passes testsuite. Moreover, lightly tested on ISR source (there is no ISR test
case in test suit
This removes avr_replace_prefix and rewrites the callers to use ACONCAT.
Passes without regressions.
Ok for trunk?
Johann
* config/avr/avr.c (avr_replace_prefix): Remove.
(avr_asm_named_section): Use ACONCAT instead of avr_replace_prefix.
(avr_asm_function_rodata_section
Denis Chertykov wrote:
> Hi Georg.
>
> I have found that conversion AVR port to using hard_frame_pointer have
> resolved PR 50925 .
> I have tested the patch without regressions, but I'm worry about it.
> Can you test it with your testsuite for regressions ?
> May be you have your own special diff
This patch extends the semantics of 24-bit __pgmx address space qualifier to
cover RAM and Flash.
RAM is represented by setting the high byte of 24-bit address to 0x80. The code
to read from 24-bit address space decides at runtime what instruction to use to
read by if-else decision depending on bi
Denis Chertykov wrote:
> Hi Georg.
>
> I have found that conversion AVR port to using hard_frame_pointer have
> resolved PR 50925 .
> I have tested the patch without regressions, but I'm worry about it.
> Can you test it with your testsuite for regressions ?
> May be you have your own special diff
This PR prints a false warning because missing DECL_EXTERNAL test in
avr_encode_section_info that checks if progmem variables come with initializer
or not.
Ok for trunk?
PR target/51756
* config/avr/avr.c (avr_encode_section_info): Test for absence of
DECL_EXTERNAL when ch
Again: A test case that fails because it incorrectly assumes int is 32 bits
wide.
Ok to apply?
* gcc.c-torture/execute/20120111-1.c: Fix wrong int = int32_t
assumption.
Index: gcc.c-torture/execute/20120111-1.c
==
http://gcc.gnu.org/viewcvs?view=revision&revision=183131
Denis Chertykov schrieb:
Committed
Denis
Some questions regarding the fix:
1) You know if PR42204 is still relevant and can be closed?
Or is it not related to PR50925?
2) Can we remove from avr.c:avr_option_override() the following:
if (avr_strict_X)
flag_caller_saves = 0;
t
Mike Stump schrieb:
On Jan 12, 2012, at 8:44 AM, Georg-Johann Lay wrote:
Again: A test case that fails because it incorrectly assumes int is 32 bits
wide.
Ok to apply?
I'd think the testcase is more naturally:
return ~((uint32_t) (arg > -3));
That not equivalent to the propos
Denis Chertykov wrote:
> Georg-Johann Lay:
>> Denis Chertykov schrieb:
>>
>> 2) Can we remove from avr.c:avr_option_override() the following:
>>
>> if (avr_strict_X)
>> flag_caller_saves = 0;
>>
>> that hacked around similar spill fails?
&
This is again a test case that assumes sizeof (int) > 2 which is not true in
general.
* g++.dg/ipa/pr51759.C: Fix assumption sizeof(int) > 2.
Ok for trunk.
Index: testsuite/g++.dg/ipa/pr51759.C
===
--- testsuite/g++.dg/ipa
This fixed multi-char testcase that would otherwise lead to "constant exceeds
its type" message and thus FAIL.
Use 2-letter constant is sufficient and don't break on int=16 platforms.
Ok to apply?
Johann
* gcc.dg/cpp/warn-multichar-2.c: Fix to work on int=16 platforms.
Index: gcc.dg/cp
Similar to fix for gcc.dg/cpp/warn-multichar-2.c: It's sifficient to have a
2-letter constant.
Ok to apply?
Johann
* gcc.dg/cpp/warn-multichar.c: Fix to work on int=16 platforms.
Index: gcc.dg/cpp/warn-multichar.c
===
---
Fixed as obvious as 1 << 15 fits always inside an int whereas 1<<16 does not.
Ok for trunk?
Johann
* gcc.dg/debug/dwarf2/pr49871.c: Fix to work on int16 platforms.
Index: gcc.dg/debug/dwarf2/pr49871.c
===
--- gcc.dg/debug
http://gcc.gnu.org/viewcvs?view=revision&revision=183151
As explained in its comment, the test case works only if BRANCH_COST > 1.
This is done by the patch.
* gcc.dg/pr46309.c: Set branch cost to greater 1 for avr.
--- trunk/gcc/testsuite/gcc.dg/pr46309.c2012/01/13 05:11:45
This patch adds -Wno-pointer-to-int-cast to the options in order to avoid FAIL
because of "warning: cast from pointer to integer of different size" when
sizeof(void*) = 2.
* gcc.dg/pr50527.c: Don't FAIL if sizeof(void*) = 2
Index: gcc.dg/pr50527.c
Following test case has wrong prototypes of malloc/memset and this is the fix.
* gcc.dg/lto/20090218-2_1.c: Fix prototype of malloc, memcpy.
Index: gcc.dg/lto/20090218-2_1.c
===
--- gcc.dg/lto/20090218-2_1.c (revision 18315
This test case is obviously written for 32-bit platforms, thus added
"dg-require-effective-target ilp32" to ensure that the pointer mess won't lead
to FAILs because of
warning: cast to pointer from integer of different size
and
warning: cast from pointer to integer of different size
Ok to apply
Denis Chertykov wrote:
> Committed
>
> Denis
Consider code prom PR51374
void __vector_18 (void)
{
extern char slot;
unsigned char status = (*(volatile unsigned char*) 0x2B);
unsigned char data = (*(volatile unsigned char*) 0x2C);
if (status & 0x10)
slot = 0;
}
the cod
Mike Stump wrote:
> On Jan 13, 2012, at 9:23 AM, Rainer Orth wrote:
>> Mike Stump writes:
>>
>>> On Jan 13, 2012, at 4:33 AM, Georg-Johann Lay wrote:
>>>> This test case is obviously written for 32-bit platforms, thus added
>>>> "dg-require-ef
Mike Stump wrote:
> On Jan 13, 2012, at 4:20 AM, Georg-Johann Lay wrote:
>> Following test case has wrong prototypes of malloc/memset and this is the
>> fix.
>>
>> * gcc.dg/lto/20090218-2_1.c: Fix prototype of malloc, memcpy.
>
> [ be sure to add Ok? to p
Jakub Jelinek wrote:
> On Fri, Jan 13, 2012 at 07:40:59PM +0100, Georg-Johann Lay wrote:
>> The ilp32 is the closes match:
>>
>> The source casts pointer to int, int to pointer, long to int, uses 32-bit
>> initializers for int, assumes size_t is unsigned long any maybe o
Jakub Jelinek wrote:
> On Fri, Jan 13, 2012 at 08:25:39PM +0100, Georg-Johann Lay wrote:
>> So it's fine to dump any code to the test suite no matter on what platform it
>> might break or work?
>
> It is wrong to knowingly commit testcases that break on such platforms,
Rainer Orth schrieb:
Mike Stump writes:
On Jan 13, 2012, at 4:33 AM, Georg-Johann Lay wrote:
This test case is obviously written for 32-bit platforms, thus added
"dg-require-effective-target ilp32" to ensure that the pointer mess won't lead
to FAILs because of
warning:
This is basically documentation of AVR specific extensions and stuff like
* command line options like -maccumulate-args etc.
* AVR named address spaces
Section doc/extend.texi::Named Address Spaces is split into several subsections
now; each subsection taking care of one target in alphabetical or
Georg-Johann Lay wrote:
> This is basically documentation of AVR specific extensions and stuff like
>
> * command line options like -maccumulate-args etc.
> * AVR named address spaces
>
> Section doc/extend.texi::Named Address Spaces is split into several
> subsections
&
Richard Guenther wrote:
> This should fix PR51782 - we need to look at the base address operand
> of MEM_REF and TARGET_MEM_REF to get at the address-space information
> as both can have an embedded VIEW_CONVERT_EXPR. This is then
> consistent with the gimple type system which keeps address-space
Adding AVR-specific release notes to wwwdocs/htdocs/gcc-4.7/changes.html
Ok?
Johann
Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.73
diff -u -r1.73 changes.html
--- changes.htm
Besides fixing some typos, this patch adds an example that shows how to access
code located with attribute progmem.
The example in "AVR named address spaces" is moved up and the note on offset
limitation is removed.
Ok to apply?
Johann
PR target/49868
* doc/extend.texi (AVR Name
This patch renames the named address spaces from their initial draft names to
their final names as proposed by several developers, amongst them Eric.
* Using __flash will make porting to/from other compilers easier.
* "__flash" is more descriptive than the meaningless "__pgm".
* __pgm might lead t
http://gcc.gnu.org/ml/gcc-patches/2012-01/msg01020.html
Georg-Johann Lay wrote:
> Adding AVR-specific release notes to wwwdocs/htdocs/gcc-4.7/changes.html
>
> Ok?
>
> Johann
>
This patch fixes PR51374 by more strictly updating mem_last_set.
Sloppy handling of mem_last_set can lead to error in volatile correctness
because combine then is allowed to drag one volatile access over an other
volatile thing (volatile access, asm volatile, unspec_volatile...).
As explained in t
This patch aims at better support of CPSE instruction in cases where otherwise
code like
TST Rn ; *cmpqi
BREQ .+2; branch
RJMP .Lm
would be produced. As branch is not a single instruction, it cannot be skipped.
peephole seems to be the only feature that can do this op
Jakub Jelinek wrote:
> On Fri, Jan 13, 2012 at 07:40:59PM +0100, Georg-Johann Lay wrote:
>> The ilp32 is the closes match:
>>
>> The source casts pointer to int, int to pointer, long to int, uses 32-bit
>> initializers for int, assumes size_t is unsigned long any maybe o
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