Some avr options were missing the "Optimization" flag, which
is added by this patch.
Johann
--
AVR: Tag optimization options as "Optimization".
Some options that are pure optimizations where not tagged as such.
gcc/
* config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
Am 19.02.24 um 08:36 schrieb Richard Biener:
On Sat, Feb 17, 2024 at 11:30 AM wrote:
From: Pan Li
This patch would like to add the middle-end presentation for the
unsigned saturation add. Aka set the result of add to the max
when overflow. It will take the pattern similar as below.
SAT
Am 27.02.24 um 12:15 schrieb Tamar Christina:
Am 19.02.24 um 08:36 schrieb Richard Biener:
On Sat, Feb 17, 2024 at 11:30 AM wrote:
From: Pan Li
This patch would like to add the middle-end presentation for the
unsigned saturation add. Aka set the result of add to the max
when overflow.
The condition when a frame pointer is required because
arguments are passe on the stack was not exact, and
there were situations when a frame was set up without
a need for it.
Johann
--
AVR: target/114132 - Code sets up a frame pointer without need.
The condition CUMULATIVE_ARGS.nregs == 0 in
Installes this minor improvement to the AVR documentations.
Johann
--
gcc/
* config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
Reduced Tiny.
* config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
* doc/extend.texi (AVR Variable Attr
This adds a new @subsubsection "AVR Internal Options" in
"AVR Options".
"Internal" options are options that are not supposed to be
set by the user, but are solely required to ship information
from device-specs to the compiler proper.
(Without device-specs, non of these options would be needed
be
Am 12.01.24 um 04:37 schrieb Jan-Benedict Glaw:
On Thu, 2024-01-04 17:28:02 +0100, Georg-Johann Lay wrote:
This fixes the avr-specific attributes io, io_low and address,
that are all basically the same except that io and io_low imply
assertions on allowed addressing modes.
--- a/gcc
Since the advent of devices AVR*, the spec pattern mmcu=avr* does no
more work to discriminate between devices and cores like avr51.
This means -nodevicelib no more works for AVR* devices because that
option is removed for mmcu=avr* (which were only cores in the old days).
Instead of that patter
avr attribute "address" only supports exactly one argument,
fixed thusly.
Johann
--
AVR: Documentation: Attribute address has exactly one argument.
gcc/
* doc/extend.texi (AVR Variable Attributes) [address]: Remove
documentation for a version without argument, which is not supp
This links an example from the avr-gcc wiki that shows how to set up
a linker script for the __flashN avr address spaces in
section AVR Named Address Spaces of the GCC user manual.
Johann
--
AVR: Documentation: Web-Link an example ld-Script for Address-Space
__flashN.
gcc/
* doc/exte
Ping #3
RFA: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640140.html
Ping #1 https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640981.html
Ping #2 https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641912.html
This is a patch that locates .rodata in flash for some AVR
devic
https://gcc.gnu.org/gcc-14/changes.html#avr
Johann
--
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 9c9dfa44..8c738683 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -342,7 +342,55 @@ a work-in-progress.
-
+AVR
+
+ On AVR64* and
I went ahead and installed Andrew's patch
https://gcc.gnu.org/r14-7240
Johann
Am 15.01.24 um 00:19 schrieb Levente via Gcc-help:
I'm trying to set up a toolchain for avr-dd MCUs, and I get this error
message when I try to compile gcc:
Lev
--
Author: Andrew Pinski
Date: Mon Jan 15 10:31:
Option -mskip-bug is no more missing from the documentation.
Johann
--
AVR: Document option -mskip-bug.
gcc/
* doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1773f0d3f0c..01170c0ce5c 100644
--- a/gcc/doc/inv
This adds some more entries to avr-mcus.def
Johann
--
AVR: Add AVR16EB, AVR16EA and AVR32EA devices.
gcc/
* config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
(avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
* doc/avr-mmcu.texi:
This fixes a typo in the diagnose of a spec.
Also re-uses a spec for a simpler specs file.
Johann
--
AVR: Fix typo in device-specs generation. Reuse -m[no-]rodata-in-ram
checker.
gcc/
* config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
in the diagnostic, an
The C++ files in the avr backend are a mix of TABS and
8 spaces for indentation. This patch rectifies that
according to the coding rules.
I applied this prior to the advent of the v14 branch so
that back-porting will be easier, at least from the new master
to v14.
Johann
--
gcc/
*
Am 18.01.24 um 20:54 schrieb Roger Sayle:
This patch tweaks RTL expansion of multi-word shifts and rotates to use
PLUS rather than IOR for disjunctive operations. During expansion of
these operations, the middle-end creates RTL like (X<>C2)
where the constants C1 and C2 guarantee that bits d
Am 22.01.24 um 08:45 schrieb Richard Biener:
On Fri, Jan 19, 2024 at 5:06 PM Georg-Johann Lay wrote:
Am 18.01.24 um 20:54 schrieb Roger Sayle:
This patch tweaks RTL expansion of multi-word shifts and rotates to use
PLUS rather than IOR for disjunctive operations. During expansion of
Applied, this adds 6 more devices, 2 new and 4 fairly old
for completeness.
Johann
--
AVR: Add AVR64DU and some older devices.
gcc/
* config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
ATA5835, ATtiny64AUTO, ATA5700M322.
* doc/avr-mmcu.texi: Rebuild.diff --git
avr.cc still had a mix of spaces and TABs for indentation.
This patch uses TABs according to the coding rules.
Applied prior to the creation of the v14 branch so that
master -> v14 back-porting will be easier.
Johann
--
AVR: Tabify avr.cc
gcc/
* config/avr/avr.cc: Tabify.
<>
Ping #1
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640140.html
FYI, Binutils https://sourceware.org/PR31124 us upstream.
Johann
This is a patch that locates .rodata in flash for some AVR
devices that can support it. All new functionality depends
on Binutils PR31124 and is switc
This fixes the avr-specific attributes io, io_low and address,
that are all basically the same except that io and io_low imply
assertions on allowed addressing modes.
It also improves some diagnostics.
Johann
--
gcc/
PR target/112952
* config/avr/avr.cc (avr_handle_addr_attribu
Ping #2
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640140.html
FYI, Binutils https://sourceware.org/PR31124 is upstream.
Johann
This is a patch that locates .rodata in flash for some AVR
devices that can support it. All new functionality depends
on Binutils PR31124 and is switch
This fixes more of the sloppy tests that assume sizeof(int) = 4 etc.
Johann
--
testsuite/52641: Fix sloppy tests that did not care for sizeof(int)=2 etc.
gcc/testsuite/
PR testsuite/52641
* gcc.c-torture/compile/attr-complex-method-2.c [target=avr]: Check
for "divsc3" a
This patch rectifies more tests that make assumptions on
sizeof(int), sizeof(void*), etc.
Johann
--
testsuite/52641: Fix fallout from sloppy tests.
gcc/testsuite/
PR testsuite/52641
* gcc.dg/memchr-3.c [avr]: Anticipate -Wbuiltin-declaration-mismatch.
* gcc.dg/pr103207.
Made some tests more generic so they can pass on more targets.
Johann
--
testsuite/52641: Fix fallout from sloppy tests.
gcc/testsuite/
PR testsuite/52641
* gcc.dg/torture/pr110838.c: Use proper shift offset to get MSB or int.
* gcc.dg/torture/pr112282.c: Use at least 3
Am 07.01.24 um 17:45 schrieb Jeff Law:
On 1/7/24 08:53, Georg-Johann Lay wrote:
Made some tests more generic so they can pass on more targets.
Johann
--
testsuite/52641: Fix fallout from sloppy tests.
gcc/testsuite/
PR testsuite/52641
* gcc.dg/torture/pr110838.c: Use proper
The patch below fixes some obvious problems in gcc.target/avr:
* Remove duplicate -mmcu=
* Skip tests with address spaces on Reduced Tiny which does not support
address spaces at all.
* Address spaces are GNU-C, but some tests were missing -std=gnu*
* Don't test address-space __flash1 on dev
This is a patch that locates .rodata in flash for some AVR
devices that can support it. All new functionality depends
on Binutils PR31124 and is switched on by configure checks
for the new emulations.
https://sourceware.org/PR31124
For explanation of the gcc part see commit message below.
Most
Applied this patch that improves IEEE double multiplication.
The old code consumed time for calling local helpers and to
prepare arguments.
Functions that use mul like expl or sinl are around 5%...9% faster
now. The code size did not increase.
Johann
--
LibF7: Tweak IEEE double multiplication
Am 02.11.23 um 12:50 schrieb Roger Sayle:
This patch optimizes a few special cases in avr.md's *insv.any_shift.
instruction. This template handles tests for a single bit, where the result
has only a (different) single bit set in the result. Usually (currently)
this always requires a three-in
This uses the paper-pencil method to compute IEEE square root.
It is faster than previous 3 * Newton-Raphson, slightly
more precise, and has almost exact same code size.
Johann
--
LibF7: Use paper-pencil method for sqrt instead of Newton-Raphson iteration.
libgcc/config/avr/libf7/
* l
The address-spaces locate data in their attaches sections like
.progmem.data; but that should only be done if the user did not
specify a section attribute.
Johann
--
PR target/53372: Don't ignore section attribute with address-space.
gcc/
PR target/53372
* config/avr/avr.cc (av
AVR was/is not affected by CVE-2017-5753, thus applies as obvious.
Johann
--
gcc/
PR target/86776
* config/avr/avr.cc (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define
to speculation_safe_value_not_needed.
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index c3e
Am 24.05.24 um 11:13 Am 25.06.24 um 16:03 schrieb Paul Koning:
On Jun 24, 2024, at 1:50 AM, Stefan Schulze Frielinghaus
wrote:
Ping.
On Mon, Jun 10, 2024 at 07:19:19AM +0200, Stefan Schulze Frielinghaus wrote:
Ping.
On Fri, May 24, 2024 at 11:13:12AM +0200, Stefan Schulze Frielinghaus
Am 27.06.24 um 10:51 schrieb Stefan Schulze Frielinghaus:
On Thu, Jun 27, 2024 at 09:45:32AM +0200, Georg-Johann Lay wrote:
Am 24.05.24 um 11:13 Am 25.06.24 um 16:03 schrieb Paul Koning:
On Jun 24, 2024, at 1:50 AM, Stefan Schulze Frielinghaus
wrote:
On Mon, Jun 10, 2024 at 07:19:19AM +0200
Applied some fixes / skips to test cases.
Johann
PR testsuite/52641
gcc/testsuite/
* gcc.dg/analyzer/pr109577.c: Use __SIZE_TYPE__ instead of
"unsigned long".
* gcc.dg/analyzer/pr93032-mztools-signed-char.c: Requires
int32plus.
* gcc.dg/analyzer/pr93032-mztools-
Applies this patch to fix code when the destination
register overlaps with a hard register used by insn
xload_A resp. xload8qi_A (PR115726).
Also fixed PR88236 in one go because that PR is very
similar in its outcome, and it's not possible to discriminate
in a test case which is which, resp. when
Am 01.07.24 um 11:37 schrieb Alejandro Colomar:
gcc/ChangeLog:
* doc/invoke.texi: Document -fasm.
Signed-off-by: Alejandro Colomar
---
gcc/doc/invoke.texi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 30c
Hi Jeff,
This is a patch to get correct code out of 64-bit
loads from address-space __memx.
The AVR address-spaces may require that move insns issue
calls to library support functions, a fact that -ftree-ter
doesn't account for. tree-ssa-ter.cc then replaces an
expression across such a library
...just noticed that disabling -ftree-ter would also fix PR53049
where it moves a volatile asm across a library call.
Am 02.07.24 um 15:42 schrieb Georg-Johann Lay:
Hi Jeff,
This is a patch to get correct code out of 64-bit
loads from address-space __memx.
The AVR address-spaces may require
The movqi output for Reduced Tiny had a wrong condition
and restore statement for the base register in the case
where the destination overlaps the base register.
Applied as obvious.
Johann
--
AVR: target/98762 - Handle partial clobber in movqi output.
PR target/98762
gcc/
* co
Am 02.07.24 um 15:48 schrieb Richard Biener:
On Tue, Jul 2, 2024 at 3:43 PM Georg-Johann Lay wrote:
Hi Jeff,
This is a patch to get correct code out of 64-bit
loads from address-space __memx.
The AVR address-spaces may require that move insns issue
calls to library support functions, a
Am 03.07.24 um 21:39 schrieb Jeff Law:
On 7/3/24 1:26 PM, Georg-Johann Lay wrote:
Am 02.07.24 um 15:48 schrieb Richard Biener:
On Tue, Jul 2, 2024 at 3:43 PM Georg-Johann Lay wrote:
Hi Jeff,
This is a patch to get correct code out of 64-bit
loads from address-space __memx.
The AVR
Address computation (usually add) with symbols that are aligned
to 256 bytes does not require to add the lo8() part as it is zero.
This patch adds a new combine insn that performs a widening add
from QImode plus such a symbol. The case when such an aligned
symbol is added to a reg that's already
Am 04.07.24 um 11:49 schrieb Richard Biener:
On Thu, Jul 4, 2024 at 11:24 AM Richard Biener
wrote:
On Wed, Jul 3, 2024 at 9:26 PM Georg-Johann Lay wrote:
Am 02.07.24 um 15:48 schrieb Richard Biener:
On Tue, Jul 2, 2024 at 3:43 PM Georg-Johann Lay wrote:
Hi Jeff,
This is a patch
Am 04.07.24 um 13:25 schrieb Richard Biener:
On Thu, Jul 4, 2024 at 1:08 PM Georg-Johann Lay wrote:
Am 04.07.24 um 11:49 schrieb Richard Biener:
On Thu, Jul 4, 2024 at 11:24 AM Richard Biener
wrote:
On Wed, Jul 3, 2024 at 9:26 PM Georg-Johann Lay wrote:
Am 02.07.24 um 15:48 schrieb
The DImode expanders from avr-dimode.md have code like
emit_move_insn(acc_a, operands[1])
where acc_a is a hard register and operands[1] may be a
mem reference to a non-generic address-space. The latter
may require a libcall, and since DImode moves are split into
8 QImode moves, these libcalls m
Up to now, a post-reload split for fake PLUS addresses
was only run on AVR_TINY. However, also non-AVR_TINY cores
have some address registers that don't support PLUS addressing,
which is the X register, and the Z register with [E]LPM.
This patch splits also these patterns. The fuse-add pass can
Such tests exists because pre-processed sources are used
as test cases, like they are provided in PRs.
This means they have, say, "unsigned long" instead of size_t,
but "unsigned long" is not a correct size_t on some targets.
Some of the tests can be transformed back so that they use __SIZE_TYPE
Hi Jeff,
This patch adds peephole2s and insns to make better use of
instructions that set condition code (SREG) as a byproduct.
Of course with cc0 all this was *much* simpler... so here we go;
adding CCNmode and CCZNmode, and extra insns that do arith + CC.
No new regressions.
Ok for master?
Am 10.07.24 um 01:17 schrieb Jeff Law:
On 7/9/24 4:03 AM, Georg-Johann Lay wrote:
Hi Jeff,
This patch adds peephole2s and insns to make better use of
instructions that set condition code (SREG) as a byproduct.
Of course with cc0 all this was *much* simpler... so here we go;
adding CCNmode and
There are currently five insns and five splits that handle
subtraction where the subtrahend is zero-extended to the mode
of the minuend.
This patch represents them as one insn (and one split) using
mode iterators.
Applied as obvious.
Johann
--
AVR: Tidy up subtract-and-zero_extend insns.
The
These are insns of the forms
(set (regA:M)
(plus:M (extend:M (regB:L))
(regA:M)))
and
(set (regA:M)
(minus:M (regA:M)
(extend:M (regB:L
where "extend" may be a sign-extend or zero-extend,
and the integer modes satisfy SImode >= M > L >= QImod
Am 12.07.24 um 18:40 schrieb Jeff Law:
On 7/10/24 3:05 AM, Georg-Johann Lay wrote:
The previous change to avr.md was several days ago, and should not
interfere with this one. Anyway, I rebased the patch against
master and attached it below. The patch is atop the ref in the patch
file name
(mode) - 1): Use instead.
(GET_MODE_MASK (QImode)): Use 0xff instead.
* config/avr/avr-fixed.md: Same.commit f840431ff92d6ab35f8e272f875f472e5a599115
Author: Georg-Johann Lay
Date: Mon Jul 15 09:12:03 2024 +0200
AVR: avr-md - Simplify GET_MODE and GET_MODE_BITSIZE.
gcc
This patch allows for more insn combine opportunities.
It extends some existing pattern to allow more patches
by iterators.
Johann
--
AVR: Allow more combinations of XOR / IOR with byte-shifts.
This patch takes some existing patterns that have QImode as one
input and uses a mode iterator to al
This is a mechanical patch that replaces a bunch of
similar insns with one insn with iterators.
Johann
--
AVR: Overhaul add and sub insns that extend one operand.
These are insns of the forms
(set (regA:M)
(plus:M (extend:M (regB:L))
(regA:M)))
and
(set (regA:M)
Applied as obvious.
Johann
--
AVR: testsuite - Add noipa function attribute to noclone functions.
Many functions under test have the noinline and noclone function
attributes attached so that no (constant) values are propagated
into the functions, so that we actually are testing what's supposed
Am 16.07.24 um 19:08 schrieb Jeff Law:
On 7/12/24 5:01 AM, Georg-Johann Lay wrote:
These are insns of the forms
(set (regA:M)
(plus:M (extend:M (regB:L))
(regA:M)))
and
(set (regA:M)
(minus:M (regA:M)
(extend:M (regB:L
where
Ping #1 for
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/656332.html
Address computation (usually add) with symbols that are aligned
to 256 bytes does not require to add the lo8() part as it is zero.
This patch adds a new combine insn that performs a widening add
from QImode plus such a
Am 17.07.24 um 16:36 schrieb Jeff Law:
On 7/17/24 3:45 AM, Georg-Johann Lay wrote:
Ping #1 for
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/656332.html
Address computation (usually add) with symbols that are aligned
to 256 bytes does not require to add the lo8() part as it is zero
Am 17.07.24 um 17:55 schrieb Jeff Law:
On 7/17/24 9:26 AM, Georg-Johann Lay wrote:
It looks fine for the trunk. Out of curiosity, does the avr port
implement linker relaxing for this case? That would seem to be
No. avr-ld performs relaxing, but only the two cases of
- JMP/CALL to RJMP
Am 17.07.24 um 19:51 schrieb Jeff Law:
On 7/17/24 11:13 AM, Georg-Johann Lay wrote:
Am 17.07.24 um 17:55 schrieb Jeff Law:
On 7/17/24 9:26 AM, Georg-Johann Lay wrote:
It looks fine for the trunk. Out of curiosity, does the avr port
implement linker relaxing for this case? That would seem to
This new builtin provides a faster way to compute
expressions like 1 << x or ~(1 << x) that are sometimes
used as masks for setting bits in the I/O region, and when
x is not known at compile-time.
The open coded C expression takes 5 + 4 * x cycles to compute an
8-bit result, whereas the builtin
Am 19.07.24 um 16:56 schrieb Jeff Law:
On 7/18/24 3:12 PM, Georg-Johann Lay wrote:
This new builtin provides a faster way to compute
expressions like 1 << x or ~(1 << x) that are sometimes
used as masks for setting bits in the I/O region, and when
x is not known at compile-tim
Applied as obvious,
Johann
--
Author: Wolfgang Hospital
Date: Sat May 18 15:02:51 2024 +0200
AVR: target/115065 - Tweak __clzhi2.
The libgcc implementation of __clzhi2 can be tweaked by
one cycle in some situations by re-arranging the instructions.
It also reduces the WCET
Applied this patch as proposed by Richard.
Johann
--
AVR: tree-optimization/115307 - Work around isinf bloat from early passes.
PR tree-optimization/115307
gcc/
* config/avr/avr.md (SFDF): New mode iterator.
(isinf2) [sf, df]: New expanders.
gcc/testsuite/
* gc
Applied as obvious.
Johann
--
AVR: Fix a typo in __builtin_avr_mask1 documentation.
gcc/
* doc/extend.texi (AVR Built-in Functions) : Fix a typo.
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 89fe5db7aed..ae1ada3cdf8 100644
--- a/gcc/doc/extend.texi
+++ b/g
Some post-inc address adjustments can be skipped when the
address register is unused after.
Johann
--
AVR: Improve POST_INC output in some rare cases.
gcc/
* config/avr/avr.cc (avr_insn_has_reg_unused_note_p): New function.
(_reg_unused_after): Use it to recognize more cases.
Applied this fix to trunk and v14 branch.
Johann
--
AVR: target/116295 - Fix unrecognizable insn with __flash read.
Some loads from non-generic address-spaces are performed by
libgcc calls, and they don't have a POST_INC form. Don't consider
such insns when running -mfuse-add.
PR tar
Applied the patchlet below.
Johann
--
AVR: Tidy up code for __[x]load insns.
gcc/
* config/avr/avr.md (*load__libgcc, *xload__libgcc):
Tidy up code.commit a90c74ab161eab09802920fbd894bf55bc4fa797
Author: Georg-Johann Lay
Date: Fri Aug 9 12:15:28 2024 +0200
AVR: Tidy up
Am 05.08.24 um 12:28 schrieb Stefan Schulze Frielinghaus:
This is a follow-up of
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/654013.html
Hi Stefan,
as an addition, maybe a built-in macro is useful that tells the target
code whether the feature is available.
Similar to __GXX_CONSTEXPR_
Applied this patch that makes it easier for the LRA maintainers
to reproduce LRA bugs that pop up for avr.
Johann
--
AVR: ad target/113934 - Add option -mlra to enable LRA.
PR target/113934
gcc/
* config/avr/avr.opt (-mlra): New target option.
* config/avr/avr.cc (avr_u
This patch sets the Undocumented flag for -mlra because
it is likely just a transient option and only experimental.
Johann
--
AVR: -mlra is not documeted in TEXI.
gcc/
* config/avr/avr.opt (mlra): Set Undocumented flag.
diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/
This patch adds function avr.cc::ra_in_progress() that returns
lra_in_progress resp. reload_in_progress depending on avr_lra_p.
Currently, direct use of ra_in_progress() is only made with -mlog=.
Johann
--
AVR: Add function avr.cc::ra_in_progress().
It returns lra_in_progress resp. re
This fixes an unrecognizable insn ICE when alignments >= 128
were passed from setmemhi to clrmemqi*. Alignment is unused,
hence set it to 0 so that the patterns match for big alignments.
Johann
---
AVR: target/85624 - Fix non-matching alignment in clrmem* insns.
The clrmem* patterns don't use
Am 13.08.24 um 10:59 schrieb Mark Wielaard:
avr added an -mlra option, but the avr.opt.url file wasn't
regenerated.
Note that commit 149a23ee2568 ("AVR: -mlra is not documeted in TEXI.")
did add the Undocumented flag, but that still needs the avr.op.urls
file to be updated.
Fixes: 09a87ea666b2
This fixes an ICE due to some typos in avr_out_movsi_mr_r_reg_disp_tiny
that didn't use operands[1] when it was required.
Johann
--
AVR: target/116390 - Fix an avrtiny asm out template.
PR target/116390
gcc/
* config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix
ou
Am 17.08.24 um 15:43 schrieb Gerald Pfeifer:
All this patch does (modulo reformatting) is put SEI in a
environment.
However, looking at this I've got a question: How about "imposing a
function name" which is listed as a difference of noblock
versus others? This (the specific name) is not actual
This fixes "relocation truncated to fit" errors from
the linker due to bogus (too small) jump offsets.
Johann
--AVR: target/116407 - Fix linker error "relocation truncated to fit".
Some text peepholes output extra instructions prior to a branch
instruction and that increase the
The 16-bit additions like addhi3 have two forms: One with a scratch:QI
and one without, where the latter is required because reload cannot
deal with a scratch when spill code pops a 16-bit addition.
Passes like combine and fwprop1 may come up with the non-scratch version,
which is sub-optimal in
Ping for the patch to male better use of SREG and some
code clean-ups for trunk, no new regressions.
https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659422.html
Johann
--
AVR: target/115830 - Make better use of SREG.N and SREG.Z.
This patch adds new CC modes CCN and CCZN for operations
Am 15.08.24 um 10:45 schrieb Richard Sandiford:
When it removes a definition, late-combine tries to update all
uses in notes. It does this using the same insn_propagation class
that it uses for patterns.
However, insn_propagation uses validate_change, which in turn
resets the INSN_CODE. This i
Am 16.07.24 um 16:34 schrieb Richard Sandiford:
order_nodes are used to implement ordered comparisons between
two insns with the same program point number. remove_insn would
remove an order_node from its splay tree, but didn't remove it
from the insn. This caused confusion if the insn was la
This patch overhauls the avr-ifelse mini-pass that optimizes
two cbranch insns to one comparison and two branches.
More optimization opportunities are realized, and the code
has been refactored.
No new regressions. Ok for trunk?
There is currently no avr maintainer, so some global reviewer
mig
Am 23.08.24 um 17:45 schrieb Richard Biener:
Am 23.08.2024 um 16:49 schrieb Jeff Law :
On 8/23/24 6:02 AM, Georg-Johann Lay wrote:
Hi, this fails on machines that don't support scheduling:
cc1: warning: instruction scheduling not supported on this target machine
FAIL: gcc.dg/torture/pr116
Am 23.08.24 um 17:47 schrieb Jeff Law:
On 8/23/24 9:45 AM, Richard Biener wrote:
Am 23.08.2024 um 16:49 schrieb Jeff Law :
On 8/23/24 6:02 AM, Georg-Johann Lay wrote:
Hi, this fails on machines that don't support scheduling:
cc1: warning: instruction scheduling not supported on this t
Am 25.08.24 um 18:15 schrieb Denis Chertykov:
Starting to review the patch...
Denis
Great to see you back!
Prior to commenting on the attached new versions of
the overhaul, let me answer Jeff's questions from the
other mail:
On 8/23/24 6:16 AM, Georg-Johann Lay wrote:
This patch over
Am 27.08.24 um 17:28 schrieb Jeff Law:
On 8/26/24 1:15 PM, Georg-Johann Lay wrote:
What the avr-ifelse pass does is try to replace 2 cbranch insns with
one compare insn and two branches. It runs after reload and just prior
to .split2 (split_after_reload). It must run after reload because
Ping #2 for the patch to make better use of SREG, and some
code clean-ups for trunk. No new regressions.
#0 https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659422.html
#1 https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660743.html
Johann
--
AVR: target/115830 - Make better use of
Am 29.08.24 um 12:18 schrieb Denis Chertykov:
чт, 29 авг. 2024 г. в 12:42, Georg-Johann Lay :
Ping #2 for the patch to make better use of SREG, and some
code clean-ups for trunk. No new regressions.
#0 https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659422.html
#1 https
The convention in round-to-nearest floating-point
rounding is to round to even ("Banker's rounding").
Johann
AVR: target/115419 - Tie breaks are rounded-to-even.
libgcc/config/avr/libf7/
PR target/115419
* libf7.c (f7_get_double): Round tie breaks to even LSB.
diff --git a/lib
Am 14.06.24 um 21:11 schrieb Detlef Vollmann:
I actually plan anyway to run a test with the built libstdc++ on simulavr.
Detlef
As an aside, simulavr tries to simulate an exact match of the hardware
including internal I/O like timers, IRQs, etc.
For GCC regression testing, no internal I/O
Applied this one:
backends.html - Update weblinks to AVR simulators.
diff --git a/htdocs/backends.html b/htdocs/backends.html
index bdaf29ad..1f7c85d7 100644
--- a/htdocs/backends.html
+++ b/htdocs/backends.html
@@ -120,9 +120,19 @@ visium | B g t s
xtensa | C
Am 18.06.24 um 00:06 schrieb Gerald Pfeifer:
On Sat, 15 Jun 2024, Georg-Johann Lay wrote:
Applied this one:
Cool.
+SimulAVR at https://www.nongnu.org/simulavr";
This one gives a http response of "301 Moved Permanently" redirecting to
https://www.nongnu.org/simulavr/
Added the following hint on testing for target avr.
Johann
--
diff --git a/htdocs/simtest-howto.html b/htdocs/simtest-howto.html
index 3afbdb0b..ea69c9ed 100644
--- a/htdocs/simtest-howto.html
+++ b/htdocs/simtest-howto.html
@@ -304,5 +304,22 @@ to exercise the just-built gcc on every test-sui
cc0 has been removed long ago, removed mentions.
Johann
diff --git a/htdocs/simtest-howto.html b/htdocs/simtest-howto.html
index ea69c9ed..f18a78f6 100644
--- a/htdocs/simtest-howto.html
+++ b/htdocs/simtest-howto.html
@@ -164,13 +164,7 @@ to exercise the just-built gcc on every test-suite
in t
Am 22.06.24 um 00:00 schrieb Jeff Law:
More minor fallout from the IOR->PLUS change a little while ago. This
time on xstormy16.
The pattern to swap nibbles actually tries to handle all the cases of
IOR, XOR and PLUS. But when we generate PLUS earlier in the pipeline,
the simplifications/
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