On Sun, Oct 11, 2015 at 9:07 AM, Alan Modra wrote:
> On Sat, Oct 10, 2015 at 11:25:38PM +0200, Andreas Schwab wrote:
>> "Lynn A. Boger" writes:
>>
>> > Index: gcc/config/rs6000/sysv4.h
>> > ===
>> > --- gcc/config/rs6000/sysv4.h
On Thu, Oct 15, 2015 at 1:50 PM, Szabolcs Nagy wrote:
> A powerpc toolchain built with (or without) --enable-secureplt
> currently creates a binary that uses bss plt if
>
> (1) any of the linked PIC objects have bss plt relocs
> (2) or all the linked objects are non-PIC or have no relocs,
>
> beca
Pierre,
Did this revised patch address the comments about MIR from Kenny?
- David
On Tue, Oct 20, 2015 at 3:38 PM, Szabolcs Nagy wrote:
> On 20/10/15 06:16, Alan Modra wrote:
>>
>> On Mon, Oct 19, 2015 at 08:10:32PM +0100, Szabolcs Nagy wrote:
>>>
>>> On 19/10/15 14:04, Szabolcs Nagy wrote:
On 19/10/15 12:12, Alan Modra wrote:
>
> On Thu, Oct 15, 2015 at 06:50
> 2015-10-16 Gregor Richards
> Szabolcs Nagy
>
> * config/rs6000/linux64.h (MUSL_DYNAMIC_LINKER32): Define.
> (MUSL_DYNAMIC_LINKER64): Define.
> (GNU_USER_DYNAMIC_LINKER32): Update.
> (GNU_USER_DYNAMIC_LINKER64): Update.
> (CHOOSE_DYNAMIC_LINKER): Update.
>
>
2015-10-16 Gregor Richards
Szabolcs Nagy
* config.gcc (enable_secureplt): Add *-linux*-musl*.
Okay.
Thanks, David
P.S. Please explicitly copy me on rs6000 patches.
cxa_atexit functionality for AIX was added to libgcc a while ago. It
seems stable in all of the testing. This patch enables it by default.
Bootstrapped on powerpc-ibm-aix7.1.0.0, powerpc-ibm-aix7.1.2.0,
powerpc-ibm-aix7.1.3.0
Thanks, David
* config.gcc (powerpc-ibm-aix[6789])[default_use_cxa_a
On Sun, Oct 25, 2015 at 8:59 PM, Segher Boessenkool
wrote:
> For 32-bit targets p8vector_ok does not imply we have int128.
>
> Tested with -m32,-m32/-mpowerpc64,-m64; okay for trunk?
>
>
> Segher
>
>
> 2015-10-26 Segher Boessenkool
>
> gcc/testsuite/
> * gcc.target/powerpc/p8vector-buil
On Sun, Oct 25, 2015 at 8:59 PM, Segher Boessenkool
wrote:
> The patterns involved can create vmadd resp. vnmsub instructions instead.
> This patch changes the testcases to allow those.
>
> Tested with -m32,-m32/-mpowerpc64,-m64; okay for trunk?
>
>
> Segher
>
>
> 2015-10-26 Segher Boessenkool
On Fri, Oct 23, 2015 at 1:26 PM, Michael Meissner
wrote:
> This patch is the rs6000.h changes. It makes the IEEE 128-bit floating point
> type that can go in vector registers a 'vector' type, so that the address code
> in rs6000.c that determines whether to use VSX addressing works. In addition,
On Fri, Oct 23, 2015 at 1:36 PM, Michael Meissner
wrote:
> This patch allows SUBREG's for the reg_or_indexed_operand, which is used when
> you have an integral value in a float/vector register, and you want to move
> the
> value (either via direct move on power8, or via store).
>
> I have built t
On Fri, Oct 23, 2015 at 1:30 PM, Michael Meissner
wrote:
> This patch changes the switch from -mfloat128-software and -mfloat128-none to
> be a binary switch, -mfloat128 and -mno-float128. It also provides some of
> the
> basic setup for IEEE types. It also removes code I had put in a previous
On Fri, Oct 23, 2015 at 1:39 PM, Michael Meissner
wrote:
> This patch prevents the compiler from calling the IEEE 128-bit emulation
> functions with the vector value in both GPRs and vector registers due to the
> fact that the library function did not have a prototype.
>
> I have built the compile
On Fri, Oct 23, 2015 at 1:33 PM, Michael Meissner
wrote:
> This patch defines 3 macros to tell the user whether -mfloat128 is enabled or
> not, and whether long double is IBM extended double or IEEE 128-bit floating
> point.
>
> I have built the compiler with this patch and the previous subpatches
On Fri, Oct 23, 2015 at 1:40 PM, Michael Meissner
wrote:
> This patch sets up all of the emulation functions.
>
> I have built the compiler with this patch and the previous subpatches (1-4).
> I
> have bootstrapped the compiler with all 16 subpatches installed, and there
> were
> no regressions
On Fri, Oct 23, 2015 at 1:45 PM, Michael Meissner
wrote:
> This patch adds support for using 'q' or 'Q' as a suffix for __float128
> constants, which is compatible with the existing x86_64 implmenetation of
> their
> __float128 support.
>
> I have built the compiler with this patch and the previo
On Fri, Oct 23, 2015 at 1:49 PM, Michael Meissner
wrote:
> This patch is part of the support needed to properly swap IEEE 128-bit
> floating
> point on little endian systems. Note, you will need the rs6000.md changes for
> this to become effective.
>
> I have built the compiler with this patch a
On Fri, Oct 23, 2015 at 1:47 PM, Michael Meissner
wrote:
> This patch is the new patch from the last submission. It sets up a hook so
> that
> the compiler will not allow IBM extended double and IEEE 128-bit floating
> point
> to intermix in a binary expression without using an explicit conversi
On Fri, Oct 23, 2015 at 1:43 PM, Michael Meissner
wrote:
> This patch updates to use the unordered comparison function for IEEE 128-bit
> floating point to mimic the behaviour of SFmode/DFmode using the fcmpu
> instruction.
>
> It also restructures the code to allow a future change to drop in easi
On Fri, Oct 23, 2015 at 1:52 PM, Michael Meissner
wrote:
> This patch changes the mangling for __float128. I came to the conclusion that
> the current code is so tangled, that it would be better to use U10__float128
> rather than "e". However, if it is felt that we should go with "e", I can go
>
On Fri, Oct 23, 2015 at 1:57 PM, Michael Meissner
wrote:
> This patch is the first of two rs6000.md patches to straighten out the IFmode,
> KFmode, and TFmode support. Part of the change is to change the iterator
> names
> to be easier to understand, using IEEE128, IBM128, and FLOAT128 as the
>
On Fri, Oct 23, 2015 at 1:58 PM, Michael Meissner
wrote:
> This patch is the second part to allow TFmode to be IBM extended double or
> IEEE
> 128-bit floating point depending on switches.
>
> I have built the compiler with this patch and the previous subpatches (1-12).
> I have bootstrapped the
On Fri, Oct 23, 2015 at 2:00 PM, Michael Meissner
wrote:
> This patch makes TFmode be fully switchable for comparisons.
>
> I have built the compiler with this patch and the previous subpatches (1-13).
> I have bootstrapped the compiler with all 16 subpatches installed, and there
> were no regress
On Fri, Oct 23, 2015 at 2:01 PM, Michael Meissner
wrote:
> This patch adds the documentation.
>
> I have built the compiler with this patch and the previous subpatches (1-14).
> I have bootstrapped the compiler with all 16 subpatches installed, and there
> were no regressions. Is it ok to install
On Fri, Oct 23, 2015 at 2:03 PM, Michael Meissner
wrote:
> This patch adds a test to make sure __float128 are passed and returned like
> vector objects, and not as IBM extended double did.
>
> This is the last subpatch of patch #7. I have bootstrapped the compiler with
> all 16 subpatches install
On Thu, Oct 29, 2015 at 12:52 PM, Segher Boessenkool
wrote:
> The PIC reg (r30) needs to be saved whenever the prologue sets it up,
> not just if it is used elsewhere in the function. Without this patch
> the prologue for such a function will modify r30 without saving it
> first, leading to disas
On Sat, Oct 31, 2015 at 1:39 PM, Segher Boessenkool
wrote:
> This one for TARGET_TOC && TARGET_MINIMAL_TOC. Without it, r30 is not
> saved in the prologue for functions that do not use r30, but the register
> is set later in the prologue anyhow. This made all java tests fail.
>
> Tested on power
On Sat, Oct 31, 2015 at 1:39 PM, Segher Boessenkool
wrote:
> This function is quite a puzzle; untangle it. No functional change.
>
> Tested etc.; okay for trunk?
>
>
> Segher
>
>
> 2015-10-31 Segher Boessenkool
>
> * config/rs6000/rs6000.c (rs6000_reg_live_or_pic_offset_p): Rewrite.
O
TLS symbols in AIX display a new, different symbol type in nm output.
Libtool explicitly creates a list of exported symbols for shared
libraries using nm and does not recognize the new TLS symbols, so
those symbols are not exported.
This is a regression for TLS support on AIX.
This patch updates
On Tue, Nov 3, 2015 at 9:47 AM, Richard Biener
wrote:
> On Tue, Nov 3, 2015 at 3:23 PM, David Edelsohn wrote:
>> TLS symbols in AIX display a new, different symbol type in nm output.
>> Libtool explicitly creates a list of exported symbols for shared
>> libraries using nm a
On Tue, Oct 27, 2015 at 12:44 PM, Michael Meissner
wrote:
> This patch adds a test to make sure __float128 and __ibm128 are not allowed to
> be combined in binary operations. I re-ran the test suite on power8 little
> endian, and this test passed. Once the preceeding 16 patches are applied to
>
[Explicitly copying build maintainers.]
Paolo and Alexandre,
Could you review and help with this patch?
TLS symbols in AIX display a new, different symbol type in nm output.
Libtool explicitly creates a list of exported symbols for shared
libraries using nm and does not recognize the new TLS sym
On Thu, Nov 5, 2015 at 8:34 AM, Paolo Bonzini wrote:
>
>
> On 05/11/2015 17:28, David Edelsohn wrote:
>> [Explicitly copying build maintainers.]
>>
>> Paolo and Alexandre,
>>
>> Could you review and help with this patch?
>>
>> TLS symbols in AI
wrote:
> On November 5, 2015 5:38:45 PM GMT+01:00, David Edelsohn
> wrote:
>>On Thu, Nov 5, 2015 at 8:34 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 05/11/2015 17:28, David Edelsohn wrote:
>>>> [Explicitly copying build maintainers.]
>>>>
This patch broke bootstrap on AIX.
/nasfarm/edelsohn/src/src/libstdc++-v3/src/c++98/ios_init.cc: In
static member function 'static bool
std::ios_base::sync_with_stdio(bool)':
/nasfarm/edelsohn/src/src/libstdc++-v3/src/c++98/ios_init.cc:181:59:
internal compiler error: in tree_to_shwi, at tree.c:7
Sorry for the incorrect blame. I thought the failure was due to GOMP
changes, but it appears to be due to the placement new size changes.
I am re-testing after Martin's fix.
By the way, Martin, the ChangeLog entry is wrong
2015-11-05 Martin Sebor
PR c++/67942
* invoke.texi (-
2015-11-06 Arnout Vandecappelle
* gcc/config.gcc: fix typo for powerpc e6500 cpu_is_64bit
For GCC, please don't send ChangeLog entries as diffs.
Applied. Thanks.
- David
IBM xlC++ compiler provides its own implementation of atexit() to
provide correct interaction between atexit() and destructors. GCC
needs to provide the same through libgcc.
I previously added partial support based on the implementation in
GLIBC (copied with FSF permission) and confirmed that des
On Sun, Nov 8, 2015 at 4:33 PM, Michael Meissner
wrote:
> This is patch #1 that I revised. I changed -mfusion-toc to -mtoc-fusion. I
> changed the references to ISA 2.08 to 3.0. I added two new debug switches for
> code in future patches that in undergoing development and is not ready to be
>
On Sun, Nov 8, 2015 at 4:36 PM, Michael Meissner
wrote:
> This is patch #2. It adds support for the new modulus instructions that are
> being added in ISA 3.0 (power9):
>
> I have built this patch (along with patches #3 and #4) with a bootstrap build
> on a power8 little endian system. There wer
On Sun, Nov 8, 2015 at 11:33 PM, Segher Boessenkool
wrote:
> The testcase used to fail on 64-bit, but it was disabled there.
> This patch makes it run there, and beefs up the checking of the
> generated code a bit.
>
> Tested on powerpc64-linux *-m32,-m32/-mpowerpc64,-m64).
> Is this okay for trun
On Mon, Nov 9, 2015 at 8:30 AM, Richard Sandiford
wrote:
> After the previous patches it's no longer necessary for
> TARGET_BUILTIN_VECTORIZED_FUNCTION to return functions that
> map to the vector optab of the original operation. We'll use
> a vector form of the internal function instead.
>
>
> g
On Sun, Nov 8, 2015 at 4:37 PM, Michael Meissner
wrote:
> This patch adds support for scalar count trailing zeros instruction that is
> being added to ISA 3.0 (power9).
>
> I have built this patch (along with patches #2 and #4) with a bootstrap build
> on a power8 little endian system. There were
On Sun, Nov 8, 2015 at 4:39 PM, Michael Meissner
wrote:
> This patch adds support for the EXTSWSLI instruction that is being added to
> PowerPC ISA 3.0 (power9).
>
> I have built this patch (along with patches #2 and #3) with a bootstrap build
> on a power8 little endian system. There were no reg
On Sun, Nov 8, 2015 at 4:42 PM, Michael Meissner
wrote:
> This patch adds support for new fusion forms in ISA 3.0 (power9). In
> particular, ISA 3.0 can fuse GPR loads of R0, FPR loads, GPR stores, FPR
> stores, and some constant generation that ISA 2.07 (power8) could not
> generate.
>
> I have
On Mon, Nov 9, 2015 at 11:57 AM, Segher Boessenkool
wrote:
> On Mon, Nov 09, 2015 at 12:34:20PM -0500, Michael Meissner wrote:
>> > > +(define_insn "*toc_fusionload_"
>> > > + [(set (match_operand:QHSI 0 "int_reg_operand" "=&b,??r")
>> > > + (match_operand:QHSI 1 "toc_fusion_mem_wrapped" "wG,wG")
On Mon, Nov 9, 2015 at 2:17 PM, Michael Meissner
wrote:
> On Mon, Nov 09, 2015 at 01:11:41PM -0800, David Edelsohn wrote:
>> On Mon, Nov 9, 2015 at 11:57 AM, Segher Boessenkool
>> wrote:
>> > On Mon, Nov 09, 2015 at 12:34:20PM -0500, Michael Meissner wrote:
This patch adds some asserts of cpu and machine to fix an assert
testcase and makes the defines consistent with PPC64 Linux.
boottrapped on powerpc-ibm-aix7.1.0.0
* config/rs6000/aix.h (TARGET_OS_AIX_CPP_BUILTINS): Add cpu and
machine asserts. Update defines for 64 bit.
Thanks, David
Index: ai
Nathan,
The ChangeLog was placed in the wrong files.
gcc/
* gimplify.c (oacc_default_clause): New.
(omp_notice_variable): Call it.
Should go in gcc/ChangeLog without "gcc/"
gcc/testsuite/
* c-c++-common/goacc/data-default-1.c: New.
should go in gcc/tests
On Tue, Nov 10, 2015 at 1:39 PM, Michael Meissner
wrote:
> This patch adds support for the MADDLD instruciton, which is a fused
> multiply/add instruction for integers. At this time, it is for 64-bit
> multiplies only. Eventually, we will restructure 128-bit multiply so that we
> can use the 64x
On Sun, Nov 8, 2015 at 7:48 PM, Michael Meissner
wrote:
> This patch adds support for the new direct move instructions (MFVSRLD and
> MTVSRDD) that simplify moving 128-bit data between GPRs and vector registers.
>
> I have built previous versions of this patch with no regressions. At the
> moment
On Sun, Nov 8, 2015 at 7:44 PM, Michael Meissner
wrote:
> This patch adds support for the IEEE 128-bit hardware instructions that are
> being added to the PowerPC ISA 3.0 (power9). With this patch, users on power7
> and power8 will use the software emulation functions that are committed, but
> st
On Thu, Nov 12, 2015 at 4:51 PM, Eric Botcazou wrote:
> Hi,
>
> this patch rotates the loop generated in the prologue to do stack checking
> when -fstack-check is specified, thereby saving one branch instruction. It
> was initially implemented as a WHILE loop to match the generic implementation
>
http://www.cplusplus.com/reference/string/basic_string/reserve/
"Note that the resulting string capacity may be equal or greater than n."
The current testcase verifies that the capacity is exactly equal to
the length of the string or reserve value, but the standard allows the
capacity to be large
On Fri, Nov 13, 2015 at 1:40 PM, David Edelsohn wrote:
> http://www.cplusplus.com/reference/string/basic_string/reserve/
>
> "Note that the resulting string capacity may be equal or greater than n."
>
> The current testcase verifies that the capacity is exactly equal to
&
No RISC architecture can store directly to MEM, so the expected RTL in
g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This
probably should be disabled for ARM and other RISC architectures.
Dollar sign is not a valid identifier on AIX, so g++.dg/cpp/ucn-1.C
will produce an addition
This seems to have broken bootstrap on PowerPC. I originally saw it
on AIX, but duplicated it on PPC64LE Linux.
The failure is genoutput seems to be miscompiled by stage1 and
produces error messages implying that it did not parse rs6000/vsx.md
correctly. I don't know if the miscompilation is gen
On Sat, Nov 14, 2015 at 5:16 AM, Andreas Schwab wrote:
> David Edelsohn writes:
>
>> + int c\u0024c;// { dg-error "not valid in an identifier" {
>> target { powerpc-ibm-aix* } } }
>
> FAIL: g++.dg/cpp/ucn-1.C -std=gnu++11 target { powerpc-ibm-ai
The copy_ctor_neg testcase fails on AIX.
/nasfarm/edelsohn/src/src/libstdc++-v3/testsuite/experimental/memory/shared_ptr/cons/copy_ctor_neg.cc:
In function 'void test02()':
/nasfarm/edelsohn/src/src/libstdc++-v3/testsuite/experimental/memory/shared_ptr/cons/copy_ctor_neg.cc:50:44:
error: no matchi
On Sat, Nov 14, 2015 at 8:30 AM, Jakub Jelinek wrote:
> On Sat, Nov 14, 2015 at 08:09:44AM -0500, David Edelsohn wrote:
>> On Sat, Nov 14, 2015 at 5:16 AM, Andreas Schwab
>> wrote:
>> > David Edelsohn writes:
>> >
>> >> + int c\u0024c;
On Sat, Nov 14, 2015 at 8:41 AM, Andreas Schwab wrote:
> David Edelsohn writes:
>
>> On Sat, Nov 14, 2015 at 5:16 AM, Andreas Schwab
>> wrote:
>>> David Edelsohn writes:
>>>
>>>> + int c\u0024c;// { dg-error "not va
Testcases that use TLS need additional options on some targets
(normall -pthread). This fixes the testcase on AIX and Solaris.
Committed as obvious.
* testsuite/experimental/random/randint.cc: Add dg-add-options tls.
Index: testsuite/experimental/random/randint.cc
==
This patch causes numerous new testsuite failure on AIX caused by the
compiler crashing during compilation, e.g.
gcc.c-torture/execute/20020206-1.c
in GCC libcpp
991 linemap_assert (line >= LINEMAPS_MACRO_LOWEST_LOCATION (set));
(gdb) where
#0 _Z11fancy_abortPKciS0_ (
file=0x11296dc0
On Thu, Nov 5, 2015 at 10:53 PM, Alexandre Oliva wrote:
> On Nov 5, 2015, Paolo Bonzini wrote:
>
>> On 05/11/2015 17:28, David Edelsohn wrote:
>>> [Explicitly copying build maintainers.]
>>>
>>> Paolo and Alexandre,
>>>
>>> Could you re
On Mon, Nov 16, 2015 at 4:15 AM, Eric Botcazou wrote:
>> No RISC architecture can store directly to MEM, so the expected RTL in
>> g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This
>> probably should be disabled for ARM and other RISC architectures.
>
> Some of them can store 0
1/13/2015 11:46 PM, David Edelsohn wrote:
>>
>> This seems to have broken bootstrap on PowerPC. I originally saw it
>> on AIX, but duplicated it on PPC64LE Linux.
>
>
> Was this a clean build? The gtfiles change doesn't propagate to the
> Makefile unless config.status is regenerated.
>
> Jason
>
On Mon, Nov 16, 2015 at 10:47 PM, Jason Merrill wrote:
> On 11/16/2015 09:39 PM, David Edelsohn wrote:
>>
>> The PPC port seems to be bootstrapping again, but I'm not sure why.
>> Mike Meissner's patch only should have affected long double.
>
>
>> It&#
The testcase in the GCC testsuite assumes that wchar_t is 32 bits,
which is not correct on AIX. 32 bit AIX maintains 16 bit wchar_t for
backward compatibility (64 bit AIX uses 32 bit wchar_t).
What is the preferred method to make the testcase safe for smaller wchar_t?
The following patch works f
Kirill,
* c-c++-common/attr-simd.c
and
* c-c++-common/attr-simd-3.c
fail on 32 bit systems, e.g., see powerpc64-linux tested in 32 bit mode.
- David
On Tue, Nov 17, 2015 at 11:22 AM, Jonathan Wakely wrote:
> On 17 November 2015 at 16:04, David Edelsohn wrote:
>> The testcase in the GCC testsuite assumes that wchar_t is 32 bits,
>> which is not correct on AIX. 32 bit AIX maintains 16 bit wchar_t for
>> backward compatibi
Richard,
One of the patches in your recent series caused bootstrap failure on PPC:
In file included from /nasfarm/edelsohn/src/src/libgcc/libgcov-driver.c:49:0:
/nasfarm/edelsohn/src/src/libgcc/../gcc/gcov-io.c: In function 'gcov_do_dump':
/nasfarm/edelsohn/src/src/libgcc/../gcc/gcov-io.c:731:51:
On Tue, Nov 17, 2015 at 9:32 PM, Alan Modra wrote:
> On Tue, Nov 17, 2015 at 07:53:18PM -0500, Michael Meissner wrote:
>> Here is the temporary patch I'm using to get past rs6000.c. But I suspect
>> the
>> TOC alignment should never be 256.
>
> Yes, it should be. Recent GNU ld aligns .TOC. to a
On Wed, Nov 18, 2015 at 11:26 PM, Jason Merrill wrote:
> The rs6000 target was hitting a bootstrap failure due to
> -Werror=type-limits. Since warn_tautological_cmp and other warnings avoid
> warning if one of the operands comes from a macro, I thought it would make
> sense to do that here as wel
This patch broke bootstrap when ISL is not enabled.
graphite-isl-ast-to-gimple.c is protected by HAVE_isl but
get_false_edge_from_guard_bb() is used outside of Graphite, including
sese.c, which is not restricted to HAVE_isl.
Please fix.
Thanks, David
The patch fixed the bootstrap failure.
Thanks, David
On Thu, Nov 19, 2015 at 3:37 PM, Sebastian Pop wrote:
> Fixed in r230625.
>
> David, please test on your systems, we were not able to reproduce the fails on
> x86_64-linux: the linker does optimize away the functions that are not used.
>
> Tha
On Fri, Nov 20, 2015 at 7:53 AM, Richard Biener wrote:
>
> Status
> ==
>
> We plan to do a GCC 5.3 release candidate at the end of next week
> followed by the actual release a week after that.
>
> So now is the time to look at your regression bugs in bugzilla and
> do some backporting for thin
The testcase allocates so much memory that it requires an additional
option to enabled higher memory limit on AIX.
Bootstrapped on powerpc-ibm-aix7.1.0.0
Thanks, David
* testsuite/23_containers/vector/profile/vector.cc: Add maxdata option on AIX.
Index: 23_containers/vector/profile/vector.cc
==
On Fri, Nov 20, 2015 at 6:47 PM, Michael Meissner
wrote:
> On Fri, Oct 02, 2015 at 02:04:48PM -0500, Peter Bergner wrote:
>> PR67808 exposes a problem with the constraints in the *extenddftf2_internal
>> pattern, in that it allows TFmode operands to occupy Altivec registers
>> which they are not a
On Tue, Nov 17, 2015 at 3:12 PM, David Malcolm wrote:
> On Tue, 2015-11-17 at 16:24 +0100, Bernd Schmidt wrote:
>> On 11/17/2015 04:13 PM, David Malcolm wrote:
>> > On Mon, 2015-11-16 at 22:34 +0100, Bernd Schmidt wrote:
>> >>
>> >> Should c_expr perhaps acquire a constructor so that this problem
On Sat, Nov 21, 2015 at 3:00 PM, David Malcolm wrote:
> On Sat, 2015-11-21 at 13:54 -0500, David Edelsohn wrote:
>> On Tue, Nov 17, 2015 at 3:12 PM, David Malcolm wrote:
>> > On Tue, 2015-11-17 at 16:24 +0100, Bernd Schmidt wrote:
>> >> On 11/17/2015 04:13 PM, David
Graphite relies on the ISL library and includes multiple ISL headers.
The ISL headers refer to identifiers that are poisoned for use in GCC.
The source files for Graphite were organized to include the ISL
headers first, to avoid the identifier poisoning, which breaks some
platforms because GCC head
PowerPC was missing a definition of the lroundMN pattern, which can be
implemented with VSX instructions available in Power7. Below is a
first draft.
- David
* config/rs6000/rs6000.md (*xsrdpidf2): New define_insn.
(lrounddfdi2): New define_expand.
diff --git a/gcc/config/rs6000/rs6000.md b/gc
On Sun, Nov 22, 2015 at 2:34 AM, Richard Biener
wrote:
> On November 22, 2015 2:52:53 AM GMT+01:00, David Edelsohn
> wrote:
>>PowerPC was missing a definition of the lroundMN pattern, which can be
>>implemented with VSX instructions available in Power7. Below is a
>>fi
v2 of the patch. Seems to pass the GCC testsuite, although the
testsuite doesn't stress FP.
There is something wrong with current VSX SFmode constraints.
Index: rs6000.md
===
--- rs6000.md (revision 230723)
+++ rs6000.md (working co
ndian power7 with a segmentation
> violation that I need to look into. I'm also building on a little endian
> power8 right now, and it has gotten further.
>
> 2015-11-23 David Edelsohn
> Michael Meissner
>
> * config/rs6000/rs6000.md (UNSPEC_XSRD
On Tue, Nov 24, 2015 at 2:13 AM, Segher Boessenkool
wrote:
> Calling rs6000_is_valid_and_mask on a reg instead of on a const_int is
> not a good idea, as PR68332 and PR67677 as well as testing with
> --enable-checking=yes,rtl show. Fix this.
>
> Bootstrapped and tested on powerpc64-linux. Is thi
On Sun, Nov 22, 2015 at 8:38 AM, Paolo Bonzini wrote:
>
>
> On 20/11/2015 14:14, David Edelsohn wrote:
>> On Fri, Nov 20, 2015 at 7:53 AM, Richard Biener wrote:
>>>
>>> Status
>>> ==
>>>
>>> We plan to do a GCC 5.3 release candidat
On Tue, Nov 10, 2015 at 4:56 PM, Michael Meissner
wrote:
> This patch d-form addressing to float/double scalars for the PowerPC that was
> added in ISA 3.0 (power9). This patch does not yet turn on D-form addressing
> as default. It is likely that patch #11, which will add limited d-form
> addre
On Tue, Nov 24, 2015 at 1:55 PM, Michael Meissner
wrote:
> Whoops, I forgot to update the ChangeLog after reversing Fv and Fv2.
>
> 2015-11-24 David Edelsohn
> Michael Meissner
>
> * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
> (Fv2
The initial rs6000_declare_alais support fort handle AIX function
descriptors was no complete. For function descriptors, both the
undecorated symbols (the function descriptor) and the "dot" symbol
(the function entry point address) must be globalized and renamed.
Thanks, David
* config/rs6000/rs
On Wed, Nov 25, 2015 at 11:57 AM, Paolo Bonzini wrote:
> Patch committed to upstream libtool, thanks for your understanding.
Great!
How can I have the patch backported to GCC trunk and 5-branch libtool,
and then rebuild configure with the appropriate versions of autoconf?
I have not been able t
On Fri, Nov 27, 2015 at 11:24 AM, Thomas Schwinge
wrote:
> Hi!
>
> On Tue, 24 Nov 2015 10:32:12 +, Alan Lawrence
> wrote:
>> I note doc/install.texi says that gcc uses "ISL Library version 0.15,
>> 0.14, 0.13, or 0.12.2". This patch breaks the build with 0.12.2 (a
>> subset of errors below)
When rs6000_adjust_cost originally was written, the return value from
recog_memoized() was handled incorrectly.
Note this also is wrong on PA and one of the SPARC adjust_cost macros.
Bootstrapped on powrepc-ibm-aix7.1.0.0.
PR target/28115
* config/rs6000/rs6000.c (rs6000_adjust_cost): Correct re
On Mon, Nov 30, 2015 at 4:44 AM, Eric Botcazou wrote:
>> Note this also is wrong on PA and one of the SPARC adjust_cost macros.
>
> Thanks for the heads up, fixed thusly, applied on the mainline
>
>
> PR target/28115
> * config/sparc/sparc.c (supersparc_adjust_cost): Fix thinko.
>
On Wed, 28 Oct 2015 at 18:14 PM, H.J. Lu wrote:
> On Wed, Oct 28, 2015 at 6:11 PM, Bernd Schmidt wrote:
>> On 10/29/2015 02:10 AM, H.J. Lu wrote:
>>>
>>> On Wed, Oct 28, 2015 at 5:23 PM, Jeff Law wrote:
So I'll ask again, why did you commit a patch which you clearly knew did
n
> Uli Weigand discovered that the gcc.target/powerpc/swaps-p8-21.c test
case fails when large and small code models are used, rather than the
default medium code model. This is because analyze_swaps is determining
whether the mask used for a vperm insn is loaded from the constant pool,
and there i
On Tue, Dec 1, 2015 at 8:55 PM, Segher Boessenkool
wrote:
> On 64-bit we can do comparisons of 32-bit values by extending those
> values to 64-bit, subtracting them, and then getting the high bit of
> the result. For registers this is always cheaper than using the carry
> bit sequence; and if the
On Wed, Dec 2, 2015 at 2:44 PM, Ulrich Weigand wrote:
> Hello,
>
> this patch fixes support for the large code model with the ELFv2 ABI.
>
> The global entry point prologue currently assumes that the TOC associated
> with a function is less than 2GB away from the function entry point. This
> is a
On Fri, Dec 4, 2015 at 9:34 AM, Segher Boessenkool
wrote:
> "register_operand" was a bit confusing. Also some other minor cleanups.
>
> Tested on powerpc64-linux; okay for mainline?
>
>
> Segher
>
>
> 2015-12-04 Segher Boessenkool
>
> * (cstore4_unsigned): Use gpc_reg_operand instead o
On Fri, Dec 4, 2015 at 9:34 AM, Segher Boessenkool
wrote:
> This implements cstore for the last case we do not yet handle, using
> the superopt algo from the venerable CWG. The only integer cases we
> do still not handle after this are for -m32 -mpowerpc64. Those case
> now generate a branch seq
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