From: Andreas Larsson
gcc/ChangeLog:
* config/sparc/sparc.c (dump_target_flag_bits): Print bit names for
LEON and LEON3.
---
gcc/config/sparc/sparc.c | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 06f41d7bb53..d5
Check the attribute of instruction to determine if it performs a store
or load operation. This more generic approach sees the last instruction
in the GOTdata_op model as a potential load and treats the memory barrier
as a potential store instruction.
gcc/ChangeLog:
* config/sparc/sparc.c
This version detects multiple empty assembly statements in a row and also
detects non-memory barrier empty assembly statements (__asm__("")). It
can be used instead of next_active_insn().
gcc/ChangeLog:
* config/sparc/sparc.c (next_active_non_empty_insn): New function
that returns
The LEON5 can often dual issue instructions from the same 64-bit aligned
double word if there are no data dependencies. Add scheduling information
to avoid scheduling unpairable instructions back-to-back.
gcc/ChangeLog:
* config/sparc/sparc-opts.h (enum sparc_processor_type): Add LEON5
A call to the function might have a load instruction in the delay slot
and a load followed by an atomic function could cause a deadlock.
gcc/ChangeLog:
* config/sparc/sparc.c (sparc_do_work_around_errata): Do not begin
functions with atomic instruction in the UT700 errata workarou
This is needed to prevent the Store -> (Non-store or load) -> Store
sequence.
gcc/ChangeLog:
* config/sparc/sparc.md: Add NOP to prevent sensitive sequence for
B2BST errata workaround.
---
gcc/config/sparc/sparc.md | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
Thank you for reviewing the patches! I will address your comments and
push the patches after testing.
Thanks again,
Daniel
On 2021-09-15 12:18, Eric Botcazou wrote:
The LEON5 can often dual issue instructions from the same 64-bit aligned
double word if there are no data dependencies. Add sched
When GCC is configured with --enable-target-optspace the compiler generates
a memcpy call in the Symbolizer constructor in sanitizer_symbolizer.cpp
when compiling for SPARC V8. Add HAVE_AS_SYM_ASSIGN to replace it with a
call to __sanitizer_internal_memcpy.
libsanitizer/ChangeLog:
* sanit
On 2024-01-16 15:44, Jakub Jelinek wrote:
On Tue, Jan 16, 2024 at 03:11:39PM +0100, Daniel Cederman wrote:
When GCC is configured with --enable-target-optspace the compiler generates
a memcpy call in the Symbolizer constructor in sanitizer_symbolizer.cpp
when compiling for SPARC V8. Add
pr88077 fails on SPARC since char HeaderStr[1] in pr88077_1.c and
long HeaderStr in pr88077_0.c differs in alignment.
warning: alignment 4 of normal symbol `HeaderStr' in c_lto_pr88077_0.o is
smaller than 8 used by the common definition in c_lto_pr88077_1.o
gcc/testsuite/ChangeLog:
* gcc
From: Andreas Larsson
LEON5 has a deeper write-buffer and hence stb is not enough to flush a
write out. For compatibility, use the default V8 approach for both
LEON3 and LEON5.
This reverts commit 49cc765db35a5a21cab2aece27a44983fa70b94b,
"sync.md (*membar_storeload_leon3): New insn."
gcc/Chang
This is to handle the membar_empty instruction that can be generated
when compiling for UT699.
gcc/ChangeLog:
* config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated
as empty
---
gcc/config/sparc/sparc.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/spar
LEON now uses the standard V8 membar patterns that contains an ldstub
instruction. This instruction needs to be aligned properly when the
GR712RC errata workaround is enabled.
gcc/ChangeLog:
* config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat
membar_storeload as atomic
* con
Conditional moves are not available in SPARC V8.
gcc/testsuite/ChangeLog:
* gcc.dg/ifcvt-4.c: Skip for SPARC V8
---
gcc/testsuite/gcc.dg/ifcvt-4.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/ifcvt-4.c b/gcc/testsuite/gcc.dg/ifcvt-4.c
index 8b2583d00e92..99ed3
On 2024-01-08 10:20, Eric Botcazou wrote:
pr88077 fails on SPARC since char HeaderStr[1] in pr88077_1.c and
long HeaderStr in pr88077_0.c differs in alignment.
warning: alignment 4 of normal symbol `HeaderStr' in c_lto_pr88077_0.o is
smaller than 8 used by the common definition in c_lto_pr88077_
"LEON3FT Stale Cache Entry After Store with Data Tag
Parity Error", for more information.
gcc/ChangeLog:
2017-01-18 Daniel Cederman
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
code when the flag is used.
See GRLIB-TN-0009, "LEON3FT Stale Cache Entry After Store with Data Tag
Parity Error", for more information.
gcc/ChangeLog:
2017-06-21 Daniel Cederman
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent
preprocessor) when needed.
But the implementation looks a bit strange, can't we merge the essentially
identical blocks of code into a single block, as for the other fixes?
I will submit a new version of the patch in which I have tried to remove
the code duplication.
--
Daniel Cederman
C
ion.
gcc/ChangeLog:
2017-06-21 Daniel Cederman
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
errata for certain LEON3FT processors.
(sparc_option_override): -mfix-ut69
mmand line in conjunction with -mfix flag. But if more
changes are required later on it would be good to have the define more
closely tied to the flag to minimize the number of changes to Makefiles
and etc.
Would it be OK to add if we document it properly?
--
Daniel Cederman
Cobham Gaisler
On 2017-06-30 07:11, Sebastian Huber wrote:
On 29/06/17 18:05, David Miller wrote:
From: Daniel Cederman
Date: Thu, 29 Jun 2017 17:15:43 +0200
I'm not thrilled with this, it's undocumented, the other workaround
don't have
it and I don't think that we really need i
floating-point operation or a floating-point branch.
It is applicable to GR712RC.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (fpop_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger
Daniel Cederman (4):
[SPARC] Errata workaround for GRLIB-TN-0012
[SPARC] Errata workaround for GRLIB-TN-0011
[SPARC] Errata workaround for GRLIB-TN-0010
[SPARC] Errata workaround for GRLIB-TN-0013
gcc/config/sparc/sparc.c | 205 -
gcc/config
0, and UT699.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (fpop_reg_depend_p): New function.
(div_sqrt_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0013 erra
This patch provides a workaround for the errata described in GRLIB-TN-0011.
If the workaround is enabled it will:
* Insert .align 16 before atomic instructions (swap, ldstub, casa).
It is applicable to GR712RC.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sync.md
target.
It is applicable to UT700.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (atomic_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0010 errata for
UT700
target.
It is applicable to UT700.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (atomic_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0010 errata for
UT700
0, and UT699.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (fpop_reg_depend_p): New function.
(div_sqrt_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0013 erra
floating-point operation or a floating-point branch.
It is applicable to GR712RC.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (fpop_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger
This patch provides a workaround for the errata described in GRLIB-TN-0011.
If the workaround is enabled it will:
* Insert .align 16 before atomic instructions (swap, ldstub, casa).
It is applicable to GR712RC.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sync.md
Hello Eric,
Thank you for your comments! I have updated the patches and will commit
them if you are OK with the changes.
Daniel Cederman (4):
[SPARC] Errata workaround for GRLIB-TN-0012
[SPARC] Errata workaround for GRLIB-TN-0011
[SPARC] Errata workaround for GRLIB-TN-0010
[SPARC] Errata
The sequence
st
fdivd / fsqrtd
std
was generated in some cases with -mfix-ut699 when there was
a st before the div/sqrt. This sequence could trigger the b2bst errata.
Now the following safe sequence is generated instead:
st
nop
fdivd / fsqrtd
std
gcc/ChangeLog:
2017-11-27 Martin A
Hello,
This patch series adds two fixes for the UT699 errata workaround.
Daniel Cederman (2):
[SPARC] Prevent -mfix-ut699 from generating b2bst errata sequences
[SPARC] Recognize the load when accessing the GOT
gcc/config/sparc/sparc.c | 8 +++-
gcc/config/sparc/sparc.md | 8
Needed for the UT699 errata workaround to function correctly when
compiling with -fPIC.
gcc/ChangeLog:
2017-11-27 Daniel Cederman
* config/sparc/sparc.c (sparc_do_work_around_errata): Treat the
movsi_pic_gotdata_op instruction as a load for the UT699 errata
workaround
+(and (eq_attr "fix_lost_divsqrt" "true")
+ (eq_attr "type" "fpdivs,fpsqrts,fpdivd,fpsqrtd"))
+ (const_string "false")
These lines should also be added to the in_integer_branch_annul_delay
attribute.
/Daniel C
...add (and (.) (not (eq_attr "branch_type" "icc")) to the first define_delay.
Ah, OK, that makes more sense. I will submit an updated version. Thanks
for getting back so quickly.
Daniel C
floating-point operation or a floating-point branch.
It is applicable to GR712RC.
gcc/ChangeLog:
2017-11-17 Daniel Cederman
* config/sparc/sparc.c (fpop_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger
Any particular reason to use MEM_P instead of mem_ref here? It looks like
there is also a case for the b2bst workaround (only loads are concerned).
No, there was no particular reason. mem_ref seems like a better choice
if it detects more types of loads.
/Daniel C
But isn't that the change I already rejected back in July?
You are right, that was a mistake from our side to submit it again. We
had rediscovered the sequence using our scanning script and I forgot
that the sequence was harmless in this case. We will update our scripts
and revert the patch.
reporting this to me.
gcc/ChangeLog:
2017-12-11 Daniel Cederman
* config/sparc/sparc.c (sparc_do_work_around_errata): Make sure
the jump is to a label.
---
gcc/config/sparc/sparc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/sparc/sparc.c b/gcc
uot;,
and StoreLoad can be achieved with a normal byte write "stb", instead of
an atomic byte read-write "ldstub". The provided patch changes the
previously mentioned memory barriers for TARGET_LEON3.
Best regards,
Daniel Cederman
ChangeLog:
2014-06-25 Danie
Not all LEON3 support the CASA instruction. This patch provides a mask
that can be used to specify which LEON3 targets that support CASA.
gcc/ChangeLog:
2015-06-22 Daniel Cederman
* config/sparc/sparc.c (sparc_option_override): Mark CPU targets
leon3 and leon3v7 as
that requires CASA to use the supervisor ASI.
gcc/ChangeLog:
2015-06-22 Daniel Cederman
* config/sparc/sparc.opt: Add supervisor mode flag (-msv-mode) and
make user mode the default
* config/sparc/sync.md: Only use supervisor ASI for CASA when in
supervisor
Early variants of LEON3, revision 0, do not support the CASA instruction.
This patch adds two new targets, leon3r0 and leon3r0v7, that are equivalent
to leon3 and leon3v7, except that they do not support CASA.
gcc/ChangeLog:
2015-06-22 Daniel Cederman
* config.gcc: Add leon3r0[v7
Linux requires LEON version 3 or above with CASA support.
gcc/ChangeLog:
2015-06-23 Daniel Cederman
* config/sparc/driver-sparc.c: map /proc/cpuinfo with CPU LEON
to leon3
---
gcc/config/sparc/driver-sparc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config
On 2015-06-23 14:34, Jakub Jelinek wrote:
On Tue, Jun 23, 2015 at 02:22:34PM +0200, Daniel Cederman wrote:
The muser-mode flag causes the CASA instruction for LEON3 to use the
user mode ASI. This is the correct behavior for almost all LEON3 targets.
For this reason it makes sense to make user
On 2015-06-23 14:58, Jakub Jelinek wrote:
On Tue, Jun 23, 2015 at 02:48:45PM +0200, Daniel Cederman wrote:
How does one check if the bit has been explicitly set? It was not obvious to
if (TARGET_USER_MODE_P (target_flags_explicit))
me, which is why I took a similar approach to a patch I
The muser-mode flag causes the CASA instruction for LEON3 to use the
user mode ASI. This is the correct behavior for almost all LEON3 targets.
For this reason it makes sense to make user mode the default.
gcc/ChangeLog:
2015-06-23 Daniel Cederman
* config/sparc/sparc.opt: Rename mask
instruction with the user-mode ASI on these systems
is not legal and will cause a trap.
--
Daniel Cederman
are
represented by different targets in binutils.
--
Daniel Cederman
now about leon3, eveything is leon for them.
Yes, that was a misunderstanding from my part.
--
Daniel Cederman
One could add a -mtune-fpu switch. Did you look at other architectures in the
GCC tree that would have similar requirements?
Thank you for the suggestion about adding a -mtune-fpu switch. I have
not yet looked at the other architectures, but will do so before proceeding.
--
Daniel Cederman
This removes a warning about operand 0 missing mode
gcc/ChangeLog:
2015-06-26 Daniel Cederman
* config/sparc/sparc.md: Window save takes a single integer
---
gcc/config/sparc/sparc.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/sparc/sparc.md b/gcc
__builtin_apply* and __builtin_return accesses the floating point registers on
SPARC even when compiling with -msoft-float.
gcc/ChangeLog:
2015-06-26 Daniel Cederman
* config/sparc/sparc.c (sparc_function_value_regno_p): Floating
point registers cannot be used when
gcc/ChangeLog:
2015-07-03 Daniel Cederman
* config/sparc/sparc.c (struct processor_costs): Set div cost
for leon to match UT699 and AT697F. Set mul cost for leon3 to
match standard leon3.
---
gcc/config/sparc/sparc.c | 8
1 file changed, 4 insertions(+), 4
On 2015-07-07 12:35, Eric Botcazou wrote:
2015-06-26 Daniel Cederman
* config/sparc/sparc.md: Window save takes a single integer
This will probably break in 64-bit mode, the operand can be a DImode register.
You are right, I forgot about that. Is there a mode one can use that
On 2015-07-07 12:37, Eric Botcazou wrote:
2015-07-03 Daniel Cederman
* config/sparc/sparc.c (struct processor_costs): Set div cost
for leon to match UT699 and AT697F. Set mul cost for leon3 to
match standard leon3.
So UT699 is not a standard LEON3?
LEON3 exists
without FPU.
* config/sparc/sparc.md (untyped_call): Do not save %f0 for a target
without FPU.
(untyped_return): Do not load %f0 for a target without FPU.
Understood. Thank you for looking at my patches and coming with
improvements.
--
Daniel Cederman
ion.
gcc/ChangeLog:
2017-07-07 Daniel Cederman
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
errata for certain LEON3FT processors.
(sparc_option_override): -mfix-ut69
write access just went on vacation. I have submitted a new version
(v4) with the change that applies to both main and 7.
--
Daniel Cederman
Cobham Gaisler
On 2017-07-07 18:04, Eric Botcazou wrote:
Great! Would you mind to apply the patch for us? The only person here
with write access just went on vacation. I have submitted a new version
(v4) with the change that applies to both main and 7.
OK, will do.
Thanks!
--
Daniel Cederman
Cobham
d later. OK to submit a new patch with only the second
nop and a correct length attribute?
--
Daniel Cederman
Cobham Gaisler
The errata fix for the UT699 fdivd and fsqrtd might cause a sequence
that can trigger the b2bst errata. Adding a NOP prevents this.
gcc/ChangeLog:
2017-07-11 Daniel Cederman
* config/sparc/sparc.md (divdf3_fix): Add NOP to prevent back
to back store errata sensitive sequence
Replace MULTILIB_EXCEPTIONS with MULTILIB_REQUIRED for readability.
-mfix-gr712rc and -mfix-ut700 are currently equivalent.
2017-07-14 Daniel Cederman
* config/sparc/t-rtems: Add mfix-gr712rc multilibs. Replace
MULTILIB_EXCEPTIONS with MULTILIB_REQUIRED. Match -mfix-gr712rc
t; any single non-store/load instruction -> stb/sth/st/std
The __FIX_B2BST define can be used to only enable workarounds in assembly
code when the flag is used.
See GRLIB-TN-0009, "LEON3FT Stale Cache Entry After Store with Data Tag
Parity Error", for more information.
gcc/ChangeLog:
operation
will be compiled to bit operations.
2014-09-14 Daniel Cederman
* libatomic/config/posix/lock.c (libat_lock_n): Acquire
locks in increasing order to avoid deadlocks
---
libatomic/config/posix/lock.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions
he new pattern is not "multi", it's "store" and you need to add:
&& !TARGET_LEON3
to the original membar_storeload since TARGET_LEON3 is also TARGET_V8.
--
Daniel Cederman
Software Engineer
Aeroflex Gaisler AB
Aeroflex Microelectronic Solutions – HiRel
Kungsgatan 12
SE-411 19 Gothenburg, Sweden
Phone: +46 31 7758665
ceder...@gaisler.com
www.Aeroflex.com/Gaisler
ChangeLog:
2014-07-11 Daniel Cederman
gcc/config/sparc/
* sync.md: Generate more efficient memory barriers for LEON3
---
gcc/config/sparc/sync.md | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc
That was an error on my side. The wrong memory model had gotten cached
in a generated make script. Lets drop membar_leon3 also then :)
On 2014-07-11 11:15, Eric Botcazou wrote:
The full barrier pattern membar_leon3 also gets generated so I think
that one should be kept also.
Do you have a tes
ChangeLog:
2014-07-11 Daniel Cederman
gcc/config/sparc/
* sync.md: Generate more efficient memory barriers for LEON3
---
gcc/config/sparc/sync.md | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index
imply mean that the memory model of the LEON3
is Strong Consistency and not TSO? In which case, the only thing to change is
the default setting for LEON3 in sparc_option_override.
--
Daniel Cederman
71 matches
Mail list logo
