Hello,
The memory barriers generated for SPARC are targeting the weakest memory
model allowed for SPARC. The LEON3/4 SPARC processors are using a
stronger memory model and thus have less requirements on the memory
barriers. For LEON3/4, StoreStore is compiler-only, instead of "stbar",
and StoreLoad can be achieved with a normal byte write "stb", instead of
an atomic byte read-write "ldstub". The provided patch changes the
previously mentioned memory barriers for TARGET_LEON3.
Best regards,
Daniel Cederman
ChangeLog:
2014-06-25 Daniel Cederman <ceder...@gaisler.com>
gcc/config/sparc/
* sync.md: Generate more efficient memory barriers for LEON3
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index e6e237f..26173a7 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -56,6 +56,15 @@
[(set_attr "type" "multi")
(set_attr "length" "0")])
+;; For LEON3, membar #StoreStore is compiler-only.
+(define_insn "*membar_storestore_leon3"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
+ "TARGET_LEON3"
+ ""
+ [(set_attr "type" "multi")
+ (set_attr "length" "0")])
+
;; For V8, STBAR is exactly membar #StoreStore, by definition.
(define_insn "*membar_storestore"
[(set (match_operand:BLK 0 "" "")
@@ -64,6 +73,14 @@
"stbar"
[(set_attr "type" "multi")])
+;; For LEON3, STB has the effect of membar #StoreLoad.
+(define_insn "*membar_storeload_leon3"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
+ "TARGET_LEON3"
+ "stb\t%%g0, [%%sp-1]"
+ [(set_attr "type" "multi")])
+
;; For V8, LDSTUB has the effect of membar #StoreLoad.
(define_insn "*membar_storeload"
[(set (match_operand:BLK 0 "" "")
@@ -72,6 +89,15 @@
"ldstub\t[%%sp-1], %%g0"
[(set_attr "type" "multi")])
+;; For LEON3, membar #StoreLoad is enough for a full barrier.
+(define_insn "*membar_leon3"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
+ UNSPEC_MEMBAR))]
+ "TARGET_LEON3"
+ "stb\t%%g0, [%%sp-1]"
+ [(set_attr "type" "multi")])
+
;; Put the two together, in combination with the fact that V8
implements PSO
;; as its weakest memory model, means a full barrier. Match all remaining
;; instances of the membar pattern for Sparc V8.
--
Daniel Cederman
Software Engineer
Aeroflex Gaisler AB
Aeroflex Microelectronic Solutions – HiRel
Kungsgatan 12
SE-411 19 Gothenburg, Sweden
Phone: +46 31 7758665
ceder...@gaisler.com
www.Aeroflex.com/Gaisler
