Re: [Patch ARM/testsuite 00/22] Neon intrinsics executable tests

On 6 June 2014 22:15, Christophe Lyon wrote: > On 6 June 2014 17:57, Ramana Radhakrishnan > wrote: >> On 06/06/14 15:40, Christophe Lyon wrote: >>> >>> On 6 June 2014 01:32, Joseph S. Myers wrote: >>>> >>>> Have these been tested for both

Re: [Patch ARM/testsuite 00/22] Neon intrinsics executable tests

On 11 June 2014 00:03, Ramana Radhakrishnan wrote: > On Thu, Jun 5, 2014 at 11:04 PM, Christophe Lyon > wrote: >> This is patch series is a more complete version of the patch I sent >> some time ago: >> https://gcc.gnu.org/ml/gcc-patches/2013-10/msg00624.html >>

Re: [Patch ARM/testsuite 00/22] Neon intrinsics executable tests

On 12 June 2014 04:31, Mike Stump wrote: > On Jun 10, 2014, at 3:03 PM, Ramana Radhakrishnan > wrote: >> I am a bit ambivalent between getting folks to add scan-assembler >> tests here and worrying between this and getting the behaviour >> correct. Additionally if you add the complexity of scann

Re: Patch improving spilling general regs into vector regs

Hi, This patches causes a failure to build GCC (since commit 211655), on all ARM and Aarch64 targets I track. I can see failures when building libgcc (_mulsc3.o, _muldc3.o, _divdc3.o), the error message being: 0xa07f6f crash_signal /tmp/214822_1.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/g

Re: [Patch ARM/testsuite 00/22] Neon intrinsics executable tests

On 11 June 2014 00:03, Ramana Radhakrishnan wrote: > On Thu, Jun 5, 2014 at 11:04 PM, Christophe Lyon > wrote: >> This is patch series is a more complete version of the patch I sent >> some time ago: >> https://gcc.gnu.org/ml/gcc-patches/2013-10/msg00624.html >>

Re: [Patch ARM/testsuite 02/22] Add unary operators: vabs and vneg.

On 27 June 2014 14:52, Ramana Radhakrishnan wrote: > On Thu, Jun 5, 2014 at 11:04 PM, Christophe Lyon > wrote: >> >> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_op.inc >> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_op.inc >> new fil

Re: [Patch ARM/testsuite 03/22] Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub.

On 27 June 2014 14:55, Ramana Radhakrishnan wrote: > On Thu, Jun 5, 2014 at 11:04 PM, Christophe Lyon > wrote: >> vadd tests also show how to add directives to scan the assembly >> output. >> >> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/bin

Re: [Patch ARM/testsuite 02/22] Add unary operators: vabs and vneg.

On 27 June 2014 15:04, Christophe Lyon wrote: > On 27 June 2014 14:52, Ramana Radhakrishnan wrote: >> On Thu, Jun 5, 2014 at 11:04 PM, Christophe Lyon >> wrote: >>> >>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/unary_op.inc >>> b/gc

[Patch ARM-AArch64/testsuite v2 00/21] Neon intrinsics executable tests

? Thanks, Christophe. Christophe Lyon (21): Neon intrinsics execution tests initial framework. Add unary operators: vabs and vneg. Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub. Add comparison operators: vceq, vcge, vcgt, vcle and vclt. Add comparison operators with floating

[Patch ARM-AArch64/testsuite v2 02/21] Add unary operators: vabs and vneg.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3a0f99b..44c4990 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/unary_op.inc: New file. + * gcc.target

[Patch ARM-AArch64/testsuite v2 03/21] Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 44c4990..73709c6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,16 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/binary_op.inc: New file. + * gcc.target

[Patch ARM-AArch64/testsuite v2 05/21] Add comparison operators with floating-point operands: vcage, vcagt, vcale and cvalt.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7af7fd0..3c25af1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,13 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/cmp_fp_op.inc: New file. + * gcc.target

[Patch ARM-AArch64/testsuite v2 10/21] Add vabdl tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e88287b..5509d41 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vabdl.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 01/21] Neon intrinsics execution tests initial framework.

/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2014-06-30 Christophe Lyon + + * gcc.target/arm/README.neon-intrinsics: New file. + * gcc.target/aarch64/neon-intrinsics/README: Likewise. + * gcc.target/aarch64/neon-intrinsics/arm-neon-ref.h: Likewise. + * gcc.target/aarch64/neon

[Patch ARM-AArch64/testsuite v2 11/21] Add vaddhn tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5509d41..e72500c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vaddhn.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 04/21] Add comparison operators: vceq, vcge, vcgt, vcle and vclt.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 73709c6..7af7fd0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,14 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/cmp_op.inc: New file. + * gcc.target

[Patch ARM-AArch64/testsuite v2 08/21] Add vabal tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 96cb431..b749a63 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vabal.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 12/21] Add vaddl tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e72500c..2888b74 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vaddl.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 09/21] Add vabd tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b749a63..e88287b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vabd.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 13/21] Add vaddw tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2888b74..de7405d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vaddw.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 14/21] Add vbsl tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index de7405d..cb539b4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vbsl.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 06/21] Add unary saturating operators: vqabs and vqneg.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3c25af1..1c317a7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/unary_sat_op.inc: New file. + * gcc.target

[Patch ARM-AArch64/testsuite v2 07/21] Add binary saturating operators: vqadd, vqsub.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1c317a7..96cb431 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/binary_sat_op.inc: New file. + * gcc.target

[Patch ARM-AArch64/testsuite v2 15/21] Add vclz tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cb539b4..dbffbcb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vclz.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 17/21] Add vld1_dup tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f26e93f..5dd2ae0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vld1_dup.c: New file. + +2014-06-30 Christophe

[Patch ARM-AArch64/testsuite v2 16/21] Add vdup and vmov tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dbffbcb..f26e93f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vdup-vmov.c: New file. + +2014-06-30 Christophe

[Patch ARM-AArch64/testsuite v2 20/21] Add vmul tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b923c53..775257e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vmul.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 18/21] Add vld2/vld3/vld4 tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5dd2ae0..2a359e0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vldX.c: New file. + +2014-06-30 Christophe Lyon

[Patch ARM-AArch64/testsuite v2 21/21] Add vuzp and vzip tests.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 775257e..14f80a0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vuzp.c: New file. + * gcc.target/aarch64

[Patch ARM-AArch64/testsuite v2 19/21] Add vld2_lane, vld3_lane and vld4_lane

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2a359e0..b923c53 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/vldX_lane.c: New file. + +2014-06-30 Christophe

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

Hi, It seems some of the scan-assembler directives fail: http://cbuild.validation.linaro.org/build/cross-validation/gcc/trunk/212196/aarch64-none-elf/diff-gcc-rh50-aarch64-none-elf-default-default-default.txt Christophe. On 1 July 2014 14:13, Marcus Shawcroft wrote: > On 23 June 2014 15:30, Ky

Re: combination of read/write and earlyclobber constraint modifier

On 3 July 2014 10:34, Tom de Vries wrote: > On 03-07-14 10:20, Marcus Shawcroft wrote: >> >> On 2 July 2014 09:02, Tom de Vries wrote: >>> >>> On 02-07-14 08:23, Marc Glisse wrote: In the first example you gave, looking at the pattern (no match_dup, setting the full regis

Re: combination of read/write and earlyclobber constraint modifier

On 7 July 2014 11:29, Christophe Lyon wrote: > On 3 July 2014 10:34, Tom de Vries wrote: >> On 03-07-14 10:20, Marcus Shawcroft wrote: >>> >>> On 2 July 2014 09:02, Tom de Vries wrote: >>>> >>>> On 02-07-14 08:23, Marc Glisse wrote: >>

[Patch ARM-AArch64/testsuite 00/13] Neon intrinsics executable tests

st on aarch64_be-none-elf because my build is currently broken (see PR 66018). 2015-05-12 Christophe Lyon * gcc.target/aarch64/neon-intrinsics/vqmovn.c: New file. * gcc.target/aarch64/neon-intrinsics/vqmovun.c: Likewise. * gcc.target/aarch64/neon-intrinsics/vqrdm

[Patch ARM-AArch64/testsuite Neon intrinsics 03/13] Add vqrdmulh tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh.c new file mode 100644 index 000..8875c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh.c @@ -0,0 +1,161 @@ +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 01/13] Add vqmovn tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovn.c new file mode 100644 index 000..b4d3198 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovn.c @@ -0,0 +1,134 @@ +#include +#incl

[Patch ARM-AArch64/testsuite Neon intrinsics 02/13] Add vqmovun tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovun.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovun.c new file mode 100644 index 000..d744765 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovun.c @@ -0,0 +1,93 @@ +#include +#in

[Patch ARM-AArch64/testsuite Neon intrinsics 05/13] Add vqrdmulh_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh_n.c new file mode 100644 index 000..fdc739c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh_n.c @@ -0,0 +1,155 @@ +#inc

[Patch ARM-AArch64/testsuite Neon intrinsics 04/13] Add vqrdmulh_lane tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh_lane.c new file mode 100644 index 000..2235e74 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrdmulh_lane.c @@ -0,0 +1,16

[Patch ARM-AArch64/testsuite Neon intrinsics 07/13] Add vqrshrn_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_n.c new file mode 100644 index 000..5a20d98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_n.c @@ -0,0 +1,174 @@ +#includ

[Patch ARM-AArch64/testsuite Neon intrinsics 10/13] Add vqshl_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshl_n.c new file mode 100644 index 000..92a5e0d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshl_n.c @@ -0,0 +1,234 @@ +#include +#i

[Patch ARM-AArch64/testsuite Neon intrinsics 08/13] Add vqrshrun_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_n.c new file mode 100644 index 000..f5e431e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrun_n.c @@ -0,0 +1,189 @@ +#inc

[Patch ARM-AArch64/testsuite Neon intrinsics 11/13] Add vqshlu_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshlu_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshlu_n.c new file mode 100644 index 000..a6710ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshlu_n.c @@ -0,0 +1,263 @@ +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 06/13] Add vqrshl tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshl.c new file mode 100644 index 000..3f0cb37 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshl.c @@ -0,0 +1,1090 @@ +#include +#inc

[Patch ARM-AArch64/testsuite Neon intrinsics 12/13] Add vqshrn_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_n.c new file mode 100644 index 000..b3556f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrn_n.c @@ -0,0 +1,177 @@ +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 09/13] Add vqshl tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshl.c new file mode 100644 index 000..f5a3084 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshl.c @@ -0,0 +1,829 @@ +#include +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 13/13] Add vqshrun_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_n.c new file mode 100644 index 000..ce1a3ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshrun_n.c @@ -0,0 +1,133 @@ +#includ

Re: [Patch ARM-AArch64/testsuite 00/13] Neon intrinsics executable tests

On 19 May 2015 at 15:32, James Greenhalgh wrote: > On Tue, May 12, 2015 at 09:30:48PM +0100, Christophe Lyon wrote: >> This patch series is a follow-up to the tests I already contributed, >> converted from my original testsuite. >> >> This series consists in 13 new fi

Re: [PATCH][Testsuite] Disable tests with dg-require-fork for simulated targets

On 18 May 2015 at 20:25, Mike Stump wrote: > On May 18, 2015, at 8:01 AM, Alan Lawrence wrote: >> Simulators such as qemu report the presence of fork (it's in glibc) but >> generally do not support synchronization primitives between threads, so any >> tests using fork are unreliable. > > Hum, I

Re: [patch, testsuite, ARM] don't try to execute advsimd-intrinsics tests on hardware without NEON

On 21 May 2015 at 07:33, Sandra Loosemore wrote: > ARM testing shares the AArch64 advsimd-intrinsics execution tests. On ARM, > though, the NEON support being tested is optional -- some arches are > compatible with the NEON compilation options but hardware available for > testing might or might n

Re: [PATCH 12/14][ARM/AArch64 Testsuite] Update advsimd-intrinsics tests to add float16 vectors

On 22 April 2015 at 19:31, Alan Lawrence wrote: > This is a fairly straightforward addition of a new type: I've added it in on > equal status to the other types, because the various > vector-load/store/element-manipulating intrinsics, are *not* conditional on > HW support. (They just involve movin

Re: [PATCH 13/14][ARM/AArch64 testsuite] Use gcc-dg-runtest in advsimd-intrinsics.exp

On 22 April 2015 at 19:36, Alan Lawrence wrote: > In the first revision of Christophe Lyon's advsimd-intrinsics tests, > https://gcc.gnu.org/ml/gcc-patches/2014-06/msg00532.html , both > gcc-dg-runtest (to assemble only) and c-torture-execute were used. In review > the gcc-dg-runtest part was then

Re: [PATCH 14/14][ARM/AArch64 testsuite] Test float16_t vcvt_* intrinsics

On 22 April 2015 at 19:38, Alan Lawrence wrote: > This adds a test of vcvt_f32_f16 and vcvt_f16_f32, also vcvt_high_f32_f16 > and vcvt_high_f16_f32. > > On ARM, we pass additional option -mfpu=neon-fp16 to the compiler (possible > following patch 2/3). The compiler is already receiving an option s

Re: [PATCH 13/14][ARM/AArch64 testsuite] Use gcc-dg-runtest in advsimd-intrinsics.exp

On 26 May 2015 at 18:25, Alan Lawrence wrote: > Christophe Lyon wrote: >> >> On 22 April 2015 at 19:36, Alan Lawrence wrote: >>> >>> In the first revision of Christophe Lyon's advsimd-intrinsics tests, >>> https://gcc.gnu.org/ml/gcc-patches/2014

[Patch ARM-AArch64/testsuite Neon intrinsics 01/20] Add vrecpe tests.

In order to have the same behaviour on ARM and AArch64 targets, we need to force flush to zero on AArch64. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h index 1742e99..4e728d5 100644 --- a/gcc/t

[Patch ARM-AArch64/testsuite Neon intrinsics 02/20] Add vrecps tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c new file mode 100644 index 000..0e41947 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c @@ -0,0 +1,117 @@ +#include +#incl

[Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests

as ARM by default. This is the final batch, except for the vget_lane tests which I will submit later. This should cover the subset of AdvSIMD intrinsics common to ARMv7 and AArch64. Tested with qemu on arm*linux, aarch64-linux. 2015-05-27 Christophe Lyon * gcc.target/aarch64/advsimd-

[Patch ARM-AArch64/testsuite Neon intrinsics 13/20] Add vshll_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c new file mode 100644 index 000..07bc904d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c @@ -0,0 +1,56 @@ +#include +#i

[Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c new file mode 100644 index 000..a2b40b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c @@ -0,0 +1,143 @@ +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 06/20] Add vshr_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c new file mode 100644 index 000..122ce41 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c @@ -0,0 +1,95 @@ +#include +#inclu

[Patch ARM-AArch64/testsuite Neon intrinsics 09/20] Add vrsqrte tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c new file mode 100644 index 000..0291ec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c @@ -0,0 +1,157 @@ +#include +#i

[Patch ARM-AArch64/testsuite Neon intrinsics 12/20] Add vset_lane tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c new file mode 100644 index 000..5159406 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c @@ -0,0 +1,99 @@ +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 04/20] Add vrev tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c new file mode 100644 index 000..3b574da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c @@ -0,0 +1,200 @@ +#include +#include "a

[Patch ARM-AArch64/testsuite Neon intrinsics 16/20] Add vsra_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c new file mode 100644 index 000..3c00497 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c @@ -0,0 +1,117 @@ +#include +#incl

[Patch ARM-AArch64/testsuite Neon intrinsics 14/20] Add vshl_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c new file mode 100644 index 000..d807ebb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c @@ -0,0 +1,96 @@ +#include +#inclu

[Patch ARM-AArch64/testsuite Neon intrinsics 17/20] Add vst1_lane tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c new file mode 100644 index 000..08583b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c @@ -0,0 +1,93 @@ +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 15/20] Add vshrn_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c new file mode 100644 index 000..6d2f4dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c @@ -0,0 +1,70 @@ +#include +#in

[Patch ARM-AArch64/testsuite Neon intrinsics 10/20] Add vrsqrts tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c new file mode 100644 index 000..4531026 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c @@ -0,0 +1,118 @@ +#include +#i

[Patch ARM-AArch64/testsuite Neon intrinsics 20/20] Add vtst tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c new file mode 100644 index 000..7f96540 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c @@ -0,0 +1,120 @@ +#include +#include "a

[Patch ARM-AArch64/testsuite Neon intrinsics 03/20] Add vreinterpret tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c new file mode 100644 index 000..9e45e25 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c @@ -0,0 +1,741 @@

[Patch ARM-AArch64/testsuite Neon intrinsics 07/20] Add vrshr_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c new file mode 100644 index 000..6f9ef5a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c @@ -0,0 +1,504 @@ +#include +#i

[Patch ARM-AArch64/testsuite Neon intrinsics 18/20] Add vstX_lane tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c new file mode 100644 index 000..26644ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c @@ -0,0 +1,578 @@ +#includ

[Patch ARM-AArch64/testsuite Neon intrinsics 05/20] Add vrshl tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c new file mode 100644 index 000..d970fbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c @@ -0,0 +1,627 @@ +#include +#include

[Patch ARM-AArch64/testsuite Neon intrinsics 19/20] Add vtbX tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c new file mode 100644 index 000..0557efd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c @@ -0,0 +1,289 @@ +#include +#include "a

[Patch ARM-AArch64/testsuite Neon intrinsics 11/20] Add vrsra_n tests.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c new file mode 100644 index 000..a9eda22 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c @@ -0,0 +1,553 @@ +#include +#i

Re: [PATCH 13/14][ARM/AArch64 testsuite] Use gcc-dg-runtest in advsimd-intrinsics.exp

On 28 May 2015 at 12:22, Alan Lawrence wrote: > Christophe Lyon wrote: >> >> On 26 May 2015 at 18:25, Alan Lawrence wrote: >>> >>> I don't see this symptom - I am able to execute such subsets with either >>> my, >>> or Sandra's, a

Re: [PATCH 13/14][ARM/AArch64 testsuite] Use gcc-dg-runtest in advsimd-intrinsics.exp

On 28 May 2015 at 13:32, Christophe Lyon wrote: > On 28 May 2015 at 12:22, Alan Lawrence wrote: >> Christophe Lyon wrote: >>> >>> On 26 May 2015 at 18:25, Alan Lawrence wrote: >>>> >>>> I don't see this symptom - I am able to execute suc

Re: [PATCH][ARM/AArch64 Testsuite] Cleanup advsimd-intrinsics.exp, removing unnecessary loop

On 28 May 2015 at 18:45, Alan Lawrence wrote: > I've tested this on aarch64, aarch64_be, and arm, and in all cases, the same > tests are executed (whether running the whole advsimd-intrinsics.exp, or > manually specifying a single file). AFAICT the loop, explicit > runtest_file_p, and gcc_set_para

Re: [PATCH][ARM/AArch64 Testsuite] Cleanup advsimd-intrinsics.exp, removing unnecessary loop

On 29 May 2015 at 12:48, Alan Lawrence wrote: > Christophe Lyon wrote: >> >> >> This looks OK, but why can't you also drop the other torture-related >> lines as you did in your previous patch? >> I mean: >> load_lib c-torture.exp >> load

Re: [PATCH, testsuite]: Cleanup dumps

c/testsuite/ChangeLog (revision 223875) +++ gcc/testsuite/ChangeLog (revision 223876) @@ -1,3 +1,7 @@ +2015-05-29 Christophe Lyon + + * gcc.target/arm/simd/vextp64_1.c: Close comment on final line. + 2015-05-29 Dominik

Re: [ARM] Fix CLZ_DEFINED_VALUE_AT_ZERO for vector modes

On 12 November 2014 14:46, Ramana Radhakrishnan wrote: > > > On 12/11/14 13:06, Christophe Lyon wrote: >> >> On 12 November 2014 04:50, Yangfei (Felix) wrote: >>>> >>>> On Wed, Oct 22, 2014 at 10:49 PM, Michael Collison >>>> >>&g

Re: New patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.

On 13 November 2014 11:09, David Sherwood wrote: > Hi All, > > I have successfully rebased this and tested in conjunction with a patch from > Alan Hayward ([AArch64] [BE] Fix vector load/stores to not use ld1/st1), who > should be submitting a new version shortly. Built and tested on: > > aarch64-

Re: libsanitizer merge from upstream r221802

On 13 November 2014 21:44, Konstantin Serebryany wrote: > On Thu, Nov 13, 2014 at 1:16 AM, Jakub Jelinek wrote: >> On Wed, Nov 12, 2014 at 05:35:48PM -0800, Konstantin Serebryany wrote: >>> Here is one more merge of libsanitizer (last one was in Sept). >>> >>> Tested on x86_64 Ubuntu 14.04 like t

Re: [Patch ARM-AArch64/testsuite] More Neon intrinsics executable tests

On 14 November 2014 12:17, Marcus Shawcroft wrote: > On 12 November 2014 13:11, Christophe Lyon wrote: >> Hi, >> >> The attached patch adds a few more tests to the recently added >> advsimd-intrinsics series. >> >> OK for trunk? >> >

Re: libsanitizer merge from upstream r221802

On 14 November 2014 11:38, Christophe Lyon wrote: > On 13 November 2014 21:44, Konstantin Serebryany > wrote: >> On Thu, Nov 13, 2014 at 1:16 AM, Jakub Jelinek wrote: >>> On Wed, Nov 12, 2014 at 05:35:48PM -0800, Konstantin Serebryany wrote: >>>> Here is one mor

Re: New patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.

up I think. > I've applied both Alan's patches and the advsimd-intrinsics tests now all pass on aarch64_be, but this doesn't need your patch. Which testcase does your patch actually fix? > Regards, > David. > > -Original Message- > From: Christophe Lyon

Re: New patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.

er to remove the CANNOT_CHANGE_MODE_CLASS > #define, which will be committed as a separate patch. > > Regards, > David Sherwood. > > -Original Message- > From: Christophe Lyon [mailto:christophe.l...@linaro.org] > Sent: 17 November 2014 21:09 > To: David Sherwood

Re: [PATCH][AArch64] Implement vsqrt_f64 intrinsic

Hi Kyrill, On 21 November 2014 at 16:52, Marcus Shawcroft wrote: > On 17 November 2014 17:35, Kyrill Tkachov wrote: > >> 2014-11-17 Kyrylo Tkachov >> >> * config/aarch64/arm_neon.h (vsqrt_f64): New intrinsic. >> >> 2014-11-17 Kyrylo Tkachov >> >> * gcc.target/aarch64/simd/vsqrt_f6

Re: [PATCH][ARM] Optimize copysign/copysignf for soft-float using BFI

On 27 November 2014 at 11:35, Ramana Radhakrishnan wrote: > On Wed, Oct 29, 2014 at 10:20 AM, Jiong Wang wrote: >> On 26/08/14 13:36, Richard Earnshaw wrote: >> >>> On 29/07/14 15:49, Jiong Wang wrote: test done === no regression on the full toolchain test on arm-none-eabi. >>

[ARM,AArch64][testsuite] Fix vaddl and vaddw tests

Hi, Here is a fix for typos in the AdvSimd intrinsic tests, where vaddl and vaddw didn't actually execute the tests. (The function was declared in main, instead of called). This patch also fixes the expected output for these tests. OK? Thanks Christophe. 2014-12-03 Christophe

Re: [ARM,AArch64][testsuite] Fix vaddl and vaddw tests

On 3 December 2014 at 15:22, Christophe Lyon wrote: > Hi, > > Here is a fix for typos in the AdvSimd intrinsic tests, where vaddl > and vaddw didn't actually execute the tests. (The function was > declared in main, instead of called). > > This patch also fixes the expec

Re: ipa-icf::merge TLC

On 27 February 2015 at 21:49, Jan Hubicka wrote: >> >> ../sysdeps/gnu/siglist.c:72:1: internal compiler error: in >> address_matters_p, at symtab.c:1908 >> versioned_symbol (libc, __new_sys_sigabbrev, sys_sigabbrev, GLIBC_2_3_3); >> ^ >> 0x66a080 symtab_node::address_matters_p() >> /scr

Re: ipa-icf::merge TLC

On 2 March 2015 at 21:21, Jan Hubicka wrote: >> >> >> On 01/03/15 16:47, Christophe Lyon wrote: >> >On 27 February 2015 at 21:49, Jan Hubicka wrote: >> >>> >> >>>../sysdeps/gnu/siglist.c:72:1: internal compiler error: in >> >&g

Re: ipa-icf::merge TLC

On 3 March 2015 at 13:44, Alex Velenko wrote: > On 02/03/15 22:04, Christophe Lyon wrote: >> >> On 2 March 2015 at 21:21, Jan Hubicka wrote: >>>> >>>> >>>> >>>> On 01/03/15 16:47, Christophe Lyon wrot

Re: ipa-icf::merge TLC

On 3 March 2015 at 21:01, Jan Hubicka wrote: >> > Hi, >> > >> > I built with r221117. I see errors while building following targets: >> > aarch64_be-none-linux-gnu, aarch64_be-none-linux-gnu, >> > arm-none-linux-gnueabihf, arm-none-linux-gnueabi. >> >> Indeed, it's broken again since r221099. > >

Re: [PATCH][ARM] New testcase to check parameter passing bug

On 03/13/15 13:04, Kyrill Tkachov wrote: Hi, Hi Honggyu, Thanks for helping out. I've got a couple of pointers for the testcase inline. I have wrote a testcase that reproduces argument overwriting bug during arm code generation. I wrote this testcase with the help of Mikael Pettersson. If

Re: Fix can_inline_edge_p and code marking calls unreachable

On 26 March 2015 at 22:12, Jan Hubicka wrote: > Hi, > this patch missed hunk adding CIF code that I commited now > * cif-code.def (CILK_SPAWN): New code Hi, After this fix, I can see build failures in glibc: key_call.c:574:1: internal compiler error: in inline_call, at ipa-inline-transfor

Re: Fix can_inline_edge_p and code marking calls unreachable

On 27 March 2015 at 03:14, Jan Hubicka wrote: >> On 2015.03.27 at 00:46 +0100, Jan Hubicka wrote: >> > > On 26 March 2015 at 22:12, Jan Hubicka wrote: >> > > After this fix, I can see build failures in glibc: >> > > key_call.c:574:1: internal compiler error: in inline_call, at >> > > ipa-inline-t

Re: [PR64164] drop copyrename, integrate into expand

On 8 June 2015 at 10:14, Richard Biener wrote: > On Sat, Jun 6, 2015 at 3:14 AM, Alexandre Oliva wrote: >> On Apr 27, 2015, Richard Biener wrote: >> >>> This should also mention that is_gimple_reg vars do not have their >>> address taken. >> >> check >> +static tree +leader_merge (tree

Re: [AArch64] Fix predicate and constraint mismatch in logical atomic operations

On 8 May 2015 at 12:42, Richard Biener wrote: > On Tue, Nov 4, 2014 at 11:44 AM, Marcus Shawcroft > wrote: >> On 25 September 2014 04:45, Michael Collison >> wrote: >>> On certain patterns in atomics.md the constraint 'n' is used in combination >>> with the predicate atomic_op_operand. The const

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