GCC maintainers:
The following patch fixes the first argument in the builtin definition
and the corresponding test cases. Initially, the builtin specification
was wrong due to a cut and past error. The documentation was fixed in:
commit 8cb748a31cd8c7ac9c88b6abc38ce077dd462a7a
Author: Bi
GCC maintainers:
The following patch takes the tests in vsx-vector-6-p7.h, vsx-vector-
6-p8.h, vsx-vector-6-p9.h and reorganizes them into a series of smaller
test files by functionality rather than processor version.
The patch has been tested on Power 10 with no regressions.
Please let me know
Kewen:
On Wed, 2023-05-31 at 17:11 +0800, Kewen.Lin wrote:
> > So, there is no need for the builtin to have to determine if the
> > user
> > is storing the result of the __builtin_set_fpscr_rn. The RN bits
> > will
> > always be updated by the __builtin_set_fpscr_rn builtin and the
> > existing f
On Wed, 2023-05-31 at 12:59 -0500, Peter Bergner wrote:
> On 5/22/23 4:04 AM, Kewen.Lin wrote:
> > on 2023/5/11 02:06, Carl Love via Gcc-patches wrote:
> > > @@ -3161,12 +3161,15 @@
> > >void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed
> >
Kewen, Segher, Peter:
The following patch is a redo of the previous "rs6000: Fix
__builtin_vec_xst_trunc definition" patch.
This patch fixes the argument in the two builtin definitions
__builtin_altivec_tr_stxvrwx and __builtin_altivec_tr_stxvrhx. It also
adds with a testcase to validate the r
GCC maintainers:
The following patch updates the expected instruction counts in four
tests. The counts in all of the tests changed with commit
f574e2dfae79055f16d0c63cc12df24815d8ead6.
The updated counts have been verified on both Power 9 and Power 10.
Please let me know if this patch is ac
Kewen, GCC maintainers:
Version 2, I have addressed the various comments from Kewen. I had
issues with adding an additional overloaded version of
scalar_insert_exp with vector arguments. The overload infrastructure
didn't work with a mix of scalar and vector arguments. I did rename
the __builti
On Mon, 2023-06-05 at 16:45 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/2 23:52, Carl Love via Gcc-patches wrote:
> > GCC maintainers:
> >
> > The following patch adds three buitins for inserting and extracting
> > the
> > exponent and signifi
Kewen, GCC maintainers:
Version 3, was able to get the overloaded version of scalar_insert_exp
to work and the change to xsxexpqp_f128_ define instruction to
work with the suggestions from Kewen.
Version 2, I have addressed the various comments from Kewen. I had
issues with adding an additiona
Kewen:
On Wed, 2023-06-07 at 17:36 +0800, Kewen.Lin wrote:
> Hi,
>
> on 2023/6/7 03:54, Carl Love wrote:
> > On Mon, 2023-06-05 at 16:45 +0800, Kewen.Lin wrote:
> > > Hi Carl,
> > >
> > > on 2023/5/2 23:52, Carl Love via Gcc-patches wrote:
>
On Tue, 2023-06-13 at 11:10 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/6/8 23:21, Carl Love wrote:
> > Kewen, GCC maintainers:
> >
> > Version 3, was able to get the overloaded version of
> > scalar_insert_exp
> > to work and the change to xsxexpqp_f128_ define instruction
> > to
> > work wit
Kewen, GCC maintainers:
Version 4, added missing cases for new xxexpqp, xsxexpdp and xsxsigqp
cases to rs6000_expand_builtin. Merged the new define_insn definitions
with the existing definitions. Renamed the builtins by removing the
__builtin_ prefix from the names. Fixed the documentation for
GCC maintainers:
Version 2, fixed various typos. Updated the change log body to say the
instruction counts were updated. The instruction counts changed as a
result of changing the first argument of the vec_replace_unaligned
builtin call from vector unsigned long long (vull) to vector unsigned
ch
On Tue, 2023-06-13 at 11:24 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/31 04:41, Carl Love wrote:
> > GCC maintainers:
> >
> > The following patch fixes the first argument in the builtin
> > definition
> > and the corresponding test cases. Initially, the builtin
> > specification
> > was w
On Thu, 2023-07-13 at 17:41 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/8 04:18, Carl Love wrote:
> > GCC maintainers:
> >
> > Version 3, added code to altivec_resolve_overloaded_builtin so the
> > correct instruction is selected for the size of the second
> > argument.
> > This restores th
GCC maintianers:
In the process of fixing the powerpc/vec-replace-word-runnable.c test I
found there is an existing issue with function find_instance in rs6000-
c.cc. Per the review comments from Kewen in
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624401.html
The fix for function fin
GCC maintainers:
The rs6000 function find_instance assumes that it is called for built-
ins with only two arguments. There is no checking for the actual
number of aruguments used in the built-in. This patch adds an
additional parameter to the function call containing the number of
aruguments i
GCC maintainers:
Version 4, changed the new RS6000_OVLD_VEC_REPLACE_UN case statement
rs6000/rs6000-c.cc. The existing REPLACE_ELT iterator name was changed
to REPLACE_ELT_V along with the associated define_mode_attr. Renamed
VEC_RU to REPLACE_ELT for the iterator name and VEC_RU_char to
REPLACE
Ping
On Thu, 2023-06-01 at 16:11 -0700, Carl Love wrote:
> GCC maintainers:
>
> The following patch updates the expected instruction counts in four
> tests. The counts in all of the tests changed with commit
> f574e2dfae79055f16d0c63cc12df24815d8ead6.
>
> The updated counts have been verified
On Fri, 2023-07-21 at 10:19 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/18 03:19, Carl Love wrote:
> > GCC maintainers:
> >
> > The rs6000 function find_instance assumes that it is called for
> > built-
> > ins with only two arguments. There is no checking for the actual
> > number of arugu
On Fri, 2023-07-21 at 13:04 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/18 03:20, Carl Love wrote:
> > GCC maintainers:
> >
> > Version 4, changed the new RS6000_OVLD_VEC_REPLACE_UN case
> > statement
> > rs6000/rs6000-c.cc. The existing REPLACE_ELT iterator name was
> > changed
> > to REPL
GCC maintianers:
Version 2. Both patches have been updated the first patch was approved
with minor issues to be fixed. I will post the updated version as
version 2 for completeness of the series. There were a few changes
with the second patch as well. The second patch has not been approved
yet
GCC maintainers:
Version 2: Updated a number of formatting and spacing issues. Added
the NARGS description to the header comment for function find_instance.
This patch was tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE
with no regressions.
The rs6000 function find_instance assumes that
GCC maintainers:
Version 5, Fixed patch description, the first argument should be of
type vector. Fixed comment in vsx.md to say "Vector and scalar
extract_elt iterator/attr ". Removed a few of the changes in
version 4. Specifically, reverted the names of REPLACE_ELT_V_sh back
to REPLACE_EL
GCC maintainers:
The following patch cleans up the definition for the
__builtin_altivec_vcmpnet. The current implementation implies that the
built-in is only supported on Power 9 since it is defined under the
Power 9 stanza. However the built-in has no ISA restrictions as stated
in the Power Vec
Kewen:
On Mon, 2023-07-31 at 14:53 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/28 23:00, Carl Love wrote:
> > GCC maintainers:
> >
> > The following patch cleans up the definition for the
> > __builtin_altivec_vcmpnet. The current implementation implies that
> > the
>
> s/__builtin_altive
GCC maintainers:
Ver 2: Re-worked the test vec-cmpne.c to create a compile only test
verify the instruction generation and a runnable test to verify the
built-in functionality. Retested the patch on Power 8 LE/BE, Power 9LE/BE and
Power 10 LE with no regressions.
The following patch cleans u
On Mon, 2023-08-07 at 17:18 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Sorry for the late review.
>
> on 2023/8/2 02:29, Carl Love wrote:
> > GCC maintainers:
> >
> > Ver 2: Re-worked the test vec-cmpne.c to create a compile only
> > test
> > verify the instruction generation and a runnable test to
GCC maintainers:
Ver 3: Updated description to make it clear the patch fixes the
confusion on the availability of the builtins. Fixed the dg-require-
effective-target on the test cases and the dg-options. Change the test
case so the for loop for the test will not be unrolled. Fixed a
spelling
Kewen:
On Wed, 2023-08-09 at 16:47 +0800, Kewen.Lin wrote:
> > Patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10
> > LE
> > with no regressions.
>
> Okay for trunk with two nits below fixed, thanks!
Thanks for all the help with the patch. Fixed the nits below, compiled
and re
GCC maintainers:
The following patch adds four built-ins for the decimal floating point
(DFP) quantize instructions on rs6000. The built-ins are for 64-bit
and 128-bit DFP operands.
The patch also adds a test case for the new builtins.
The Patch has been tested on Power 10LE and Power 9 LE/BE
GCC maintainers:
Version 2, renamed the built-in instances. Changed the name of the
overloaded built-in. Added the missing documentation for the new
built-ins. Fixed typos. Changed name of the test. Updated the
effective target for the test. Retested the patch on Power 10LE and
Power 8 and
On Thu, 2023-06-15 at 14:23 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/6/15 04:37, Carl Love wrote:
> > Kewen, GCC maintainers:
> >
> > Version 4, added missing cases for new xxexpqp, xsxexpdp and
> > xsxsigqp
> > cases to rs6000_expand_builtin. Merged the new define_insn
> > definitions
> >
Kewen, GCC maintainers:
Version 5, Tested the patch on P9 BE per request. Fixed up test case
to get the correct expected values for BE and LE. Fixed typos.
Updated the doc/extend.texi to clarify the vector arguments. Changed
test file names per request. Moved builtin defs next to related
defi
GCC maintainers:
The GLibC team requested a builtin to replace the mffscrn and mffscrniinline
asm instructions in the GLibC code. Previously there was discussion on adding
builtins for the mffscrn instructions.
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620261.html
In the end, it was
Kewen:
On Mon, 2023-06-19 at 14:08 +0800, Kewen.Lin wrote:
> >
> Hi Carl,
>
> on 2023/6/17 01:57, Carl Love wrote:
> > overloaded instance. Update comments.
> > * config/rs6000/rs6000-overload.def
> > (__builtin_vec_scalar_insert_exp): Add new overload definition
> > with
> >
Kewen, GCC maintainers:
Version 6, Fixed missing change log entry. Changed builtin id names as
requested. Missed making the change on the last version. Fixed
comment in the three test cases. Reran regression suite on Power 10,
no regressions.
Version 5, Tested the patch on P9 BE per request
On Mon, 2023-06-19 at 15:17 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/31 04:46, Carl Love wrote:
> > GCC maintainers:
> >
> > The following patch takes the tests in vsx-vector-6-p7.h, vsx-
> > vector-
> > 6-p8.h, vsx-vector-6-p9.h and reorganizes them into a series of
> > smaller
> > test
GCC maintainers:
Ver 2. Switched to using code macros to generate the call to the
builtin and test the results. Added in instruction counts for the key
instruction for the builtin. Moved the tests into an additional
function call to ensure the compile doesn't replace the builtin call
code wit
Kewen:
On Wed, 2023-06-28 at 16:35 +0800, Kewen.Lin wrote:
> > Yea, I was going with a runnable test and didn't include the
> > instruction counts. Added back in. Rather then doing by processor
> > version (P8, P9, P10) I was able to do it by BE/LE. The
> > instruction
> > counts were the same
GCC maintainers:
Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
of the scan-assembler-times checks to cover multiple similar
instructions. Change the function check macro to a macro to generate a
function to do the test and check the results. Retested on the various
proce
Kewen:
On Fri, 2023-06-30 at 11:37 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/6/30 05:36, Carl Love wrote:
> > Kewen:
> >
> > On Wed, 2023-06-28 at 16:35 +0800, Kewen.Lin wrote:
> > > > Yea, I was going with a runnable test and didn't include the
> > > > instruction counts. Added back in.
Kewen:
On Fri, 2023-06-30 at 15:20 -0700, Carl Love wrote:
> So, went to look at the assembly to verify my comment on the
> difference
> being related to the loads. I decided to actually count the
> instructions just to verify the number in the assembly files.
> Before,
> I just looked at the ass
GCC maintainers:
Ver 2, Went back thru the requirements and emails. Not sure where I
came up with the requirement for an overloaded version with double
argument. Removed the overloaded version with the double argument.
Added the macro to announce if the __builtin_set_fpscr_rn returns a
void
Kewen:
On Fri, 2023-06-30 at 15:20 -0700, Carl Love wrote:
> Segher never liked the above way of looking at the assembly. He
> prefers:
> gcc -S -g -mcpu=power8 -o vsx-vector-6-func-2lop.s vsx-vector-6-
> func-
> 2lop.c
>
> grep xxlor vsx-vector-6-func-2lop.s | wc
> 34 68 516
>
Kewen:
On Tue, 2023-07-04 at 10:49 +0800, Kewen.Lin wrote:
>
> >
> > The tests are broken up into a seriers of files for related
> > tests. The
>
> s/seriers/series/
Fixed
>
> > new tests are runnable tests to verify the builtin argument types
> > and the
> > functional correctness of ea
GCC maintainers:
Ver 4. Fixed a few typos. Redid the tests to create separate run and
compile tests.
Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
of the scan-assembler-times checks to cover multiple similar
instructions. Change the function check macro to a macro to ge
Kewen:
On Mon, 2023-06-19 at 11:50 +0800, Kewen.Lin wrote:
> > generated the vinsd instruction for the two calls with the first
> > argument of unsigned long long int. When the first argument of the
> > builtin is changed to the correct type, vector unsigned char the
> > builtin generates the vin
GCC maintainers:
Version 3, added code to altivec_resolve_overloaded_builtin so the
correct instruction is selected for the size of the second argument.
This restores the instruction counts to the original values where the
correct instructions were originally being generated. The naming of
the
On Fri, 2023-07-07 at 10:15 +0800, Kewen.Lin wrote:
>
> > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-compile.c
> > new file mode 100644
> > index 000..6b7d73ed66c
> > --- /dev/null
> >
GCC maintainers:
Ver 5. Removed -compile from the names of the compile only tests. Fixed
up the reference to the compile file names in the .h file headers.
Replaced powerpc_vsx_ok with vsx_hw in the run test files. Removed the
-save-temps from all files. Retested on all of the various platfor
On Thu, 2023-07-06 at 17:54 -0500, Peter Bergner wrote:
> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
> > rs6000, __builtin_set_fpscr_rn add retrun value
>
> s/retrun/return/
>
> Maybe better written as:
>
> rs6000: Add return value to __builtin_set_fpscr
On Fri, 2023-07-07 at 12:06 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Some more minor comments are inline below on top of Peter's
> insightful
> review comments.
>
> on 2023/7/1 08:58, Carl Love wrote:
> > GCC maintainers:
> >
> > Ver 2, Went back thru the requirements and emails. Not sure where
GCC maintainers:
Ver 3, Renamed the patch per comments on ver 2. Previous subject line
was " [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value".
Fixed spelling mistakes and formatting. Updated define_expand
"rs6000_set_fpscr_rn to have the rs6000_get_fpscr_fields and
rs6000_updat
Peter:
On Mon, 2023-07-10 at 16:57 -0500, Peter Bergner wrote:
> On 7/10/23 2:18 PM, Carl Love wrote:
> > + /* Get the current FPSCR fields, bits 29:31 (DRN) and bits 56:63
> > (VE, OE, UE,
> > + ZE, XE, NI, RN) from the FPSCR and return them. */
>
> The 'Z' above should line up directly unde
On Tue, 2023-07-11 at 13:54 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Excepting for Peter's review comments, some nits are inline below.
>
> on 2023/7/11 03:18, Carl Love wrote:
> > GCC maintainers:
> >
> >
> >
> > -
> > rs6000, Add return value
GCC maintainers:
Ver 4, Removed extra space in subject line. Added comment to commit
log comments about new __SET_FPSCR_RN_RETURNS_FPSCR__ define. Changed
Added to Add and Renamed to Rename in ChangeLog. Updated define_expand
"rs6000_set_fpscr_rn" per Peter's comments to use new temporary
regis
GCC maintainers:
The following patch fixes errors in the arguments in the
__builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx builtin
definitions. Note, these builtins are used by the overloaded
__builtin_vec_xst_trunc builtin.
The patch adds a new overloaded builtin definition for
__bu
GCC maintainers:
version 2. Fixed an issue with the test case. The dg-options line was
missing.
The following patch adds an overloaded builtin. There are two possible
arguments for the builtin. The builtin definitions are:
double __builtin_mffscrn (unsigned long int);
double __builtin_mf
Peter:
On Thu, 2023-05-18 at 16:28 -0500, Peter Bergner wrote:
>
>
> > + void __builtin_vec_xst_trunc (vsq, signed long long, signed long
> > *);
> > +TR_STXVRLX TR_STXVRLX_S
> > + void __builtin_vec_xst_trunc (vuq, signed long long, unsigned
> > long *);
> > +TR_STXVRLX TR_STXVRL
On Mon, 2023-05-22 at 14:36 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/19 05:12, Carl Love via Gcc-patches wrote:
> > GCC maintainers:
> >
> > version 2. Fixed an issue with the test case. The dg-options line
> > was
> > missing.
> >
>
Kewen, Segher, GCC maintainers:
Version 3, fixed various issues noted by Kewen. Retested on Power 10.
No regression issues.
Version 2, Fixed an issue with the test case. The dg-options line was
missing.
The following patch adds an overloaded builtin. There are two possible
arguments for the
On Mon, 2023-05-22 at 17:04 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/11 02:06, Carl Love via Gcc-patches wrote:
> > GCC maintainers:
> >
> > The following patch fixes errors in the arguments in the
> > __builtin_altivec_tr_stxvrhx, __built
Kewen, GCC maintainers:
Version 2, addressed comments from Kewen. Added an additional
overloaded builtin:
void __builtin_vec_xst_trunc (vuq, signed long long, long *);
The following patch fixes errors in the arguments in the
__builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx built
On Wed, 2023-05-24 at 13:32 +0800, Kewen.Lin wrote:
> on 2023/5/24 06:30, Peter Bergner wrote:
> > On 5/23/23 12:24 AM, Kewen.Lin wrote:
> > > on 2023/5/23 01:31, Carl Love wrote:
> > > > The builtins were requested for use in GLibC. As of version
> > > > 2.31 they
> > > > were added as inline asm
Peter, Kewen:
On Thu, 2023-05-25 at 13:28 +0800, Kewen.Lin wrote:
> on 2023/5/24 23:20, Carl Love wrote:
> > On Wed, 2023-05-24 at 13:32 +0800, Kewen.Lin wrote:
> > > on 2023/5/24 06:30, Peter Bergner wrote:
> > > > On 5/23/23 12:24 AM, Kewen.Lin wrote:
> > > > > on 2023/5/23 01:31, Carl Love wrot
Will, Segher:
The following is the updated patch set for the 128-bit Binary Integer
Operation. I am reposting the entire set for completeness. I have
noted in each patch the changes made since the previous version.
The patches have been tested on Power 8 and Power 9 to ensure there are
no reg
Segher, Will:
Add support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
The updates from the previous version of the patch:
Removed stray ";; carll" comment.
Removed #if 1 and #endif in the test case.
Replaced TARGET_TI_VECTOR_OPS with POWER10.
The pa
Segher, Will:
Patch 1, adds the 128-bit sign extension instruction support and
corresponding builtin support.
No changes from the previous version.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
Fixed the issues in the ChangeLog noted by
Will, Segher:
Add support for divide, modulo, shift, compare of 128-bit
integers instructions and builtin support.
The following are the changes from the previous version of the patch.
The TARGET_TI_VECTOR_OPS was removed per comments for patch 3. Just
using TARGET_POWER10.
Removed extra com
Segher, Will:
Patch 5 adds the 128-bit integer to/from 128-floating point
conversions. This patch has to invoke the routines to use the 128-bit
hardware instructions if on Power 10 or use software routines if
running on a pre Power 10 system via the resolve function.
Add ifunc resolves for __f
Segher, Will:
Patch 4 adds the vector 128-bit integer shift instruction support for
the V1TI type.
The following changes were made from the previous version.
Renamed VSX_TI to VEC_TI, put def in vector.md. Didn't get it
separated into a different patch.
Reworked the XXSWAPD_V1TI to not use U
Will, Segher:
Patch 1, adds the 128-bit sign extension instruction support and
corresponding builtin support.
I updated the change log per the comments from Will.
Patch has been retested on Power 9 LE.
Pet me know if it is ready to commit to mainline.
Carl
--
Will, Segher:
The following changes were made from the previous version:
Per Will's comments, I split the bug fix from patch 2 into a separate
patch. This patch is the bug fix for the vec_rlnm builtin.
Regression tests reran on Power 9 LE with no regression errors.
Please let me know if it l
Will, Segher:
Patch 4 adds the vector 128-bit integer shift instruction support for
the V1TI type.
The changes from the previous version include:
Fixed up the change log entry issues noted by Will.
Regression tests reran on Power 9 LE with no regression errors.
Please let me know if it looks O
Will and Segher:
This is the rest of the second patch which adds the 128-bit integer
support for divide, modulo, shift, compare of 128-bit
integers instructions and builtin support.
In the last round of changes, the flag for the 128-bit operations was
removed. Per Will's comments, the BU_P10_12
Will, Segher:
This patch adds support for converting to/from 128-bit integers and
128-bit decimal floating point formats using the new P10 instructions
dcffixqq and dctfixqq. The new instructions are only used on P10 HW,
otherwise the conversions continue to use the existing SW routines.
The cha
Will, Segher:
Add support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
The updates from the previous version of the patch:
Just a fix for the change log per Will's comments.
No regression failures were found when run on a P9.
Please let me know if this i
David:
>
> Hi, Carl
>
> I thought that vector.md was a transfer vector for the patterns and
> instructions were defined in vsx.md. Why are the new insn patterns
> defined in vector.md?
I am a bit of a newbie here. I wasn't aware of any specific guide
lines on the vector instructions. I put
David:
I have reworked the patch moving the new vector instruction patterns to
vsx.md. Also, cleaned up the vector division instructions. The
div3 pattern definitions are the only ones that should be
defined.
I have retested the patch on:
powerpc64le-unknown-linux-gnu (Power 9 LE)
with n
GCC maintainers:
The gcc test suite compiles and attempts to run the check-builtin-
vec_rlnm-runnable.c test on Power 8 platforms. The test should only be
run on Power 9 and newer platforms. The attached patch fixes the
target for the executable test so it only runs on Power 9 and newer
platform
Segher, Will:
Bill asked that I refresh thes 128-bit integer patch set and get it
reposted. I have rebased the patches onto the latest mainline
respository. I have also retested the patches on Power 8 BE, Power 9
LE and Power 10 LE hardware.
A request has been made last week to change the funct
Will, Segher:
This patch fixes the order of the argument in the vec_rlmi and
vec_rlnm builtins. The patch also adds a new test cases to verify
the fix.
The patch has been tested on
powerpc64-linux instead (Power 8 BE)
powerpc64-linux instead (Power 9 LE)
powerpc64-linux instead (Powe
Will, Segher:
This patch adds support for converting to/from 128-bit integers and
128-bit decimal floating point formats.
The patch has been tested on
powerpc64-linux instead (Power 8 BE)
powerpc64-linux instead (Power 9 LE)
powerpc64-linux instead (Power 10 LE)
Please let me know if
Will, Segher:
This patch adds the 128-bit integer support for divide, modulo, shift,
compare of 128-bit integers instructions and builtin support.
The patch has been tested on
powerpc64-linux instead (Power 8 BE)
powerpc64-linux instead (Power 9 LE)
powerpc64-linux instead (Power 10 L
Will, Segher:
The previous patch added the vector 128-bit integer shift instruction
support for the V1TI type. This patch renames and moves the VSX_TI
iterator from vsx.md to VEC_TI in vector.md. The uses of VEC_TI are
also updated.
The patch has been tested on
powerpc64-linux instead (Powe
Will, Segher:
This patch adds support for converting to/from 128-bit integers and
128-bit decimal floating point formats using the new P10 instructions
dcffixqq and dctfixqq. The new instructions are only used on P10 HW,
otherwise the conversions continue to use the existing SW routines.
The fil
Segher, Will:
The agreement for the sign extension builtin was to just make it Endian
aware rather then go with a more complex definition. The prior patch
has been updated with this new functionality.
This patch adds support for the 128-bit extension instruction and
corresponding builtin support
On Tue, 2021-04-27 at 18:46 -0500, will schmidt wrote:
> On Mon, 2021-04-26 at 09:35 -0700, Carl Love wrote:
> > Will, Segher:
> >
> > This patch fixes the order of the argument in the vec_rlmi and
> > vec_rlnm builtins. The patch also adds a new test cases to verify
> > the fix.
> >
> > The pat
Kewen, Peter:
> on 2023/8/17 08:19, Carl Love wrote:
> > GCC maintainers:
> >
> > Version 2, renamed the built-in instances. Changed the name of the
> > overloaded built-in. Added the missing documentation for the new
> > built-ins. Fixed typos. Changed name of the test. Updated the
> > effe
GCC maintainers:
Version 3, fixed the built-in instance names. Missed removing the "n"
the name. Added the tighter constraints on the predicates for the
define_insn. Updated the wording for the built-ins in the
documentation file. Changed the test file name again. Updated the
ChangeLog file,
On Mon, 2023-08-28 at 10:21 +0800, Kewen.Lin wrote:
> Hi Carl,
> >
> > A testcase is added for the new built-in definitions.
> >
> > gcc/ChangeLog:
> > * config/rs6000/dfp.md: New UNSPEC_DQUAN.
>
> Nit: (UNSPEC_DQUAN): New unspec.
Fixed.
>
> > +(define_insn "dfp_dqua_"
> > + [(set
GCC maintainers:
Version 4, additional define_insn name fix. Change Log fix for the
UNSPEC_DQUAN. Retested patch on Power 10 LE.
Version 3, fixed the built-in instance names. Missed removing the "n"
the name. Added the tighter constraints on the predicates for the
define_insn. Updated the
Kewen:
On Tue, 2023-08-29 at 16:54 +0800, Kewen.Lin wrote:
> > The following functions require @option{-mhard-float},
> > diff --git a/gcc/testsuite/gcc.target/powerpc/pr93448.c
> > b/gcc/testsuite/gcc.target/powerpc/pr93448.c
> > new file mode 100644
> > index 000..f9c388585d7
> > --- /
Segher:
The following is a five patch series for the 128-bit Binary Integer
Operations (RFC 2608).
The last patch does the 128-bit integer to 128-bit float to/from
conversions. The patch has been reviewed by Michael Meissner to make
sure the Floating point 128-mode handling is correct.
The patc
Segher, Will:
Path 3 adds support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
Carl Love
Add TI to TD (128-bit DFP) and TD to TI support
gcc/ChangeLog
2020-08-10 Carl
Segher, Will:
Patch 4 adds 128-bit integer shift instruction support.
Carl Love
-
Test 128-bit shifts for just the int128 type.
gcc/ChangeLog
2020-08-10 Carl Love
* config/rs6000/altivec.md (altivec_vslq, altiv
Segher, Will:
Patch 5 adds the 128-bit integer to/from 128-floating point
conversions. This patch has to invoke the routines to use the 128-bit
hardware instructions if on Power 10 or use software routines if
running on a pre Power 10 system via the resolve function.
Segher, Will:
Patch 2, adds support for divide, modulo, shift, compare of 128-bit
integers. The support adds the instruction and builtin support.
Carl Love
---
rs6000, 128-bit multiply, divide, shift, compare
gcc/ChangeLog
2020
Segher, Will:
Patch 1, adds the sign extension instruction support and corresponding
builtins.
Carl Love
-
RS6000 Add 128-bit sign extension support
gcc/ChangeLog
2020-08-10 Carl Love
* config/rs6000/al
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