Kewen:
On Wed, 2023-05-31 at 17:11 +0800, Kewen.Lin wrote:
> > So, there is no need for the builtin to have to determine if the
> > user
> > is storing the result of the __builtin_set_fpscr_rn. The RN bits
> > will
> > always be updated by the __builtin_set_fpscr_rn builtin and the
> > existing f
On Wed, 2023-05-31 at 12:59 -0500, Peter Bergner wrote:
> On 5/22/23 4:04 AM, Kewen.Lin wrote:
> > on 2023/5/11 02:06, Carl Love via Gcc-patches wrote:
> > > @@ -3161,12 +3161,15 @@
> > >void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed
> >
Kewen, Segher, Peter:
The following patch is a redo of the previous "rs6000: Fix
__builtin_vec_xst_trunc definition" patch.
This patch fixes the argument in the two builtin definitions
__builtin_altivec_tr_stxvrwx and __builtin_altivec_tr_stxvrhx. It also
adds with a testcase to validate the r
GCC maintainers:
The following patch updates the expected instruction counts in four
tests. The counts in all of the tests changed with commit
f574e2dfae79055f16d0c63cc12df24815d8ead6.
The updated counts have been verified on both Power 9 and Power 10.
Please let me know if this patch is ac
Kewen, GCC maintainers:
Version 2, I have addressed the various comments from Kewen. I had
issues with adding an additional overloaded version of
scalar_insert_exp with vector arguments. The overload infrastructure
didn't work with a mix of scalar and vector arguments. I did rename
the __builti
On Mon, 2023-06-05 at 16:45 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/2 23:52, Carl Love via Gcc-patches wrote:
> > GCC maintainers:
> >
> > The following patch adds three buitins for inserting and extracting
> > the
> > exponent and signifi
Kewen, GCC maintainers:
Version 3, was able to get the overloaded version of scalar_insert_exp
to work and the change to xsxexpqp_f128_ define instruction to
work with the suggestions from Kewen.
Version 2, I have addressed the various comments from Kewen. I had
issues with adding an additiona
Kewen:
On Wed, 2023-06-07 at 17:36 +0800, Kewen.Lin wrote:
> Hi,
>
> on 2023/6/7 03:54, Carl Love wrote:
> > On Mon, 2023-06-05 at 16:45 +0800, Kewen.Lin wrote:
> > > Hi Carl,
> > >
> > > on 2023/5/2 23:52, Carl Love via Gcc-patches wrote:
>
On Tue, 2023-06-13 at 11:10 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/6/8 23:21, Carl Love wrote:
> > Kewen, GCC maintainers:
> >
> > Version 3, was able to get the overloaded version of
> > scalar_insert_exp
> > to work and the change to xsxexpqp_f
Kewen, GCC maintainers:
Version 4, added missing cases for new xxexpqp, xsxexpdp and xsxsigqp
cases to rs6000_expand_builtin. Merged the new define_insn definitions
with the existing definitions. Renamed the builtins by removing the
__builtin_ prefix from the names. Fixed the documentation for
GCC maintainers:
Version 2, fixed various typos. Updated the change log body to say the
instruction counts were updated. The instruction counts changed as a
result of changing the first argument of the vec_replace_unaligned
builtin call from vector unsigned long long (vull) to vector unsigned
ch
On Tue, 2023-06-13 at 11:24 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/31 04:41, Carl Love wrote:
> > GCC maintainers:
> >
> > The following patch fixes the first argument in the builtin
> > definition
> > and the corresponding test cases. Initially
On Thu, 2023-07-13 at 17:41 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/8 04:18, Carl Love wrote:
> > GCC maintainers:
> >
> > Version 3, added code to altivec_resolve_overloaded_builtin so the
> > correct instruction is selected for the size of the second
GCC maintianers:
In the process of fixing the powerpc/vec-replace-word-runnable.c test I
found there is an existing issue with function find_instance in rs6000-
c.cc. Per the review comments from Kewen in
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624401.html
The fix for function fin
GCC maintainers:
The rs6000 function find_instance assumes that it is called for built-
ins with only two arguments. There is no checking for the actual
number of aruguments used in the built-in. This patch adds an
additional parameter to the function call containing the number of
aruguments i
GCC maintainers:
Version 4, changed the new RS6000_OVLD_VEC_REPLACE_UN case statement
rs6000/rs6000-c.cc. The existing REPLACE_ELT iterator name was changed
to REPLACE_ELT_V along with the associated define_mode_attr. Renamed
VEC_RU to REPLACE_ELT for the iterator name and VEC_RU_char to
REPLACE
Ping
On Thu, 2023-06-01 at 16:11 -0700, Carl Love wrote:
> GCC maintainers:
>
> The following patch updates the expected instruction counts in four
> tests. The counts in all of the tests changed with commit
> f574e2dfae79055f16d0c63cc12df24815d8ead6.
>
> The upd
On Fri, 2023-07-21 at 10:19 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/18 03:19, Carl Love wrote:
> > GCC maintainers:
> >
> > The rs6000 function find_instance assumes that it is called for
> > built-
> > ins with only two arguments. There is n
On Fri, 2023-07-21 at 13:04 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/18 03:20, Carl Love wrote:
> > GCC maintainers:
> >
> > Version 4, changed the new RS6000_OVLD_VEC_REPLACE_UN case
> > statement
> > rs6000/rs6000-c.cc. The existing REPLACE_E
GCC maintianers:
Version 2. Both patches have been updated the first patch was approved
with minor issues to be fixed. I will post the updated version as
version 2 for completeness of the series. There were a few changes
with the second patch as well. The second patch has not been approved
yet
GCC maintainers:
Version 2: Updated a number of formatting and spacing issues. Added
the NARGS description to the header comment for function find_instance.
This patch was tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE
with no regressions.
The rs6000 function find_instance assumes that
GCC maintainers:
Version 5, Fixed patch description, the first argument should be of
type vector. Fixed comment in vsx.md to say "Vector and scalar
extract_elt iterator/attr ". Removed a few of the changes in
version 4. Specifically, reverted the names of REPLACE_ELT_V_sh back
to REPLACE_EL
GCC maintainers:
The following patch cleans up the definition for the
__builtin_altivec_vcmpnet. The current implementation implies that the
built-in is only supported on Power 9 since it is defined under the
Power 9 stanza. However the built-in has no ISA restrictions as stated
in the Power Vec
Kewen:
On Mon, 2023-07-31 at 14:53 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/7/28 23:00, Carl Love wrote:
> > GCC maintainers:
> >
> > The following patch cleans up the definition for the
> > __builtin_altivec_vcmpnet. The current implement
GCC maintainers:
Ver 2: Re-worked the test vec-cmpne.c to create a compile only test
verify the instruction generation and a runnable test to verify the
built-in functionality. Retested the patch on Power 8 LE/BE, Power 9LE/BE and
Power 10 LE with no regressions.
The following patch cleans u
On Mon, 2023-08-07 at 17:18 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Sorry for the late review.
>
> on 2023/8/2 02:29, Carl Love wrote:
> > GCC maintainers:
> >
> > Ver 2: Re-worked the test vec-cmpne.c to create a compile only
> > test
> > verify t
GCC maintainers:
Ver 3: Updated description to make it clear the patch fixes the
confusion on the availability of the builtins. Fixed the dg-require-
effective-target on the test cases and the dg-options. Change the test
case so the for loop for the test will not be unrolled. Fixed a
spelling
Kewen:
On Wed, 2023-08-09 at 16:47 +0800, Kewen.Lin wrote:
> > Patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10
> > LE
> > with no regressions.
>
> Okay for trunk with two nits below fixed, thanks!
Thanks for all the help with the patch. Fixed the nits below, compiled
and re
/BE.
Please let me know if the patch is acceptable for mainline. Thanks.
Carl Love
--
rs6000, add overloaded DFP quantize support
Add decimal floating point (DFP) quantize built-ins for both 64-bit DFP
and 128-DFP operands. In each case
let me know if the patch is acceptable for mainline. Thanks.
Carl Love
--
[PATCH] rs6000, add overloaded DFP quantize support
Add decimal floating point (DFP) quantize built-ins for both 64-bit DFP
and 128-DFP operands. In each
On Thu, 2023-06-15 at 14:23 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/6/15 04:37, Carl Love wrote:
> > Kewen, GCC maintainers:
> >
> > Version 4, added missing cases for new xxexpqp, xsxexpdp and
> > xsxsigqp
> > cases to rs6000_expand_builtin. Mer
Kewen, GCC maintainers:
Version 5, Tested the patch on P9 BE per request. Fixed up test case
to get the correct expected values for BE and LE. Fixed typos.
Updated the doc/extend.texi to clarify the vector arguments. Changed
test file names per request. Moved builtin defs next to related
defi
GCC maintainers:
The GLibC team requested a builtin to replace the mffscrn and mffscrniinline
asm instructions in the GLibC code. Previously there was discussion on adding
builtins for the mffscrn instructions.
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620261.html
In the end, it was
Kewen:
On Mon, 2023-06-19 at 14:08 +0800, Kewen.Lin wrote:
> >
> Hi Carl,
>
> on 2023/6/17 01:57, Carl Love wrote:
> > overloaded instance. Update comments.
> > * config/rs6000/rs6000-overload.def
> > (__builtin_vec_scalar_insert_exp): Add
Kewen, GCC maintainers:
Version 6, Fixed missing change log entry. Changed builtin id names as
requested. Missed making the change on the last version. Fixed
comment in the three test cases. Reran regression suite on Power 10,
no regressions.
Version 5, Tested the patch on P9 BE per request
On Mon, 2023-06-19 at 15:17 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/31 04:46, Carl Love wrote:
> > GCC maintainers:
> >
> > The following patch takes the tests in vsx-vector-6-p7.h, vsx-
> > vector-
> > 6-p8.h, vsx-vector-6-p9.h and reorga
GCC maintainers:
Ver 2. Switched to using code macros to generate the call to the
builtin and test the results. Added in instruction counts for the key
instruction for the builtin. Moved the tests into an additional
function call to ensure the compile doesn't replace the builtin call
code wit
Kewen:
On Wed, 2023-06-28 at 16:35 +0800, Kewen.Lin wrote:
> > Yea, I was going with a runnable test and didn't include the
> > instruction counts. Added back in. Rather then doing by processor
> > version (P8, P9, P10) I was able to do it by BE/LE. The
> > instruction
> > counts were the same
GCC maintainers:
Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
of the scan-assembler-times checks to cover multiple similar
instructions. Change the function check macro to a macro to generate a
function to do the test and check the results. Retested on the various
proce
Kewen:
On Fri, 2023-06-30 at 11:37 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/6/30 05:36, Carl Love wrote:
> > Kewen:
> >
> > On Wed, 2023-06-28 at 16:35 +0800, Kewen.Lin wrote:
> > > > Yea, I was going with a runnable test and didn't include th
Kewen:
On Fri, 2023-06-30 at 15:20 -0700, Carl Love wrote:
> So, went to look at the assembly to verify my comment on the
> difference
> being related to the loads. I decided to actually count the
> instructions just to verify the number in the assembly files.
> Before,
> I
GCC maintainers:
Ver 2, Went back thru the requirements and emails. Not sure where I
came up with the requirement for an overloaded version with double
argument. Removed the overloaded version with the double argument.
Added the macro to announce if the __builtin_set_fpscr_rn returns a
void
Kewen:
On Fri, 2023-06-30 at 15:20 -0700, Carl Love wrote:
> Segher never liked the above way of looking at the assembly. He
> prefers:
> gcc -S -g -mcpu=power8 -o vsx-vector-6-func-2lop.s vsx-vector-6-
> func-
> 2lop.c
>
> grep xxlor vsx-vector-6-func-2lop.s | wc
>
Kewen:
On Tue, 2023-07-04 at 10:49 +0800, Kewen.Lin wrote:
>
> >
> > The tests are broken up into a seriers of files for related
> > tests. The
>
> s/seriers/series/
Fixed
>
> > new tests are runnable tests to verify the builtin argument types
> > and the
> > functional correctness of ea
GCC maintainers:
Ver 4. Fixed a few typos. Redid the tests to create separate run and
compile tests.
Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
of the scan-assembler-times checks to cover multiple similar
instructions. Change the function check macro to a macro to ge
Kewen:
On Mon, 2023-06-19 at 11:50 +0800, Kewen.Lin wrote:
> > generated the vinsd instruction for the two calls with the first
> > argument of unsigned long long int. When the first argument of the
> > builtin is changed to the correct type, vector unsigned char the
> > builtin generates the vin
GCC maintainers:
Version 3, added code to altivec_resolve_overloaded_builtin so the
correct instruction is selected for the size of the second argument.
This restores the instruction counts to the original values where the
correct instructions were originally being generated. The naming of
the
On Fri, 2023-07-07 at 10:15 +0800, Kewen.Lin wrote:
>
> > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-compile.c
> > new file mode 100644
> > index 000..6b7d73ed66c
> > --- /dev/null
> >
GCC maintainers:
Ver 5. Removed -compile from the names of the compile only tests. Fixed
up the reference to the compile file names in the .h file headers.
Replaced powerpc_vsx_ok with vsx_hw in the run test files. Removed the
-save-temps from all files. Retested on all of the various platfor
On Thu, 2023-07-06 at 17:54 -0500, Peter Bergner wrote:
> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
> > rs6000, __builtin_set_fpscr_rn add retrun value
>
> s/retrun/return/
>
> Maybe better written as:
>
> rs6000: Add return value to __builtin_set_fpscr
On Fri, 2023-07-07 at 12:06 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Some more minor comments are inline below on top of Peter's
> insightful
> review comments.
>
> on 2023/7/1 08:58, Carl Love wrote:
> > GCC maintainers:
> >
> > Ver 2, Went back thru
GCC maintainers:
Ver 3, Renamed the patch per comments on ver 2. Previous subject line
was " [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value".
Fixed spelling mistakes and formatting. Updated define_expand
"rs6000_set_fpscr_rn to have the rs6000_get_fpscr_fields and
rs6000_updat
Peter:
On Mon, 2023-07-10 at 16:57 -0500, Peter Bergner wrote:
> On 7/10/23 2:18 PM, Carl Love wrote:
> > + /* Get the current FPSCR fields, bits 29:31 (DRN) and bits 56:63
> > (VE, OE, UE,
> > + ZE, XE, NI, RN) from the FPSCR and return them. */
>
> The '
On Tue, 2023-07-11 at 13:54 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> Excepting for Peter's review comments, some nits are inline below.
>
> on 2023/7/11 03:18, Carl Love wrote:
> > GCC maintainers:
> >
> >
> >
> > --
GCC maintainers:
Ver 4, Removed extra space in subject line. Added comment to commit
log comments about new __SET_FPSCR_RN_RETURNS_FPSCR__ define. Changed
Added to Add and Renamed to Rename in ChangeLog. Updated define_expand
"rs6000_set_fpscr_rn" per Peter's comments to use new temporary
regis
GCC maintainers:
The following patch fixes errors in the arguments in the
__builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx builtin
definitions. Note, these builtins are used by the overloaded
__builtin_vec_xst_trunc builtin.
The patch adds a new overloaded builtin definition for
__bu
GCC maintainers:
version 2. Fixed an issue with the test case. The dg-options line was
missing.
The following patch adds an overloaded builtin. There are two possible
arguments for the builtin. The builtin definitions are:
double __builtin_mffscrn (unsigned long int);
double __builtin_mf
Peter:
On Thu, 2023-05-18 at 16:28 -0500, Peter Bergner wrote:
>
>
> > + void __builtin_vec_xst_trunc (vsq, signed long long, signed long
> > *);
> > +TR_STXVRLX TR_STXVRLX_S
> > + void __builtin_vec_xst_trunc (vuq, signed long long, unsigned
> > long *);
> > +TR_STXVRLX TR_STXVRL
On Mon, 2023-05-22 at 14:36 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/19 05:12, Carl Love via Gcc-patches wrote:
> > GCC maintainers:
> >
> > version 2. Fixed an issue with the test case. The dg-options line
> > was
> > missing.
> >
>
Kewen, Segher, GCC maintainers:
Version 3, fixed various issues noted by Kewen. Retested on Power 10.
No regression issues.
Version 2, Fixed an issue with the test case. The dg-options line was
missing.
The following patch adds an overloaded builtin. There are two possible
arguments for the
On Mon, 2023-05-22 at 17:04 +0800, Kewen.Lin wrote:
> Hi Carl,
>
> on 2023/5/11 02:06, Carl Love via Gcc-patches wrote:
> > GCC maintainers:
> >
> > The following patch fixes errors in the arguments in the
> > __builtin_altivec_tr_stxvrhx, __built
Kewen, GCC maintainers:
Version 2, addressed comments from Kewen. Added an additional
overloaded builtin:
void __builtin_vec_xst_trunc (vuq, signed long long, long *);
The following patch fixes errors in the arguments in the
__builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx built
On Wed, 2023-05-24 at 13:32 +0800, Kewen.Lin wrote:
> on 2023/5/24 06:30, Peter Bergner wrote:
> > On 5/23/23 12:24 AM, Kewen.Lin wrote:
> > > on 2023/5/23 01:31, Carl Love wrote:
> > > > The builtins were requested for use in GLibC. As of version
> > > &
Peter, Kewen:
On Thu, 2023-05-25 at 13:28 +0800, Kewen.Lin wrote:
> on 2023/5/24 23:20, Carl Love wrote:
> > On Wed, 2023-05-24 at 13:32 +0800, Kewen.Lin wrote:
> > > on 2023/5/24 06:30, Peter Bergner wrote:
> > > > On 5/23/23 12:24 AM, Kewen.Lin wrote:
> >
regression errors. The new tests have been manually compiled and
run on mambo to ensure they work correctly.
Please review the patches and let me know if they are acceptable for
mainline. Thanks.
Carl Love
ER10.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
The P10 test was run by hand on Mambo.
Carl Love
---
gcc/ChangeLog
2020-09-21 Carl Love
* con
Will.
Carl Love
---
gcc/ChangeLog
2020-09-21 Carl Love
* config/rs6000/altivec.h (vec_signextll, vec_signexti): Add define
for new builtins.
* config/rs6000/rs6000-builtin.def (VSIGNEXTI, VSIGNEXTLL): Add
it in the dg-require command.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
The P10 test was run by hand on Mambo.
Carl Love
---
gcc/ChangeLog
2020-09-2
fixunskfti-sw.c about changes made from the original
file fixunskfti.c.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
The P10 tests were run by hand on Mambo.
Carl Love
t use UNSPEC.
Test suite program cleanups, removed "//" comments that were not
needed.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
The P10 test was run by hand on Mambo.
---
gcc/ChangeLog
2020-10-05 Carl Love
* config/rs6000/altivec.h (vec_signextll, vec_signexti): Add define
for new builtins.
* config/rs6000/rs6000-builtin.def (VSIGNEXTI, VSIGNEXTLL): Add
overloaded builtin
if it looks OK to commit to mainline.
Carl
--
gcc/ChangeLog
2020-10-05 Carl Love
* config/rs6000/altivec.h (vec_rlnm): Fix bug in argument generation.
---
gcc/config/rs6000/altivec.h | 2 +-
1 file chang
OK to commit to mainline.
Carl
-
gcc/ChangeLog
2020-10-05 Carl Love
* config/rs6000/altivec.md (altivec_vslq, altivec_vsrq):
Rename to altivec_vslq_, altivec_vsrq_, mode VEC_TI.
* config/rs6000/vector.md
20-10/05 Carl Love
* config/rs6000/altivec.h (vec_signextq, vec_dive, vec_mod): Add define
for new builtins.
* config/rs6000/altivec.md (UNSPEC_VMULEUD, UNSPEC_VMULESD,
UNSPEC_VMULOUD, UNSPEC_VMULOSD): New unspecs.
(altivec_eqv1ti, altivec_gtv1ti, altivec_gt
/ChangeLog
2020-10-05 Carl Love
* config/rs6000/rs6000.md (floatti2, floatunsti2,
fix_truncti2, fixuns_truncti2): Add
define_insn for mode IEEE 128.
* libgcc/config/rs6000/fixkfti.c: Renamed to fixkfti-sw.c.
Update source function name. White space fixes
this is ready for mainline.
Carl
--
gcc/ChangeLog
2020-10-05 Carl Love
* config/rs6000/dfp.md (floattitd2, fixtdti2): New define_insns.
* config/rs6000/rs6000-call.c (P10V_BUILTIN_VCMP
David:
>
> Hi, Carl
>
> I thought that vector.md was a transfer vector for the patterns and
> instructions were defined in vsx.md. Why are the new insn patterns
> defined in vector.md?
I am a bit of a newbie here. I wasn't aware of any specific guide
lines on the vector instructions. I put
no regressions. Additionally the new test case was compiled and
executed by hand on Mambo to verify the test case passes.
Please let me know if this patch is acceptable for mainline. Thanks.
Carl Love
--
2020-11-02
let me know if the patch looks OK for mainline. Thanks.
Carl
-
The effective target for a Power 9 runnable test should be
p9vector_hw.
2021-06-11 Carl Love
gcc/testsuite/ChangeLog
* gcc.target/powerpc/check-builtin-vec_rlnm
what the new functionality will be.
The following five patches have minor fixes to the builtin
descriptions, typo fixes, etc. from the previous iteration. The patch
series numbers have changed.
Carl Love
(Power 10 LE)
Please let me know if the patch is acceptable for mainline.
Carl Love
2021-04-26 Carl Love
gcc/
* config/rs6000/altivec.md (altivec_vrlmi): Fix
bug in argument generation.
gcc/testsuite
if the patch is acceptable for mainline.
Carl Love
gcc/ChangeLog
dje@gmail.com, gcc-patches@gcc.gnu.org, Bill Schmidt
, Peter Bergner ,
2021-04-26 Carl Love
* config/rs6000/dfp.md (floattitd2, fixtdti2): New
LE)
Please let me know if the patch is acceptable for mainline.
Carl Love
---
gcc/ChangeLog
2021-04-26 Carl Love
* config/rs6000/altivec.h (vec_dive, vec_mod): Add define for new
builtins
(Power 8 BE)
powerpc64-linux instead (Power 9 LE)
powerpc64-linux instead (Power 10 LE)
Please let me know if the patch is acceptable for mainline.
Carl Love
gcc/ChangeLog
2021-04-26 Carl Love
* config/rs6000
(Power 9 LE)
powerpc64-linux instead (Power 10 LE)
Please let me know if the patch is acceptable for mainline.
Carl Love
gcc/ChangeLog
2021-04-26 Carl Love
* config/rs6000/rs6000.md (floatti2, floatunsti2
testing was done by generating the BE code sequence and
then manually using gdb and visual inspection to make sure the elements
were correctly reversed and the expected elements were sign extended.
Please let me know if the patch is acceptable for mainline.
Carl Love
On Tue, 2021-04-27 at 18:46 -0500, will schmidt wrote:
> On Mon, 2021-04-26 at 09:35 -0700, Carl Love wrote:
> > Will, Segher:
> >
> > This patch fixes the order of the argument in the vec_rlmi and
> > vec_rlnm builtins. The patch also adds a new test cases to verif
Kewen, Peter:
> on 2023/8/17 08:19, Carl Love wrote:
> > GCC maintainers:
> >
> > Version 2, renamed the built-in instances. Changed the name of the
> > overloaded built-in. Added the missing documentation for the new
> > built-ins. Fixed typos. Chang
w builtins.
The Patch has been tested on Power 10LE and Power 9 LE/BE.
Please let me know if the patch is acceptable for mainline. Thanks.
Carl Love
---
rs6000, add overloaded DFP quantize support
Add decimal floating point (DFP) quantize
On Mon, 2023-08-28 at 10:21 +0800, Kewen.Lin wrote:
> Hi Carl,
> >
> > A testcase is added for the new built-in definitions.
> >
> > gcc/ChangeLog:
> > * config/rs6000/dfp.md: New UNSPEC_DQUAN.
>
> Nit: (UNSPEC_DQUAN): New unspec.
Fixed.
>
> > +(define_insn "dfp_dqua_"
> > + [(set
uctions on rs6000. The built-ins are for 64-bit
and 128-bit DFP operands.
The patch also adds a test case for the new builtins.
The Patch has been tested on Power 10LE and Power 9 LE/BE.
Please let me know if the patch is acceptable for mainline. Thanks.
Kewen:
On Tue, 2023-08-29 at 16:54 +0800, Kewen.Lin wrote:
> > The following functions require @option{-mhard-float},
> > diff --git a/gcc/testsuite/gcc.target/powerpc/pr93448.c
> > b/gcc/testsuite/gcc.target/powerpc/pr93448.c
> > new file mode 100644
> > index 000..f9c388585d7
> > --- /
patches have been tested on Power 8 and Power 9 to ensure there are
no regression errors. The new tests have been manually compiled and
run on mambo to ensure they work correctly.
Please review the patches and let me know if they are acceptable for
mainline. Thanks.
Carl Love
Segher, Will:
Path 3 adds support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
Carl Love
Add TI to TD (128-bit DFP) and TD to TI support
gcc/ChangeLog
2020-08-10 Carl
Segher, Will:
Patch 4 adds 128-bit integer shift instruction support.
Carl Love
-
Test 128-bit shifts for just the int128 type.
gcc/ChangeLog
2020-08-10 Carl Love
* config/rs6000/altivec.md (altivec_vslq
.
Carl
---
Conversions between 128-bit integer and floating point values.
gcc/ChangeLog
2020-08-10 Carl Love
config/rs6000/rs6000.md (floatunsti2,
fix_truncti2, fixuns_truncti2): Add
define_insn for mode IEEE 128
Segher, Will:
Patch 2, adds support for divide, modulo, shift, compare of 128-bit
integers. The support adds the instruction and builtin support.
Carl Love
---
rs6000, 128-bit multiply, divide, shift, compare
gcc/ChangeLog
Segher, Will:
Patch 1, adds the sign extension instruction support and corresponding
builtins.
Carl Love
-
RS6000 Add 128-bit sign extension support
gcc/ChangeLog
2020-08-10 Carl Love
* config/rs6000
ower 8 LE)
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regressions.
Please let me know if the patch is acceptable for trunk.
Carl Love
-
[PATCH] rs6000, restrict bfloat convert intrinsic t
Segher:
On Thu, 2020-08-13 at 12:36 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Aug 11, 2020 at 12:22:37PM -0700, Carl Love wrote:
> > +/* Sign extend builtins that work on ISA 3.0, but not defined
> > until ISA 3.1. */
>
> What does this mean? Not defined
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