[PATCH 3/12 V2] arm: Add option -mbranch-protection

Richard Earnshaw writes: [...] > +@item > +-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]] > +@opindex mbranch-protection > +Enable branch protection features (armv8.1-m.main only). > +@samp{none} generate code without b

Re: [PATCH 4/12] arm: Add testsuite library support for PACBTI target

Richard Earnshaw writes: > On 01/07/2022 14:03, Richard Earnshaw via Gcc-patches wrote: >> On 28/04/2022 10:40, Andrea Corallo via Gcc-patches wrote: >>> Add targeting-checking entities for PACBTI in testsuite >>> framework. >>> >>> Pre-approv

[PATCH 5/12 V2] arm: Implement target feature macros for PACBTI

Richard Earnshaw writes: > On 28/04/2022 10:42, Andrea Corallo via Gcc-patches wrote: >> This patch implements target feature macros when PACBTI is enabled >> through the -march option or -mbranch-protection. The target feature >> macros __ARM_FEATURE_PAC_DEFAULT and __AR

[PATCH 7/12 V2] arm: Emit build attributes for PACBTI target feature

Richard Earnshaw writes: > On 28/04/2022 10:45, Andrea Corallo via Gcc-patches wrote: >> This patch emits assembler directives for PACBTI build attributes as >> defined by the >> ABI. >> <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/a

[PATCH 8/12 V3] arm: Introduce multilibs for PACBTI target feature

Richard Earnshaw writes: [...] >> The documentation mentions -mbranch-protection=standard+leaf, so >> you're missing a mapping for that. >> OK with that change. >> R. > > Oh, and please add some tests to gcc/testsuite/gcc.target/arm/multilib.exp > > R. Hi Richard, thanks, here the updated patc

[PATCH 9/12 V2] arm: Make libgcc bti compatible

Richard Earnshaw writes: > On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote: >> This change add bti instructions at the beginning of arm specific >> libgcc hand written assembly routines. >> 2022-03-31 Andrea Corallo >> * libgcc/config/arm/c

[PATCH 5/12 V3] arm: Implement target feature macros for PACBTI

Hi Richard, thanks for reviewing. Richard Earnshaw writes: [...] > diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c > b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c > new file mode 100644 > index 000..311cf572dd9 > --- /dev/null > +++ b/gcc/testsuite/gcc.ta

[PATCH 5/12 V4] arm: Implement target feature macros for PACBTI

Andrea Corallo via Gcc-patches writes: > Hi Richard, > > thanks for reviewing. > > Richard Earnshaw writes: > > [...] > >> diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c >> b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c >>

[PATCH 7/12 V2] arm: Emit build attributes for PACBTI target feature

Richard Earnshaw writes: > On 28/04/2022 10:45, Andrea Corallo via Gcc-patches wrote: >> This patch emits assembler directives for PACBTI build attributes as >> defined by the >> ABI. >> <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/a

Re: [PATCH 9/12 V2] arm: Make libgcc bti compatible

Richard Earnshaw writes: > On 21/07/2022 10:17, Andrea Corallo via Gcc-patches wrote: >> Richard Earnshaw writes: >> >>> On 28/04/2022 10:48, Andrea Corallo via Gcc-patches wrote: >>>> This change add bti instructions at the beginning of arm specific >&g

Re: [PATCH 10/12 V2] arm: Implement cortex-M return signing address codegen

Richard Earnshaw writes: [...] > +(define_insn "pac_nop" > + [(set (reg:SI IP_REGNUM) > + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] > + UNSPEC_PAC_NOP))] > + "TARGET_THUMB2" > + "pac\t%|ip, %|lr, %|sp" > + [(set_attr "length" "2")]) > > This pattern is missing

Re: [PATCH] [arm] complete vmsr/vmrs blank and case adjustments

Alexandre Oliva writes: > Back in September last year, some of the vmsr and vmrs patterns had an > extraneous blank removed, and the case of register names lowered, but > another instance remained, and so did a few testcases. [...] Hi Alexandre, I'm not approver but LGTM, thanks for fixing thi

Re: [PATCH] [PR104882] [arm] require mve hw for mve run test

Alexandre Oliva via Gcc-patches writes: > The pr104882.c test is an execution test, but arm_v8_1m_mve_ok only > tests for compile-time support. Add a requirement for mve hardware. > > Regstrapped on x86_64-linux-gnu. > Tested on arm-vxworks7 (gcc-12) and arm-eabi (trunk). Ok to install? > > for

Re: [PATCH] arm: [testuiste] fix ivopts.c target test [PR96372]

Kyrylo Tkachov writes: [...] > Ah ok, then it's fine to be consistent. > The patch is ok. > Thanks, > Kyrill Thanks, into master as 0568f801eff Andrea

[PATCH] arm: Low overhead loop handle long range branches [PR98931]

Hi all, this is to fix PR98931 where the LE (loop end, Armv8.1-M low overhead loops) instruction cannot cover sufficently long branches. In this case we emit as an alternative: subslr, #1 bne label arm-none-eabi regtested, arm-none-linux-gnueabihf boostrapped. Okay for

Re: [PATCH v2] arm: Low overhead loop handle long range branches [PR98931]

Jakub Jelinek writes: > On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek via Gcc-patches wrote: >> >"TARGET_32BIT && TARGET_HAVE_LOB" >> > - "le\t%|lr, %l0") >> > + "* >> > + if (get_attr_length (insn) == 4) >> > +return \"le\\t%|lr, %l0\"; >> > + else >> > +return \"subs\\

Re: [PATCH v2] arm: Low overhead loop handle long range branches [PR98931]

"Richard Earnshaw (lists)" writes: > On 09/02/2021 16:27, Andrea Corallo via Gcc-patches wrote: >> Jakub Jelinek writes: >> >>> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek via Gcc-patches >>> wrote: >>>>>

[PATCH v3] arm: Low overhead loop handle long range branches [PR98931]

Andrea Corallo via Gcc-patches writes: > "Richard Earnshaw (lists)" writes: > >> On 09/02/2021 16:27, Andrea Corallo via Gcc-patches wrote: >>> Jakub Jelinek writes: >>> >>>> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek

Re: [PATCH v3] arm: Low overhead loop handle long range branches [PR98931]

"Richard Earnshaw (lists)" writes: [...] > + [(set (attr "length") > +(if_then_else > +(lt (minus (pc) (match_dup 0)) (const_int 1024)) > + (const_int 4) > + (const_int 6))) > + (set_attr "type" "branch")]) > > Shouldn't that be using "ltu" rather than "lt"

Re: [committed] jit: fix ICE on BUILT_IN_TRAP [PR99126]

David Malcolm via Gcc-patches writes: > I tried several approaches to fixing this; this seemed the > least invasive. Hi Dave, thanks for fixing this. I do have a trivial question: are we guaranteed that the middle-end will not try to add any build-in other than a trap? Regards Andrea

Re: [committed] jit: fix ICE on BUILT_IN_TRAP [PR99126]

Andrea Corallo via Gcc-patches writes: > David Malcolm via Gcc-patches writes: > >> I tried several approaches to fixing this; this seemed the >> least invasive. > > Hi Dave, > > thanks for fixing this. > > I do have a trivial question: are we guaranteed t

Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead Loop tests

Andrea Corallo writes: > Hi all, > > I'd like to submit the following patch to fix PR96375 ([11 regression] > arm/lob[2-5].c fail on some configurations). > > It fix the observed regression making sure -mthumb is always used and > allowing Low Overhead Loop tests to be executed only on cortex-M p

Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead Loop tests

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 01 October 2020 15:36 >> To: gcc-patches@gcc.gnu.org >> Cc: Richard Earnshaw ; Kyrylo Tkachov >> ; Christophe Lyon >> Subject: Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead >> Loop tests >>

[PATCH 10/15 V2] arm: Implement cortex-M return signing address codegen

Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stac

[PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Hi all, ping^2 for patches 9/15 7/15 11/15 12/15 and 10/15 V2 of this series. Andrea

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Kyrylo Tkachov writes: > Hi Andrea, > >> -Original Message- >> From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Andrea >> Corallo via Gcc-patches >> Sent: Friday, August 12, 2022 4:34 PM >> To: Andrea Corallo via

[PATCH] Don't ICE running selftests if errors were raised [PR99723]

Hi all this is to address PR 99723. In the PR GCC crashes as the initialization of common trees is not performed as no compilation is happening, this is because we raise an error earlier while processing the arch flags. This patch changes the code to execute selftests only if no errors where rai

[PATCH] arm: Define __ARM_FEATURE_AES and __ARM_FEATURE_SHA2 when march +crypto is selected

Hi all, this patch fixes the missing definition of __ARM_FEATURE_AES and __ARM_FEATURE_SHA2 when AES SHA1 & SHA2 crypto instructions are available [1] (read when march +crypto is selected). Okay for master? Thanks Andrea [1]

Re: [PATCH] arm: Define __ARM_FEATURE_AES and __ARM_FEATURE_SHA2 when march +crypto is selected

Kyrylo Tkachov writes: > Hi Andrea, > >> -Original Message- >> From: Andrea Corallo >> Sent: Wednesday, September 28, 2022 1:19 PM >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; Andrea Corallo >> Subject: [PATCH] arm: Define __ARM_FEATURE_AES and >> __ARM_F

[PATCH 12/15 V2] arm: implement bti injection

Kyrylo Tkachov writes: > Hi Andrea, [...] > diff --git a/gcc/config/arm/aarch-bti-insert.cc > b/gcc/config/arm/aarch-bti-insert.cc > index 2d1d2e334a9..8f045c247bf 100644 > --- a/gcc/config/arm/aarch-bti-insert.cc > +++ b/gcc/config/arm/aarch-bti-insert.cc > @@ -41,6 +41,7 @@ > #include "cfgr

Re: [PATCH] Don't ICE running selftests if errors were raised [PR99723]

Jeff Law via Gcc-patches writes: > On 9/27/22 09:12, Andrea Corallo via Gcc-patches wrote: >> Hi all >> >> this is to address PR 99723. >> >> In the PR GCC crashes as the initialization of common trees is not >> performed as no compilation is happenin

Re: [PATCH][pushed] jit: Initialize function::m_blocks in ctor

Martin Liška writes: > This resolves the problem reported here: > https://mail.gnu.org/archive/html/bug-gnu-emacs/2021-11/msg00606.html > https://bugzilla.opensuse.org/show_bug.cgi?id=1192951 > > I'm going to push it as obvious. > > Martin Hi Martin, thanks for the fix! Question: that piece of

Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch enables address return signature and verification based on > Armv8.1-M Pointer Authentication [1]. > > To sign the return address, we use the PAC R12, LR, SP instruction > upon function entry. This is si

Re: [PATCH][pushed] jit: Initialize function::m_blocks in ctor

Martin Liška writes: [...] >> Question: that piece of code is there since 2014, should we >> back-port >> the fix as well? > > I've just pushed to to all active code streams (master, > releases/gcc-{9,10,11}). Wonderful, thanks again. Andrea

Re: [Patch 1/8, Arm, AArch64, GCC] Refactor mbranch-protection option parsing and make it common to AArch32 and AArch64 backends. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

Tejas Belagod via Gcc-patches writes: > Ping for this series. > > Thanks, > Tejas. Hi all, pinging this series. BR Andrea

Re: [Patch 1/8, Arm, AArch64, GCC] Refactor mbranch-protection option parsing and make it common to AArch32 and AArch64 backends. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

Richard Earnshaw writes: > On 30/11/2021 11:11, Andrea Corallo via Gcc-patches wrote: >> Tejas Belagod via Gcc-patches writes: >> >>> Ping for this series. >>> >>> Thanks, >>> Tejas. >> Hi all, >> pinging this series. >> B

Re: [Patch 3/8, Arm, GCC] Add option -mbranch-protection. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

Richard Earnshaw via Gcc-patches writes: [...] >> Thanks for the reviews. >> Add -mbranch-protection option. This option enables the >> code-generation of >> pointer signing and authentication instructions in function prologues and >> epilogues. >> 2021-10-25 Tejas Belagod >> gcc/ChangeLog:

Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen

Andrea Corallo via Gcc-patches writes: > Andrea Corallo via Gcc-patches writes: > >> Hi all, >> >> this patch enables address return signature and verification based on >> Armv8.1-M Pointer Authentication [1]. >> >> To sign the return address, we u

[Patch 6/8 V2] Arm: Add pointer authentication for stack-unwinding runtime.

Richard Earnshaw via Gcc-patches writes: > On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: >> >>> -Original Message- >>> From: Gcc-patches >> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via >>> Gcc-patches >>> Sent: Friday, October 8, 2021 1:18 PM >>> To

Re: [Patch 8/8, Arm, GCC] Introduce multilibs for PACBTI target feature. [Was RE: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI target feature.]

Richard Earnshaw via Gcc-patches writes: > On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: >> >>> -Original Message- >>> From: Gcc-patches >> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via >>> Gcc-patches >>> Sent: Friday, October 8, 2021 1:19 PM >>> To

Re: [Patch 6/8 V2] Arm: Add pointer authentication for stack-unwinding runtime.

Richard Earnshaw writes: > On 09/12/2021 17:36, Andrea Corallo via Gcc-patches wrote: >> Richard Earnshaw via Gcc-patches writes: >> >>> On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: >>>> >>>>> -Original Message- &

Re: [Patch 7/8 V2] Arm: Emit build attributes for PACBTI target feature.

Richard Earnshaw via Gcc-patches writes: > On 28/10/2021 12:43, Tejas Belagod via Gcc-patches wrote: >> >>> -Original Message- >>> From: Gcc-patches >> bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via >>> Gcc-patches >>> Sent: Friday, October 8, 2021 1:19 PM >>> To

Re: [PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Richard Earnshaw writes: > On 21/09/2022 09:07, Andrea Corallo via Gcc-patches wrote: >> Hi all, >> ping^2 for patches 9/15 7/15 11/15 12/15 and 10/15 V2 of this >> series. >>Andrea > > Subject says xx/15, but I only see 1-12 from you. > > R. Yeah

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Richard Earnshaw writes: > On 27/09/2022 16:24, Kyrylo Tkachov via Gcc-patches wrote: >> >>> -Original Message- >>> From: Andrea Corallo >>> Sent: Tuesday, September 27, 2022 11:06 AM >>> To: Kyrylo Tkachov >>> Cc: Andr

Re: [PATCH 10/15 V2] arm: Implement cortex-M return signing address codegen

Richard Earnshaw writes: > On 14/09/2022 15:20, Andrea Corallo via Gcc-patches wrote: >> Hi all, >> >> this patch enables address return signature and verification based on >> Armv8.1-M Pointer Authentication [1]. >> >> To sign the return address, we use

[PATCH 10/15 V3] arm: Implement cortex-M return signing address codegen

Hi all, the third iteration of this patch is attached addresing review comments. Thanks Andrea >From b42e28be75f374a4e1a5943c8c9002e07dbcc567 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 20 Jan 2022 15:36:23 +0100 Subject: [PATCH] [PATCH 10/15] arm: Implement cortex-M return sign

[PATCH 12/15 V3] arm: implement bti injection

Hi all, please find attached the third iteration of this patch addresing review comments. Thanks Andrea >From e3001bd662b84dafeca200b52fc644b7bf81c4af Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 7 Apr 2022 11:51:56 +0200 Subject: [PATCH] [PATCH 12/15] arm: implement bti injectio

[PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Hi all, as I respinned few patches, dropped one and added another, I'm reposting this series thant enables return address verification and branch target identification based on Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1] for Arm Cortex-M. This feature is contro

[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64

Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the mo

[PATCH 2/15] arm: Add Armv8.1-M Mainline target feature +pacbti

This patch adds the -march feature +pacbti to Armv8.1-M Mainline. This feature enables pointer signing and authentication instructions on M-class architectures. Pre-approved here . gcc/Changelog: * config/arm/arm.h (TAR

[PATCH 3/15] arm: Add option -mbranch-protection

Hi all, this adds -mbranch-protection option. This option enables the code-generation of pointer signing and authentication instructions in function prologues and epilogues. gcc/ChangeLog: * config/arm/arm.c (arm_configure_build_target): Parse and validate -mbranch-protection op

[PATCH 4/15] arm: Add testsuite library support for PACBTI target

Hi all, this adds targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested changes here . gcc/testsuite/ChangeLog: * testsuite/lib/target-supports.exp: (check_effective_tar

[PATCH 5/15] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE

[PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtime

Hi all, this patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feat

[PATCH 7/15] arm: Emit build attributes for PACBTI target feature

This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emit EABI attributes for Tag_PAC_extension, Tag_BTI_extensi

[PATCH 8/15] arm: Introduce multilibs for PACBTI target feature

This patch add the following new multilibs. thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+fp/mbranch-protection/ha

[PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Hi all, this patch enables 'arm_emit_multi_reg_pop' to set again the stack pointer as CFA reg when popping if this is necessary. /gcc/ * config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointer was set define again the stack pointer as CFA reg when popping. diff --git a/

[PATCH 10/15] arm: Implement cortex-M return signing address codegen

Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stac

[PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. The original patch was approved here: . After that Richard E. note

[PATCH 12/15] arm: implement bti injection

Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads target

Re: [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Andrea Corallo via Gcc-patches writes: > Hi all, > > as I respinned few patches, dropped one and added another, I'm reposting > this series thant enables return address verification and branch target > identification based on Armv8.1-M Pointer Authentication and Branch >

[PATCH] contrib: Fix a typo in contrib/git-fetch-vendor.sh

Hi all, just commited this to fix a typo as obvious. Bests Andrea /contrib/ChangeLog: * git-fetch-vendor.sh : Fix typo. diff --git a/contrib/git-fetch-vendor.sh b/contrib/git-fetch-vendor.sh index 15303629b5c..bbd52fb2055 100755 --- a/contrib/git-fetch-vendor.sh +++ b/contrib/git-fe

Re: [PATCH V2] arm: add -static-pie support

Lance Fredrickson via Gcc-patches writes: > Yes, this is a 1st submission. > Yes, I guess I was going for DCO rules. > I will look at running the test suite. Does this need to be done on > the target? because my arm target is a measly dual core 1ghz embedded > chip and low ram. Netgear R7000 rout

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch enables 'arm_emit_multi_reg_pop' to set again the stack > pointer as CFA reg when popping if this is necessary. > > /gcc/ > > * config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointe

Re: [PATCH 7/15] arm: Emit build attributes for PACBTI target feature

Andrea Corallo via Gcc-patches writes: > This patch emits assembler directives for PACBTI build attributes as > defined by the > ABI. > > <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf> > > gcc/ChangeLog: > > * config/arm/

Re: [PATCH 10/15] arm: Implement cortex-M return signing address codegen

Ping Andrea

Re: [PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch splits and restructures the aarch64 bti pass code in order > to have it usable by the arm backend as well. These changes have no > functional impact. > > The original patch was approved here: > <https:

Re: [PATCH 12/15] arm: implement bti injection

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch enables Branch Target Identification Armv8.1-M Mechanism > [1]. > > This is achieved by using the bti pass made common with Aarch64. > > The pass iterates through the instructions and adds the necessary B

[PATCH 0/12] arm: Enables return address verification and branch target identification on Cortex-M

Hi all, this series enables return address verification and branch target identification based on Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1] for Arm Cortex-M. This feature is controlled by the newly introduced '-mbranch-protection' option, contextually the Arm

[PATCH 1/12] arm: Make mbranch-protection opts parsing common to AArch32/64

Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the mo

[PATCH 2/12] arm: Add Armv8.1-M Mainline target feature +pacbti

This patch adds the -march feature +pacbti to Armv8.1-M Mainline. This feature enables pointer signing and authentication instructions on M-class architectures. Pre-approved here . gcc/Changelog: * config/arm/arm.h (TA

[PATCH 3/12] arm: Add option -mbranch-protection

[PATCH 3/12] arm: Add option -mbranch-protection Add -mbranch-protection option. This option enables the code-generation of pointer signing and authentication instructions in function prologues and epilogues. gcc/ChangeLog: * config/arm/arm.c (arm_configure_build_target): Parse and vali

[PATCH 4/12] arm: Add testsuite library support for PACBTI target

Add targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested changes here . gcc/testsuite/ChangeLog: * testsuite/lib/target-supports.exp: (check_effective_target_arm_pacbti_

[PATCH 5/12] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE

[PATCH 6/12] arm: Add pointer authentication for stack-unwinding runtime

This patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feature is sw

[PATCH 7/12] arm: Emit build attributes for PACBTI target feature

This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emit EABI attributes for Tag_PAC_extension, Tag_BTI_extensi

[PATCH 8/12] arm: Introduce multilibs for PACBTI target feature

This patch add the following new multilibs. thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+fp/mbranch-protection/ha

[PATCH 9/12] arm: Make libgcc bti compatible

This change add bti instructions at the beginning of arm specific libgcc hand written assembly routines. 2022-03-31 Andrea Corallo * libgcc/config/arm/crti.S (FUNC_START): Add bti instruction if necessary. * libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START):

[PATCH 10/12] arm: Implement cortex-M return signing address codegen

Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stac

[PATCH 11/12] aarch64: Make bti pass generic so it can be used by the arm backend

Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. Best Regards Andrea gcc/Changelog * config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into 'aarch-bti-i

[PATCH 12/12] arm: implement bti injection

Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads target

Re: [PATCH 2/x] arm: add vst1_lane_bf16 + vstq_lane_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Hi all, > > Second patch of the serie here adding vst1_lane_bf16, vst1q_lane_bf16 > bfloat16 related neon intrinsics. > > Please see refer to: > ACLE <https://developer.arm.com/docs/101028/latest> > ISA <https://deve

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Hi all, > > I'd like to submit the following patch implementing the bfloat16_t > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16. > > Please see refer to: > ACLE <https://developer.arm.com/docs

[PATCH 3/x] arm: Add vld1_bf16 + vld1q_bf16 intrinsics

Hi all, Third patch of the serie here adding vld1_bf16, vld1q_bf16 bfloat16 related neon intrinsics. Please see refer to: ACLE ISA Regtested and bootstrapped. Thanks! Andrea gcc/ChangeLog 2020-1

[PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

Hi all, Forth patch of the serie here adding vst1_bf16, vst1q_bf16 bfloat16 related neon intrinsics. Please see refer to: ACLE ISA Regtested and bootstrapped. Thanks! Andrea gcc/ChangeLog 2020-1

[PATCH 5/x] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics

Hi all, 5th patch of the serie here adding vld2_lane_bf16, vld2q_lane_bf16, vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16, vld4q_lane_bf16 related neon intrinsics. Please see refer to: ACLE ISA Regt

[PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

Hi all, last patch for this the serie adding vst2_lane_bf16, vst2q_lane_bf16, vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16, vst4q_lane_bf16 related neon intrinsics. Please see refer to: ACLE ISA Re

Re: [PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

Kyrylo Tkachov writes: [...] > I see this patch also has the hunk: > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index 33e8015b140..6dc5df93216 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -946,6 +946,9 @@ typedef struct {

Re: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 02 November 2020 09:04 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd >> Subject: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics >> >> Hi all, >> >> last pat

Re: [PATCH V2] aarch64: Add vcopy(q)__lane(q)_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Richard Sandiford writes: [...] >> OK with that change if it works (for trunk and for whichever >> branches need it). >> >> Thanks, >> Richard > > Hi Richard, > > I've applied the suggestions and

Re: [PATCH V3] aarch64: Add vstN_lane_bf16 + vstNq_lane_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Andrea Corallo via Gcc-patches writes: > [...] > >> Hi all, >> >> third version of this patch following the suggestions got for its sister >> patch <https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557308.ht

Re: [PATCH V4] aarch64: Add bfloat16 vldN_lane_bf16 + vldNq_lane_bf16 intrisics

Andrea Corallo via Gcc-patches writes: > Richard Sandiford writes: > [...] >> OK for both. Thanks for doing this. >> >> Richard > > Welcome, installed into master as 44e570d9fb0. > > Will follow-up for the backport. > > Thanks! > > And

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Christophe Lyon writes: > On Wed, 4 Nov 2020 at 14:29, Christophe Lyon > wrote: >> >> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches >> wrote: >> > >> > Hi Andrea, >> > >> > > -Original Message- >> > > From: Andrea Corallo >> > > Sent: 26 October 2020 15:59 >> > > To: gcc

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Christophe Lyon writes: > On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches > wrote: >> >> Hi Andrea, >> >> > -Original Message- >> > From: Andrea Corallo >> > Sent: 26 October 2020 15:59 >> > To: gcc-patches@gcc.gnu.org >> > Cc: Kyrylo Tkachov ; Richard Earnshaw >> > ; nd >>

[PATCH] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: [...] >> I think you need to add -mfloat-abi=hard to the dg-additional-options >> otherwise vld1_lane_bf16_1.c >> fails on targets with a soft float-abi default (eg arm-linux-gnueabi). >> >> See bf16_vldn_1.c. > > Actually that's not sufficient because in turn we get: > /

Re: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo wrote: >> >> Christophe Lyon writes: >> >> [...] >> >> >> I think you need to add -mfloat-abi=hard to the dg-additional-options >> >> otherwise vld1_lane_bf16_1.c >> >> fails on targets with a soft float-abi default (eg arm-l

[PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: > On Thu, 5 Nov 2020 at 15:30, Andrea Corallo wrote: >> >> Christophe Lyon writes: >> >> > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo wrote: >> >> >> >> Christophe Lyon writes: >> >> >> >> [...] >> >> >> >> >> I think you need to add -mfloat-abi=hard to the dg-additio

[PATCH] aarch64: Do not alter force_reg returned register expanding fcmla

Hi all, this patch is to fix a force_reg returned rtx potentially modified in `aarch64_general_expand_builtin`. Bootstrapped and reg-tested on aarch64-none-linux-gnu. Okay for trunk? Thanks Andrea 2020-11-06 Andrea Corallo * config/aarch64/aarch64-builtins.c (aarch64_exp

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: [...] > Yes, it works for me, thanks. Super, happy to push it when I get the okay. Andrea

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 09 November 2020 10:05 >> To: Christophe Lyon >> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org; >> Richard Earnshaw ; nd >> Subject: Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 >> testcase >> >

  1   2   3   >