[PATCH 5/15] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE

[PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtime

Hi all, this patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feat

[PATCH 7/15] arm: Emit build attributes for PACBTI target feature

This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emit EABI attributes for Tag_PAC_extension, Tag_BTI_extensi

[PATCH 8/15] arm: Introduce multilibs for PACBTI target feature

This patch add the following new multilibs. thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+fp/mbranch-protection/ha

[PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Hi all, this patch enables 'arm_emit_multi_reg_pop' to set again the stack pointer as CFA reg when popping if this is necessary. /gcc/ * config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointer was set define again the stack pointer as CFA reg when popping. diff --git a/

[PATCH 10/15] arm: Implement cortex-M return signing address codegen

nsion> gcc/Changelog 2021-11-03 Andrea Corallo * config/arm/arm.c: (arm_compute_frame_layout) (arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue) (arm_conditional_register_usage): Update for pac codegen. (arm_current_function_pac_enabled_p): New f

[PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. The original patch was approved here: . After that Richard E. note

[PATCH 12/15] arm: implement bti injection

targeted by indirect jumps. Best Regards Andrea [1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension> gcc/ChangeLog 2022-04-07 Andrea Corallo * config.gcc (arm*-*-*

Re: [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M

Andrea Corallo via Gcc-patches writes: > Hi all, > > as I respinned few patches, dropped one and added another, I'm reposting > this series thant enables return address verification and branch target > identification based on Armv8.1-M Pointer Authentication and Branch >

[PATCH] contrib: Fix a typo in contrib/git-fetch-vendor.sh

Hi all, just commited this to fix a typo as obvious. Bests Andrea /contrib/ChangeLog: * git-fetch-vendor.sh : Fix typo. diff --git a/contrib/git-fetch-vendor.sh b/contrib/git-fetch-vendor.sh index 15303629b5c..bbd52fb2055 100755 --- a/contrib/git-fetch-vendor.sh +++ b/contrib/git-fe

Re: [PATCH V2] arm: add -static-pie support

Lance Fredrickson via Gcc-patches writes: > Yes, this is a 1st submission. > Yes, I guess I was going for DCO rules. > I will look at running the test suite. Does this need to be done on > the target? because my arm target is a measly dual core 1ghz embedded > chip and low ram. Netgear R7000 rout

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch enables 'arm_emit_multi_reg_pop' to set again the stack > pointer as CFA reg when popping if this is necessary. > > /gcc/ > > * config/arm/arm.cc (arm_emit_multi_reg_pop): If the frame pointe

Re: [PATCH 7/15] arm: Emit build attributes for PACBTI target feature

Andrea Corallo via Gcc-patches writes: > This patch emits assembler directives for PACBTI build attributes as > defined by the > ABI. > > <https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf> > > gcc/ChangeLog: > > * config/arm/

Re: [PATCH 10/15] arm: Implement cortex-M return signing address codegen

Ping Andrea

Re: [PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch splits and restructures the aarch64 bti pass code in order > to have it usable by the arm backend as well. These changes have no > functional impact. > > The original patch was approved here: > <https:

Re: [PATCH 12/15] arm: implement bti injection

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch enables Branch Target Identification Armv8.1-M Mechanism > [1]. > > This is achieved by using the bti pass made common with Aarch64. > > The pass iterates through the instructions and adds the necessary B

[PATCH 0/12] arm: Enables return address verification and branch target identification on Cortex-M

Hi all, this series enables return address verification and branch target identification based on Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1] for Arm Cortex-M. This feature is controlled by the newly introduced '-mbranch-protection' option, contextually the Arm

[PATCH 1/12] arm: Make mbranch-protection opts parsing common to AArch32/64

Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the mo

[PATCH 2/12] arm: Add Armv8.1-M Mainline target feature +pacbti

This patch adds the -march feature +pacbti to Armv8.1-M Mainline. This feature enables pointer signing and authentication instructions on M-class architectures. Pre-approved here . gcc/Changelog: * config/arm/arm.h (TA

[PATCH 3/12] arm: Add option -mbranch-protection

[PATCH 3/12] arm: Add option -mbranch-protection Add -mbranch-protection option. This option enables the code-generation of pointer signing and authentication instructions in function prologues and epilogues. gcc/ChangeLog: * config/arm/arm.c (arm_configure_build_target): Parse and vali

[PATCH 4/12] arm: Add testsuite library support for PACBTI target

Add targeting-checking entities for PACBTI in testsuite framework. Pre-approved with the requested changes here . gcc/testsuite/ChangeLog: * testsuite/lib/target-supports.exp: (check_effective_target_arm_pacbti_

[PATCH 5/12] arm: Implement target feature macros for PACBTI

This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE

[PATCH 6/12] arm: Add pointer authentication for stack-unwinding runtime

This patch adds authentication for when the stack is unwound when an exception is taken. All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feature is sw

[PATCH 7/12] arm: Emit build attributes for PACBTI target feature

This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emit EABI attributes for Tag_PAC_extension, Tag_BTI_extensi

[PATCH 8/12] arm: Introduce multilibs for PACBTI target feature

This patch add the following new multilibs. thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+fp/mbranch-protection/ha

[PATCH 9/12] arm: Make libgcc bti compatible

This change add bti instructions at the beginning of arm specific libgcc hand written assembly routines. 2022-03-31 Andrea Corallo * libgcc/config/arm/crti.S (FUNC_START): Add bti instruction if necessary. * libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START

[PATCH 10/12] arm: Implement cortex-M return signing address codegen

Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stac

[PATCH 11/12] aarch64: Make bti pass generic so it can be used by the arm backend

Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. Best Regards Andrea gcc/Changelog * config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into 'aarch-bti-i

[PATCH 12/12] arm: implement bti injection

Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads target

Re: [PATCH 2/x] arm: add vst1_lane_bf16 + vstq_lane_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Hi all, > > Second patch of the serie here adding vst1_lane_bf16, vst1q_lane_bf16 > bfloat16 related neon intrinsics. > > Please see refer to: > ACLE <https://developer.arm.com/docs/101028/latest> > ISA <https://deve

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Hi all, > > I'd like to submit the following patch implementing the bfloat16_t > neon related load intrinsics: vld1_lane_bf16, vld1q_lane_bf16. > > Please see refer to: > ACLE <https://developer.arm.com/docs

[PATCH 3/x] arm: Add vld1_bf16 + vld1q_bf16 intrinsics

ngeLog 2020-10-29 Andrea Corallo * config/arm/arm-builtins.c (VAR14): Define macro. * config/arm/arm_neon_builtins.def: Touch for: __builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf. * config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics. gcc/testsuite/Cha

[PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

ngeLog 2020-10-29 Andrea Corallo * config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def : Touch for: __builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf. gcc/testsuite/ChangeLog 2020-10-29 Andrea Corallo * gcc.tar

[PATCH 5/x] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics

96/latest> Regtested and bootstrapped. Thanks! Andrea gcc/ChangeLog 2020-10-29 Andrea Corallo * config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16) (vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16) (vld4q_lane_bf16): Add intrinsics. * config/arm/arm_neon_

[PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

96/latest> Regtested and bootstrapped. Thanks! Andrea >From 47b1272f7d14d91f4e327501c1e1bad6ceeb4525 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 29 Oct 2020 11:20:23 +0100 Subject: [PATCH 6/6] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics gcc/ChangeLog 2020-10-29

Re: [PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

Kyrylo Tkachov writes: [...] > I see this patch also has the hunk: > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index 33e8015b140..6dc5df93216 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -946,6 +946,9 @@ typedef struct {

Re: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 02 November 2020 09:04 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd >> Subject: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane

Re: [PATCH V2] aarch64: Add vcopy(q)__lane(q)_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Richard Sandiford writes: [...] >> OK with that change if it works (for trunk and for whichever >> branches need it). >> >> Thanks, >> Richard > > Hi Richard, > > I've applied the suggestions and

Re: [PATCH V3] aarch64: Add vstN_lane_bf16 + vstNq_lane_bf16 intrinsics

Andrea Corallo via Gcc-patches writes: > Andrea Corallo via Gcc-patches writes: > [...] > >> Hi all, >> >> third version of this patch following the suggestions got for its sister >> patch <https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557308.ht

Re: [PATCH V4] aarch64: Add bfloat16 vldN_lane_bf16 + vldNq_lane_bf16 intrisics

Andrea Corallo via Gcc-patches writes: > Richard Sandiford writes: > [...] >> OK for both. Thanks for doing this. >> >> Richard > > Welcome, installed into master as 44e570d9fb0. > > Will follow-up for the backport. > > Thanks! > > And

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Christophe Lyon writes: > On Wed, 4 Nov 2020 at 14:29, Christophe Lyon > wrote: >> >> On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches >> wrote: >> > >> > Hi Andrea, >> > >> > > -Original Message- >> &

Re: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Christophe Lyon writes: > On Tue, 3 Nov 2020 at 11:27, Kyrylo Tkachov via Gcc-patches > wrote: >> >> Hi Andrea, >> >> > -Original Message- >> > From: Andrea Corallo >> > Sent: 26 October 2020 15:59 >> > To: gcc-patches@gcc.

[PATCH] arm: [testcase] Better narrow some bfloat16 testcase

ch should implement your suggestions. On my arm-none-linux-gnueabi setup the tests were already skipped as unsupported so if you could test and confirm this fixes the issue you see would be great. Thanks! Andrea >From d27e3f39fa2f348a4b8aa929bbb65808a09f1211 Mon Sep 17 00:00:00 2001 From

Re: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo wrote: >> >> Christophe Lyon writes: >> >> [...] >> >> >> I think you need to add -mfloat-abi=hard to the dg-additional-options >> >> otherwise vld1_lane_bf16_1.c >

[PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: > On Thu, 5 Nov 2020 at 15:30, Andrea Corallo wrote: >> >> Christophe Lyon writes: >> >> > On Thu, 5 Nov 2020 at 12:11, Andrea Corallo wrote: >> >> >> >> Christophe Lyon writes: >> >> >> &g

[PATCH] aarch64: Do not alter force_reg returned register expanding fcmla

Hi all, this patch is to fix a force_reg returned rtx potentially modified in `aarch64_general_expand_builtin`. Bootstrapped and reg-tested on aarch64-none-linux-gnu. Okay for trunk? Thanks Andrea 2020-11-06 Andrea Corallo * config/aarch64/aarch64-builtins.c

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

Christophe Lyon writes: [...] > Yes, it works for me, thanks. Super, happy to push it when I get the okay. Andrea

Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16 testcase

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 09 November 2020 10:05 >> To: Christophe Lyon >> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org; >> Richard Earnshaw ; nd >> Subject: Re: [PATCH V2] arm: [testcas

Re: [PATCH] aarch64: Do not alter force_reg returned register expanding fcmla

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 09 November 2020 10:04 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd >> Subject: [PATCH] aarch64: Do not alter force_reg returned

[PATCH] [PR target/97727] aarch64: [testcase] fix bf16_vstN_lane_2.c for big endian targets

Hi all, this simple patch is to fix PR target/97727. Okay for trunk and gcc-10? Thanks! Andrea 2020-11-09 Andrea Corallo PR target/97727 * gcc.target/aarch64/advsimd-intrinsics/bf16_vldN_lane_2.c: Relax regexps. >F

[PATCH] aarch64: Make use of RTL predicates

Hi all, I'd like to propose this patch to make use of RTL predicates into the AArch64 back-end where possible. Bootstrapped and regtested on aarch64-unknown-linux-gnu. Okay for trunk? Thanks Andrea >From 9a027963f228b5c11aba30537cf888bba09bd6c2 Mon Sep 17 00:00:00 2001 From: Andrea

[PATCH] [PR target/97727] arm: [testsuite] fix some simd tests on armbe

Hi all, I'd like to submit this patch to fix three testcases reported to be failing on arm big endian on PR target/97727. Okay for trunk? Thanks Andrea >From c2d5faf49647381edbcdce6a709b5ed046ce13a4 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Tue, 10 Nov 2020 15:15:

Re: [PATCH] aarch64: Make use of RTL predicates

Kyrylo Tkachov via Gcc-patches writes: > Hi Andrea, > >> -Original Message----- >> From: Andrea Corallo >> Sent: 10 November 2020 13:26 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd >> Subject: [PATCH] a

[committed] arm: Make use of RTL predicates

>From 156edf21fab7dd5891c72db7ec58b38ef7d52bfa Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Fri, 13 Nov 2020 11:42:04 + Subject: [PATCH] arm: Make use of RTL predicates 2020-11-13 Andrea Corallo * config/arm/aarch-common.c (aarch_accumulator_forwarding): Use RTL predicates where

[PATCH] [PR target/97726] arm: [testsuite] fix some simd tests on armbe

Andrea Corallo via Gcc-patches writes: > Hi all, > > I'd like to submit this patch to fix three testcases reported to be > failing on arm big endian on PR target/97727. > > Okay for trunk? > > Thanks > > Andrea Ops I got the PR number wrong, target/9772

Re: [PATCH] [PR target/97727] aarch64: [testcase] fix bf16_vstN_lane_2.c for big endian targets

Andrea Corallo via Gcc-patches writes: > Hi all, > > this simple patch is to fix PR target/97727. > > Okay for trunk and gcc-10? > > Thanks! > > Andrea > > 2020-11-09 Andrea Corallo > > PR target/97727 > * gcc.target/aarch64/ad

[PATCH 1/2] arm: add arm bti pass

8-1-m-pointer-authentication-and-branch-target-identification-extension> >From 94ee67dbc78c5ea15dde7114d7bffc18a5843cb7 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 28 Jul 2021 15:49:16 +0200 Subject: [PATCH 1/2] arm: add arm bti pass gcc/ChangeLog 2021-09-15 Andrea Corallo

[PATCH 2/2] arm: implement -mbranch-protection command line option

on-and-branch-target-identification-extension> >From aec6bfd6d65fc4b5675dcc89417bc2612dd719cd Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 8 Sep 2021 18:10:15 +0200 Subject: [PATCH 2/2] arm: implement -mbranch-protection command line option gcc/ChangeLog 2021-09-15 Andrea Corallo

Re: Building GNU Arm Embedded Toolchain for macOS/arm64

Romain Goyet via Gcc-patches writes: > Hello, > > Arm distribute pre-built versions of GCC that targets bare-metal Cortex-M > devices at > https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm > > They offer a source release as well as pre-built bi

[PATCH] [1/2] arm: Implement cortex-M return signing address codegen

ter-authentication-and-branch-target-identification-extension> [2] <https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581176.html> >From 605970bdef506d749bbe9650ee469f41b1d7377f Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Fri, 24 Sep 2021 14:50:29 +0200 Subject: [PATCH 1/2] [P

[PATCH] [2/2] arm: add arm bti pass

branch-target-identification-extension> >From 3fc8c64d20efd618b72e4527b7486d779fdaf13b Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 28 Jul 2021 15:49:16 +0200 Subject: [PATCH 2/2] [PATCH] [2/2] arm: add arm bti pass gcc/ChangeLog 2021-11-03 Andrea Corallo *

Re: [Patch 1/8, Arm, AArch64, GCC] Refactor mbranch-protection option parsing and make it common to AArch32 and AArch64 backends. [Was RE: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.]

Tejas Belagod via Gcc-patches writes: [...] > This change refactors all the mbranch-protection option parsing code and types > to make it common to both AArch32 and AArch64 backends. This change also > pulls > in some supporting types from AArch64 to make it common > (aarch_parse_opt_result).

Re: [PATCH 1/2] arm: add arm bti pass

Andrea Corallo via Gcc-patches writes: > Hi all, > > this patch is part of a series that enables Armv8.1-M in GCC and adds > Branch Target Identification Mechanism [1]. > > This patch moves and generalize the Aarch64 "bti" pass so it can be > used also by the Arm

Re: [PATCH 9/12 V2] arm: Make libgcc bti compatible

Richard Earnshaw writes: > On 22/07/2022 16:09, Andrea Corallo via Gcc-patches wrote: >> Richard Earnshaw writes: >> >>> On 21/07/2022 10:17, Andrea Corallo via Gcc-patches wrote: >>>> Richard Earnshaw writes: >>>> >>>>> On 28/0

[PATCH 10/15 V6] arm: Implement cortex-M return signing address codegen

_REGNUM) (reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] > + VUNSPEC_AUT_NOP)] > > Similarly. > > R. Hi Richard & all, please find attached the updated patch implementing suggestions. BR Andrea >From adabef75c4af91865b0639243d6d9aa03bf8ad68 Mon Sep 17 00:00:00 200

[PATCH 12/15 V4] arm: implement bti injection

Hi Richard, thanks for reviewing. Richard Earnshaw writes: > On 28/10/2022 17:40, Andrea Corallo via Gcc-patches wrote: >> Hi all, >> please find attached the third iteration of this patch addresing >> review >> comments. >> Thanks >>

[PATCH 1/15 V2] arm: Make mbranch-protection opts parsing common to AArch32/64

Hi all, respinning this as a rebase was necessary, also now is setting 'aarch_enable_bti' to zero as default for arm as suggested during the review of 12/15. Best Regards Andrea >From 6c765818542cc7b40701e8adae2cbe077d5982cc Mon Sep 17 00:00:00 2001 From: Andrea Corallo Dat

[PATCH 12/15 V5] arm: implement bti injection

Richard Earnshaw writes: > On 14/12/2022 17:00, Richard Earnshaw via Gcc-patches wrote: >> On 14/12/2022 16:40, Andrea Corallo via Gcc-patches wrote: >>> Hi Richard, >>> >>> thanks for reviewing. >>> >>> Richard Earnshaw writes: >>>

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Andrea Corallo via Gcc-patches writes: > Richard Earnshaw writes: > >> On 27/09/2022 16:24, Kyrylo Tkachov via Gcc-patches wrote: >>> >>>> -Original Message- >>>> From: Andrea Corallo >>>> Sent: Tuesday, September 27, 2022 11:0

Re: [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary

Richard Earnshaw writes: > On 09/01/2023 16:48, Richard Earnshaw via Gcc-patches wrote: >> On 09/01/2023 14:58, Andrea Corallo via Gcc-patches wrote: >>> Andrea Corallo via Gcc-patches writes: >>> >>>> Richard Earnshaw writes: >>>> >&g

[PATCH 10/15 V7] arm: Implement cortex-M return signing address codegen

Richard Earnshaw writes: [...] > > Otherwise ok with that change. > > R. Minor respin of this patch addressing the suggestion to have 'use_return_insn' return zero when PAC is enabled. BR Andrea >From 0a894f73fc09be865b7a7cb205e871bf82f8abba Mon Sep 17 00:00:00

[PATCH 15/23] arm: improve tests for vqrdmlashq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. --- .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 32

[PATCH 17/23] arm: improve tests for vqdmlsdhxq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Li

[PATCH 01/23] arm: improve tests and fix vclsq*

gcc/ChangeLog: * config/arm/mve.md (mve_vclsq_s): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise.

[PATCH 16/23] arm: improve tests for vqdmlsdhq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewi

[PATCH 06/23] arm: improve tests for vmulltq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16

[PATCH] ira.c: Fix ICE in ira-color [PR97092]

over subsequent iterations. bootstrapped and regtested on aarch64-unknown-linux-gnu. Okay for trunk? Thanks! Andrea >From 302573854794f023d8f4ab47660f367016627340 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 9 Dec 2020 17:59:12 +0100 Subject: [PATCH] ira.c: Fix ICE in ira-color

Re: [PATCH] ira.c: Fix ICE in ira-color [PR97092]

Vladimir Makarov writes: > On 2020-12-10 10:12 a.m., Andrea Corallo wrote: >> Hi all, >> >> following discussion on PR97092 I'd like to submit the following patch >> with a fix plus associated testcase. >> >> With this patch applied mode is recomput

Re: [PATCH][GCC10][1/6] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Kyrylo Tkachov writes: [...] > Ok. > Thanks, > Kyrill Hi Kyrill, I've installed the serie into releases/gcc-10 as follow: 00be3a70dd8 arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics 69191da4f4f arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics f09b8cc616a arm: Add vst1_bf16 + vst1q_bf16

Re: [PATCH V2] arm: [testsuite] fix lob tests for -mfloat-abi=hard

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 01 December 2020 10:13 >> To: gcc-patches@gcc.gnu.org >> Cc: Richard Earnshaw ; nd ; >> Kyrylo Tkachov >> Subject: [PATCH V2] arm: [testsuite] fix lob tests for -mf

Re: [PATCH] arm: Improve documentation for effective target 'arm_softfloat'

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 01 December 2020 13:52 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd >> Subject: [PATCH] arm: Improve documentation for effecti

[committed] .dir-locals.el: Set 'fill-column' to 80 for c-mode

updated by 'update-copyright.py'? I think this is not scanning the root of the repo. Thanks Andrea >From f60c1b3102791b98de7c1ce951bce335394682ca Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Fri, 11 Dec 2020 15:35:25 +0100 Subject: [PATCH] .dir-locals.el: Set 'fill-column&

Re: [PATCH] ira.c: Fix ICE in ira-color [PR97092]

Vladimir Makarov writes: > On 2020-12-10 10:12 a.m., Andrea Corallo wrote: >> Hi all, >> >> following discussion on PR97092 I'd like to submit the following patch >> with a fix plus associated testcase. >> >> With this patch applied mode is recomput

Re: [PATCH] ira.c: Fix ICE in ira-color [PR97092]

Vladimir Makarov writes: > On 2020-12-14 11:23 a.m., Andrea Corallo wrote: >> Vladimir Makarov writes: >> >>> On 2020-12-10 10:12 a.m., Andrea Corallo wrote: >>>> Hi all, >>>> >>>> following discussion on PR97092 I'd like to su

[PATCH] arm: Fix bootstrap

ongoing. Okay for trunk? Thanks! Andrea >From 64cbd4705dc42b4d3ae37155d91b9ebec5862641 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 17 Dec 2020 13:55:28 + Subject: [PATCH] arm: Fix bootstrap gcc/ChangeLog 2020-12-17 Andrea Corallo * config/arm/arm_neon.h (

Re: [PATCH] arm: Fix bootstrap

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 17 December 2020 14:56 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd ; Prathamesh Kulkarni >> >> Subject: [PATCH] arm: Fix bo

[PATCH] Fix typo in function-abi.h

Hi all, just pushed the following as obvious. Regards Andrea >From 1aff68d54c33ae10fbbb52adb50527baf7b2f627 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Tue, 12 Jan 2021 17:52:52 +0100 Subject: [PATCH] Fix typo in function-abi.h gcc/Changelog 2021-01-12 Andrea Cora

Re: [committed] jit: remove "Alpha" warning from docs

David Malcolm writes: > On Thu, 2021-01-14 at 23:23 +0100, Andrea Corallo wrote: >> Hi Dave and all, >> >> libgccjit is still advertized as alpha state in the documentation >> despite having being introduced few years ago. >> >> I think we may want to

[PATCH] arm: [testuiste] fix ivopts.c target test [PR96372]

; >From 6199695364808c59202dfcb1b29df1e84dab5aa9 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Fri, 15 Jan 2021 15:34:19 +0100 Subject: [PATCH] arm: [testuiste] fix ivopts.c target test [PR96372] gcc/ 2021-01-15 Andrea Corallo PR target/96372 * doc/sourcebuild.texi (arm_

Re: [PATCH] arm: [testuiste] fix ivopts.c target test [PR96372]

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 19 January 2021 17:13 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd ; >> christophe.l...@linaro.org >> Subject: [PATCH] ar

Re: [PATCH] [PR target/97726] arm: [testsuite] fix some simd tests on armbe

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 16 November 2020 16:11 >> To: Andrea Corallo via Gcc-patches >> Cc: nd ; Richard Earnshaw ; >> Kyrylo Tkachov >> Subject: [PATCH] [PR target/97726] arm: [

Re: [PATCH] [PR target/97727] aarch64: [testcase] fix bf16_vstN_lane_2.c for big endian targets

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 09 November 2020 18:24 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd ; >> christophe.l...@linaro.org >> Subject: [

[PATCH] arm: [testsuite] fix lob tests for -mfloat-abi=hard

nd -mfloat-abi=hard may not be used together". Okay for trunk? Thanks Andrea >From ac47dfed0230d9fe596d27331b04ef194633927d Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 26 Nov 2020 12:33:18 +0100 Subject: [PATCH] arm: [testsuite] fix lob tests for -mfloa

Re: [PATCH] arm: [testsuite] fix lob tests for -mfloat-abi=hard

"Richard Earnshaw (lists)" writes: > On 26/11/2020 13:53, Andrea Corallo via Gcc-patches wrote: >> Hi all, >> >> I'd like to submit the following simple patch to clean some Low Loop >> Overhead test failing on hard float configurations. >> >

Re: [PATCH] arm: [testsuite] fix lob tests for -mfloat-abi=hard

Andrea Corallo via Gcc-patches writes: > "Richard Earnshaw (lists)" writes: > >> On 26/11/2020 13:53, Andrea Corallo via Gcc-patches wrote: >>> Hi all, >>> >>> I'd like to submit the following simple patch to clean some Low Loop

[PATCH V2] arm: [testsuite] fix lob tests for -mfloat-abi=hard

Hi all, second version of this patch here fixing lob[2-5].c tests for hard float abi targets implementing Kyrill's suggestions. Okay for trunk? Andrea >From f7f36b243c82a5dd49540cc48ceb8ce636872d5a Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 26 Nov 2020 12:33:18 +0100

[PATCH] arm: Improve documentation for effective target 'arm_softfloat'

ively 'arm_softfloat' is checking if the target requires floating point emulation but not what ABI is used, so I think would be nice to specify that in the documentation. Okay for trunk? Thanks Andrea >From 67e74689e4332d33c3f27119dc21a7722bb6125b Mon Sep 17 00:00:00 2001 From:

[PATCH][GCC10] arm: Fix unwanted fall-through in arm.c

rom a795f7aaf87fa3610bd690fcfb567e7150fe7570 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 27 May 2020 17:43:48 +0100 Subject: [PATCH] arm: Fix unwanted fall-through in arm.c Backporting from mainline. gcc/ChangeLog 2020-05-28 Andrea Corallo * config/arm/arm.c (mve_vector_mem_operand):

Re: [PATCH][GCC10] arm: Fix unwanted fall-through in arm.c

Andrea Corallo via Gcc-patches writes: > Hi all, > > this is to fix in GCC 10 the incomplete backport done by 1aabb312f of > what at the time I fixed on master with dd019ef07. > > Regtested and bootstraped on arm-linux-gnueabihf. > > I guess should be under the obviou

[PATCH][GCC10][1/6] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

.com/docs/ddi0596/latest> The serie has been bootstrapped on arm-linux-gnueabihf and regtested. Okay for gcc-10? Thanks Andrea >From 7b2080b71405918769811174082646219d23163c Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 21 Oct 2020 11:16:01 +0200 Subject: [PATCH 1/6] arm: Add

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