Hi Christophe,
Maybe this patch was based on an older source, but the comment now reads:
/* _t vfoo[t0](_t, _t)
_t vfoo[_n_t0](_t, _t)
Where the _n form only supports s16/s32/u16/u32 types as for vorrq.
Example: vorrq.
int16x8_t [__arm_]vorrq[_s16](int16x8_t a, int16x8_t b)
int1
Hi,
This looks great to me, only one small suggestion, but take it or leave
it I think it's a matter of preference.
On 11/07/2024 22:42, Christophe Lyon wrote:
+ /* No predicate, no suffix. */
if (e.type_suffix (0).integer_p)
if (e.type_suffix (0).unsigne
On 11/07/2024 22:42, Christophe Lyon wrote:
+ bool
+ check (function_checker &c) const override
+ {
+if (c.mode_suffix_id == MODE_none)
+ return true;
+
+unsigned int bits = c.type_suffix (0).element_bits;
+return c.require_immediate_range (1, 1, bits);
+ }
When trying t
Hey Jakub,
This what ya had in mind?
Kind regards,
Andre Vieiradiff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index
ca5174de991bb088f653468f77485c15a61526e6..924e045a15a78b5702a0d6997953f35c6b47efd1
100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
Ping.
On 27/10/15 17:03, Andre Vieira wrote:
Ping.
BR,
Andre
On 13/10/15 18:01, Andre Vieira wrote:
This patch ports the aeabi_idiv routine from Linaro Cortex-Strings
(https://git.linaro.org/toolchain/cortex-strings.git), which was
contributed by ARM under Free BSD license.
The new
On 26/12/15 01:45, Thomas Preud'homme wrote:
[Sending on behalf of Andre Vieira]
Hello,
This patch adds RTL patterns for the push and pop instructions for thumb1.
These are needed by subsequent patches in the series.
*** gcc/ChangeLog ***
2015-10-27 Andre Vieira
T
On 26/12/15 01:47, Thomas Preud'homme wrote:
[Sending on behalf of Andre Vieira]
Hello,
This patch adds support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute. In this patch we implement the attribute
handling and diagnosis around the attribute. See Sect
On 05/01/16 14:38, Andre Vieira wrote:
On 31/12/15 20:54, Joseph Myers wrote:
On Sat, 26 Dec 2015, Thomas Preud'homme wrote:
+#define CMSE_TT_ASM(flags) \
+{ \
+ cmse_address_info_t result; \
+ __asm__ ("tt" # flags " %0,%1" \
+ : "=r"(result) \
+
On 26/12/15 01:52, Thomas Preud'homme wrote:
[Sending on behalf of Andre Vieira]
Hello,
This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute in two ways:
1) Generate two labels for the function, the regular function name and one with
On 26/12/15 01:54, Thomas Preud'homme wrote:
[Sending on behalf of Andre Vieira]
Hello,
This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of information
through unbanked registers.
When returning from a
On 26/12/15 01:55, Thomas Preud'homme wrote:
[Sending on behalf of Andre Vieira]
Hello,
This patch adds support for the ARMv8-M Security Extensions
'cmse_nonsecure_call' attribute. This attribute may only be used for function
types and when used in combination with the '
On 26/12/15 01:59, Thomas Preud'homme wrote:
[Sending on behalf of Andre Vieira]
Hello,
This patch adds support ARMv8-M's Security Extension's cmse_nonsecure_caller
intrinsic. This intrinsic is used to check whether an entry function was called
from a non-secure state.
See S
On 19/01/16 15:28, Andre Vieira (lists) wrote:
On 16/01/16 14:49, Senthil Kumar Selvaraj wrote:
User-agent: mu4e 0.9.13; emacs 24.5.1
Hi,
Apologies for the bad posting style (I don't have the
original email handy), but shouldn't _gnu_cmse_nonsecure_call be defined
with the .global
On 12/02/16 07:43, Jeff Law wrote:
On 02/11/2016 06:28 PM, Bernd Schmidt wrote:
This seems fairly straightforward:
(insn 213 455 216 6 (set (reg:SI 266)
(mem/u/c:SI (post_inc:SI (reg/f:SI 267)) [4 S4 A32])) 748
{*thumb1_movsi_insn}
(expr_list:REG_EQUAL (const_int -1044200508 [0x
On 18/01/16 11:04, Andre Vieira (lists) wrote:
Hi there,
Can we have the "#pragma GCC pop_options" fix backported to GCC-5?
Patch found in https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html
and was committed in r228794.
The same patch applies cleanly to gcc-5, which would oth
On 15/02/16 10:33, Andre Vieira (lists) wrote:
On 18/01/16 11:04, Andre Vieira (lists) wrote:
Hi there,
Can we have the "#pragma GCC pop_options" fix backported to GCC-5?
Patch found in https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html
and was committed in r228794.
The
Hi there,
This patch series adds support for the recently announced ARM core
Cortex-R8.
Andre Vieira(2)
Add support for Cortex-R8
Fix testcases after introduction of Cortex-R8
Tested by comparing regression runs of Cortex-R7 vs Cortex-R8 for both
ARM and THUMB modes.
Is this OK?
Cheers,
Andre
gcc/ChangeLog:
2016-03-02 Andre Vieira
* config/arm/arm-cores.def (cortex-r8): New.
* config/arm/arm-tables.opt (cortex-r8): New.
* config/arm/arm-tune.md: Regenerate.
* gcc/doc/invoke.texi: Add cortex-r8 to list of cpu values.
>F
Hi,
Tests used to check for "r8" which will not work because cortex-r8
string is now included in the assembly. Fixed by checking for "[^\-]r8".
Is this Ok?
Cheers,
Andre
gcc/testsuite/ChangeLog:
2016-03-02 Andre Vieira
* gcc.target/arm/pr45701-1.c: Change a
On 21/05/15 10:01, Kyrill Tkachov wrote:
> Hi Sandra,
>
> On 21/05/15 06:43, Sandra Loosemore wrote:
>> This is another patch aimed at fixing bugs relating to trying to execute
>> NEON code on a target that doesn't support it revealed by my
>> arm-none-eabi testing on a gazillion different multili
On 29/02/16 10:47, Andre Vieira (lists) wrote:
> On 15/02/16 10:33, Andre Vieira (lists) wrote:
>> On 18/01/16 11:04, Andre Vieira (lists) wrote:
>>> Hi there,
>>>
>>> Can we have the "#pragma GCC pop_options" fix backported to GCC-5?
>>>
>
On 03/03/16 12:11, Bernd Schmidt wrote:
> On 03/03/2016 11:45 AM, Andre Vieira (lists) wrote:
>> On 29/02/16 10:47, Andre Vieira (lists) wrote:
>>> On 15/02/16 10:33, Andre Vieira (lists) wrote:
>>>> On 18/01/16 11:04, Andre Vieira (lists) wrote:
>>>&
Hi all,
This is a prototype I have put together to look at the feasibility and
profitability of vectorizing loops with breaks as suggested in PR 91246.
I am posting this here for comments as I am curious what your opinions
are on my approach. I don't expect much attention to this in stage 4,
Hi,
This was a matter of mistaken logic in (define_attr "conds" ..). This
was setting the conds attribute for any neon instruction to no_cond
which was messing up code generation.
Bootsrapped and regression tested arm-linux-gnueabihf.
Is this OK for trunk?
2020-03-19 An
Hi,
I noticed some issues with the patches that landed on trunk and this
patch series fixes them. The first issue was revealed after I fixed the
testisms (in patch 2/2).
Andre Vieira (2):
Fix MVE move from GPR -> GPR
Fix testisms for MVE testsuite
.
Is this OK for trunk?
gcc/ChangeLog:
2020-03-20 Andre Vieira
* config/arm/mve.md (mve_mov): Fix R->R case.
gcc/testsuite/ChangeLog:
2020-03-** Andre Vieira
* gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test.
diff --git a/gcc/config/arm/mve.md b/gcc/config/
Hi,
This patch fixes some testism where -mfpu=auto was missing or where we
could end up with -mfloat-abi=hard and soft on the same command-line.
Tested on arm-none-eabi.
Is this OK for trunk?
gcc/testsuite/ChangeLog:
2020-03-20 Andre Vieira
* gcc.target/arm/mve/intrinsics
MVE should
not be
using these.
This fixes regressions for gcc.dg/atomic/c11-atomic-exec-5.c
Bootstrapped and tested arm-linux-gnueabihf.
Is this OK for trunk?
gcc/ChangeLog:
2020-03-20 Andre Vieira
* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to
Hi,
This patch series changes all MVE tests into assembly tests so we check whether
the generated assembly is syntactically correct. The first patch of the series
fixes an issue this caught where the instructions don't allow destination and
source registers to be the same.
Andre Viei
Hi,
This patch adds an earlyclobber to the MVE instructions that require it
and were missing it. These are vrev64 and 32-bit element variants of
vcadd, vhcadd vcmul, vmull[bt] and vqdmull[bt].
Regression tested on arm-none-eabi.
Is this OK for trunk?
Cheers,
Andre
2020-03-23 Andre
On 08/07/2020 09:04, Andre Simoes Dias Vieira wrote:
On 07/07/2020 13:43, Christophe Lyon wrote:
Hi,
On Mon, 6 Jul 2020 at 16:31, Andre Vieira (lists)
wrote:
On 30/06/2020 14:50, Andre Vieira (lists) wrote:
On 29/06/2020 11:15, Christophe Lyon wrote:
On Mon, 29 Jun 2020 at 10:56
ld be
rather useless.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-02 Andre Vieira
* config/arm/arm_mve.h: Condition the header file on
__ARM_FEATURE_MVE.
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
f1dcdc2153217e796c58526ba0e5be11be6
When committing my last patch I accidentally removed -mfpu=auto from the
following tests. This puts it back.
2020-04-03 Andre Vieira
* gcc.target/arm/mve/intrinsics/mve_vector_float.c: Put
-mfpu=auto back.
* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise
Now with the zipped patch so it reaches the mailing list.
Sorry for that.
On 07/04/2020 09:57, Kyrylo Tkachov wrote:
-Original Message-
From: Andre Vieira (lists)
Sent: 07 April 2020 09:57
To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH][GCC][Arm]: MVE: Fix
On 06/04/2020 16:12, Christophe Lyon via Gcc-patches wrote:
Hi,
While checking Martin's fix for PR ipa/94445, he made me realize that
the cmse-15.c testcase still fails at -Os because ICF means that we
generate
nonsecure2:
b nonsecure0
which is OK, but does not match the currentl
ed on arm-none-eabi.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-07 Andre Vieira
* config/arm/arm.c (output_move_neon): Deal with label + offset
cases.
* config/arm/mve.md (*mve_mov): Handle const vectors.
gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira
* gcc.t
is OK for trunk?
gcc/ChangeLog:
2020-04-07 Andre Vieira
* config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
* config/arm/mve/md: Fix v[id]wdup patterns.
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
e31c2e8fdc4f500bf9408d05ad86e151397
d to use the
bottom part.
We can solve this in a better way, but for now this will do.
Regression tested on arm-none-eabi.
Is this OK for trunk?
2020-04-07 Andre Vieira
* config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit
shifts.
diff --git a/gcc/config/ar
ers,
Andre
On 07/04/2020 11:52, Kyrylo Tkachov wrote:
-Original Message-
From: Andre Vieira (lists)
Sent: 07 April 2020 11:35
To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov
Subject: [PATCH][GCC][Arm]: MVE: Fix constant load pattern
Hi,
This patch fixes the constant load pattern f
On 07/04/2020 11:57, Christophe Lyon wrote:
On Tue, 7 Apr 2020 at 12:40, Andre Vieira (lists)
wrote:
Hi,
This patch fixes v[id]wdup intrinsics. They had two issues:
1) the predicated versions did not link the incoming inactive vector
parameter to the output
2) The backend didn't enforc
-none-eabi.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-07 Andre Vieira (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
mve_vqshrntq_n_*,
mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*,
mve_vqshrnbq_m_n_*, mve_v
and
then stored in memory using scalar store pattern.
Regression tested on arm-none-eabi.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-07 Andre Vieira
* config/arm/mve.md (mve_vec_extract*): Allow memory operands
in set.
gcc/testsuite/ChangeLog:
2020-04-07 An
Hi,
This patch fixes some testisms I found when testing using -Wall/-Werror.
Is this OK for trunk?
gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira
* gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c
Hi,
This patch fixes the passing of some pointers to builtins that expect
slightly different types of pointers. In C this didn't prove an issue,
but when compiling for C++ gcc complains.
Regression tested on arm-none-eabi.
Is this OK for trunk?
2020-04-07 Andre Vieira
* c
e PRESERVE NAMESPACE macro.
This patch further fixes two testisms that were brought to light by C++
testing added in this patch.
Regression tested on arm-none-eabi.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-07 Andre Vieira
* config/arm/arm_mve.h: Add C++ polymorphism and fix
On 10/04/2020 14:55, Christophe Lyon via Gcc-patches wrote:
Some MVE tests explicitly test a -mfloat-abi=hard option, but we need
to check that the toolchain actually supports it (which may not be the
case for arm-linux-gnueabi* targets).
We also make use of dg-add-options arm_v8_1m_mve_fp and a
On 10/04/2020 14:55, Christophe Lyon via Gcc-patches wrote:
Several ARM/MVE tests can be compiled even if the toolchain does not
support -mfloat-abi=hard (softfp is OK).
Use dg-add-options arm_v8_1m_mve or arm_v8_1m_mve_fp instead of using
dg-additional-options.
Hi Christophe,
I think a bunch
On 10/04/2020 14:55, Christophe Lyon via Gcc-patches wrote:
For arm-linux-gnueabi* targets, a toolchain cannot support the
float-abi opposite to the one it has been configured for: since glibc
does not support such multilibs, we end up lacking gnu/stubs-*.h when
including stdint.h for instance.
On 10/04/2020 14:55, Christophe Lyon via Gcc-patches wrote:
This test can pass with a hard-float toolchain, provided we don't
force -mfloat-abi=softfp.
This patch removes this useless option, as well as -save-temps which
is implied by arm_v8_1m_mve_fp.
Hi Christophe,
LGTM, but you need to wait
On 10/04/2020 14:55, Christophe Lyon via Gcc-patches wrote:
Since arm_mve.h includes stdint.h, its use requires the presence of
the right gnu/stub-*.h, so make sure to include it when checking the
arm_v8_1m_mve_ok_nocache effective target, otherwise we can decide MVE
is supported while it's not
Hi,
This patch fixes an ICE we were seeing due to a missing vec_duplicate
pattern.
Regression tested on arm-none-eabi.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-15 Andre Vieira
* config/arm/mve.md (mve_vec_duplicate): New pattern.
(V_sz_elem2): Remove unused mode
Hi,
This series backports all the patches and fixes regarding outline
atomics to the gcc-8 branch.
Bootstrapped the series for aarch64-linux-gnu and regression tested.
Is this OK for gcc-8?
Andre Vieira (19):
aarch64: Add early clobber for aarch64_store_exclusive
aarch64: Simplify LSE cas
2020-04-16 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
* config/aarch64/atomics.md (aarch64_atomic__lse):
scratch register need not be early-clobber. Document the reason
why we cannot use ST.
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config
Allow zero as an input; fix constraints; avoid unnecessary split.
2020-04-16 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
* config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
(aarch64_gen_atomic_ldop): Don't call it.
* config/aa
The cas insn is a single insn, and if expanded properly need not
be split after reload. Use the proper inputs for the insn.
2020-04-16 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
* config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
Force
Fix constraints; avoid unnecessary split. Drop the use of the atomic_op
iterator in favor of the ATOMIC_LDOP iterator; this is simplier and more
logical for ldclr aka bic.
2020-04-16 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
* config/aarch64/aarch64.c
gcc/ChangeLog:
2020-04-16 Andre Vieira
Backport from mainline.
2018-07-16 Ramana Radhakrishnan
* config/aarch64/atomics.md (aarch64_store_execlusive): Add
early clobber.
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index
Do not zero-extend the input to the cas for subword operations;
instead, use the appropriate zero-extending compare insns.
Correct the predicates and constraints for immediate expected operand.
2020-04-16 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
2020-04-16 Andre Vieira
Backport from mainline.
2019-09-19 Richard Henderson
* config/aarch64/aarch64 (aarch64_split_compare_and_swap):Unify
some code paths;
use aarch64_gen_compare_reg instead of open-coding.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64
2020-04-16 Andre Vieira
Backport from mainline
2019-09-19 Richard Henderson
* config/aarch64/aarch64.opt (-moutline-atomics): New.
* config/aarch64/aarch64.c (aarch64_atomic_ool_func): New.
(aarch64_ool_cas_names, aarch64_ool_swp_names): New.
(aarch64_ool_ldadd_names
2020-04-16 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
* optabs-libfuncs.c (build_libfunc_function_visibility):
New, split out from...
(build_libfunc_function): ... here.
(init_one_libfunc_visibility): New, split out from
2020-04-16 Andre Vieira
Backport from mainline
2019-09-25 Richard Henderson
PR target/91834
* config/aarch64/lse.S (LDNM): Ensure STXR output does not
overlap the inputs.
diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S
index
This is the libgcc part of the interface -- providing the functions.
Rationale is provided at the top of libgcc/config/aarch64/lse.S.
2020-04-16 Andre Vieira
Backport from mainline
2019-09-19 Richard Henderson
* config/aarch64/lse-init.c: New file.
* config/aarch64/lse.S
2020-04-16 Andre Vieira
Backport from mainline
2020-01-17 Wilco Dijkstra
PR target/92692
* config/aarch64/atomics.md (aarch64_compare_and_swap)
Use epilogue_completed rather than reload_completed.
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64
2020-04-16 Andre Vieira
Backport from mainline.
2019-09-19 Richard Henderson
* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support
for NE comparison of TImode values.
(aarch64_emit_load_exclusive): Add support for TImode.
(aarch64_emit_store_exclusive
2020-04-16 Andre Vieira
Backport from mainline.
2019-09-19 Richard Henderson
* config/aarch64/aarch64.c (aarch64_print_operand): Allow integer
registers with %R.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index
2020-04-16 Andre Vieira
Backport from mainline
2019-09-25 Richard Henderson
PR target/91833
* config/aarch64/lse-init.c: Include auto-target.h. Disable
initialization if !HAVE_SYS_AUXV_H.
* configure.ac (AC_CHECK_HEADERS): Add sys/auxv.h.
* config.in, configure
2020-04-16 Andre Vieira
Backport from mainline
2019-08-21 Prathamesh Kulkarni
PR target/90724
* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): Force y
in reg if it fails aarch64_plus_operand predicate.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config
2020-04-16 Andre Vieira
Backport from mainline
2020-03-31 Jakub Jelinek
PR target/94368
* config/aarch64/constraints.md (Uph): New constraint.
* config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
(aarch64_compare_and_swap): Use it instead of n in
it zero extends y
into SImode. The problem is that when the zero extended constant isn't
usable directly, it forces it into a REG, but with y_mode mode, and then
compares against y. That is wrong, because it should force it into a SImode
REG and compare that way.
2020-04-16 Andre V
.inst directive if LSE support isn't
available in the assembler.
2020-04-16 Andre Vieira
Backport from mainline
2020-04-15 Jakub Jelinek
PR target/93053
* configure.ac (LIBGCC_CHECK_AS_LSE): Add HAVE_AS_LSE checking.
* config/aarch64/lse.S: Include auto-target.h, if HAVE_AS_
On 16/04/2020 13:24, Andre Vieira (lists) wrote:
Hi,
This series backports all the patches and fixes regarding outline
atomics to the gcc-8 branch.
Bootstrapped the series for aarch64-linux-gnu and regression tested.
Is this OK for gcc-8?
Andre Vieira (19):
aarch64: Add early clobber for
On 20/04/2020 09:42, Kyrylo Tkachov wrote:
Hi Andre,
-Original Message-
From: Andre Vieira (lists)
Sent: 16 April 2020 13:24
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Sandiford
; s...@amazon.com
Subject: [PATCH 0/19][GCC-8] aarch64: Backport outline atomics
Hi,
This
it to build
even with older binutils by using .inst directive if LSE support isn't
available in the assembler.
2020-04-22 Andre Vieira
Backport from mainline.
2020-04-15 Jakub Jelinek
PR target/93053
* configure.ac (LIBGCC_CHECK_AS_LSE): Add HAVE_AS_LSE checking.
* conf
Add the backported functionality of -moutline-atomics for AArch64 to the
gcc-9 and gcc-8 changes.html
Validates. Is this OK?
diff --git a/htdocs/gcc-8/changes.html b/htdocs/gcc-8/changes.html
index
83dd1bc010a6e4debb76790b3fe62275bf0e0657..83e57db181294110f71a5d59960fb4d3fed7be98
100644
--- a/
need the overlap checks, NEON only loads from or stores to FP
registers and these can't be used in its addressing modes.
Bootstrapped arm-linux-gnueabihf with '--enable-checking=yes,rtl' for
armv7-a and amrv8-a.
Is this OK for trunk?
gcc/ChangeLog:
2020-04-2
Hi,
Backport of PR target/94518: Fix memmodel index in
aarch64_store_exclusive_pair
This fixes bootstrap with --enable-checking=yes,rtl for aarch64.
OK for gcc-8?
Cheers,
Andre
gcc/ChangeLog:
2020-04-28 Andre Vieira
PR target/94814
Backport from gcc-9.
2020-04-07 Kyrylo
involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.
gcc/ChangeLog:
2020-04-29 Andre Vieira
Backport from mainline.
2018-10-31 Richard Henderson
* config/aarch64/aarch64.c
Hi Richard,
As I mentioned in the IRC channel, I managed to get "most" of the
regression testsuite working for x86_64 (avx512) and aarch64.
On x86_64 I get a failure that I can't explain, was hoping you might be
able to have a look with me:
"PASS->FAIL: gcc.target/i386/vect-perm-odd-1.c exec
tch 1 I'll add a target hook that allows each target to sanitize
the cloned declaration's attributes and in patch 2 I'll make the arm's
implementation of it remove 'cmse_nonsecure_entry' from the cloned
declaration's attribute list.
Andre Vieira (2)
[Patch
Hi,
This patch adds a new target hook called
TARGET_HOOK_SANITIZE_CLONE_ATTRIBUTES. This hook is meant to give each
target the ability to sanitize a cloned's declaration attribute list.
Is this OK for trunk?
Cheers,
Andre
gcc/ChangeLog:
2019-10-08 Andre Vieira
* ipa
for trunk?
Cheers,
Andre
gcc/ChangeLog:
2019-10-08 Andre Vieira
* config/arm/arm.c (TARGET_SANITIZE_CLONE_ATTRIBUTES): Define.
(arm_sanitize_clone_attributes): New.
gcc/testsuite/ChangeLog:
2019-10-08 Andre Vieira
* gcc.target/arm/cmse/ipa-clone.c: New test.
diff -
. The exception is 'create_virtual_clone' which calls
'create_clone' so it should be caught there.
Is this OK for trunk?
Cheers,
Andre
gcc/ChangeLog:
2019-10-09 Andre Vieira
* cgraphclones.c(create_clone): Call new target hook when
c
checks this in the future. I feel it's easier and more flexible to
leave it up to the users of the hook to check it themselves using
DECL_EXTERNAL. I will mention it in the description though.
Cheers,
Andre
gcc/ChangeLog:
2019-10-09 Andre Vieira
* cgraphclones.c(create_clone):
Adding Jakub to CC'
On 09/10/2019 16:29, Andre Vieira (lists) wrote:
Hi Martin,
I see thank you. For my particular use case I only need to strip
attributes for local symbols. However, if I were to claim it is only
used for non-externally visible clones than I would also need to make
Hi Kyrill,
On 10/10/2019 10:53, Kyrill Tkachov wrote:
I'm a bit surprised that TARGET_FMA (which just checks isa_bit_vfpv4)
doesn't imply TARGET_VFP_DOUBLE.
Can one really have a VFPV4 single-precision-only configuration? Richard?
Armv7e-M supports single precision only FPv4, which also
d.
Is this OK for trunk?
gcc/ChangeLog:
2019-10-10 Andre Vieira
PR 88915
* cfgloop.h (loop): Add epilogue_vsizes member.
* cfgloop.c (flow_loop_free): Release epilogue_vsizes.
(alloc_loop): Initialize epilogue_vsizes.
* gentype.c (main): Add poly_uint64 type and
Hi,
Just some minor changes after name changes in the first patch. I'll
assume this is also OK.
gcc/ChangeLog:
2019-10-15 Andre Vieira
* config/arm/arm.c (TARGET_MODIFY_CLONE_CGRAPH_NODE): Define.
(arm_modify_clone_cgraph_node): New.
gcc/testsuite/ChangeLog:
2019-
Hi,
I have changed the name to make the target hook more general and not
create the illusion it is related to sanitizers.
Is this OK for trunk?
Cheers,
Andre
gcc/ChangeLog:
2019-10-15 Andre Vieira
* cgraphclones.c(create_clone): Call new target hook when
creating a new
Hi,
This piece of code was pre-approved by richi.
Retested by bootstrapping and regression testing on x86_64 (AVX512) and
aarch64.
Committed in revision r277101.
gcc/ChangeLog:
2019-10-17 Andre Vieira
* tree-vect-loop.c (vect_transform_loop): Move code from here
Hi,
This piece of code was pre-approved by richi.
Retested by bootstrapping and regression testing on x86_64 (AVX512) and
aarch64.
Committed in revision r277103.
gcc/ChangeLog:
2019-10-17 Andre Vieira
* tree-vect-loop.c (determine_peel_for_niter): New function
contained
Hi,
This piece of code was pre-approved by richi.
Retested by bootstrapping and regression testing on x86_64 (AVX512) and
aarch64.
Committed in revision r277105.
gcc/ChangeLog:
2019-10-17 Andre Vieira
* tree-vect-loop.c (vect_analyze_loop_2): Use same condition to
decide
encountered when trying to link for
-mcpu=cortex-r8 -mfloat-abi=hard.
Built arm-none-eabi and compared testsuite run of
-march=armv7e-m+fp/-mfloat-abi=hard to
-march=armv7-r+fp.sp/-mfloat-abi=hard which looked alright.
Is this OK for trunk?
gcc/ChangeLog:
2019-10-18 Andre Vieira
Hi,
Updated the patch with respect to Richard Earnshaw's comments and
committed in r277156.
gcc/ChangeLog:
2019-10-18 Andre Vieira
* config/arm/t-multilib: Add rule to regenerate mutlilib header
file with any change to t-multilib, t-aprofile and t-rmprofile.
.
Cheers,
Andre
2019-10-21 Andre Vieira
* tree-vect-stmts (ensure_base_align): Only change alignment if new
alignment is more restrictive.
diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c
index e606945d536ad3353b2317aed5b504a89eec9fc3
Hi Richi,
See inline responses to your comments.
On 11/10/2019 13:57, Richard Biener wrote:
On Thu, 10 Oct 2019, Andre Vieira (lists) wrote:
Hi,
+
+ /* Keep track of vector sizes we know we can vectorize the epilogue
with. */
+ vector_sizes epilogue_vsizes;
};
please don't en
The patch applies cleanly on gcc-9 and gcc-8.
I bootstrapped this on aarch64-none-linux-gnu and tested
aarch64-none-elf for both.
Is this OK for those backports?
libgcc/ChangeLog:
2020-05-28 Andre Vieira
Backport from mainline.
2020-05-06 Kyrylo Tkachov
* config/aarch64
Hi,
So this is my rework of the code you sent me, I have not included the
'permute' code you included as I can't figure out what it is meant to be
doing. Maybe something to look at later.
I have also included three tests that show it working for some simple
cases and even a nested one.
Unf
The 'you' here is Richi, which Richi is probably aware but maybe not the
rest of the list :')
On 09/06/2020 15:29, Andre Vieira (lists) wrote:
Hi,
So this is my rework of the code you sent me, I have not included the
'permute' code you included as I can't figu
ed.
Regression tested on arm-none-eabi.
Is this OK for trunk? (Will eventually backport to previous versions if
stable.)
Cheers,
Andre
gcc/ChangeLog:
2020-06-22 Andre Vieira
PR target/95646
* config/arm/arm.c: (cmse_nonsecure_entry_clear_be
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