[PATCH 16/19][GCC-8] aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]

[Andre Vieira (lists)]

2020-04-16  Andre Vieira <andre.simoesdiasvie...@arm.com>

    Backport from mainline
    2020-03-31  Jakub Jelinek <ja...@redhat.com>

    PR target/94368
    * config/aarch64/constraints.md (Uph): New constraint.
    * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
    (aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
    constraint.

    * gcc.dg/pr94368.c: New test.


diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 
0ee8d2efac05877d610981b719bd02afdf93a832..1005462ae23aa13dbc3013a255aa189096e33366
 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -38,6 +38,8 @@
 
 (define_mode_attr cas_short_expected_pred
   [(QI "aarch64_reg_or_imm") (HI "aarch64_plushi_operand")])
+(define_mode_attr cas_short_expected_imm
+  [(QI "n") (HI "Uph")])
 
 (define_insn_and_split "aarch64_compare_and_swap<mode>"
   [(set (reg:CC CC_REGNUM)                                     ;; bool out
@@ -47,7 +49,8 @@
       (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
    (set (match_dup 1)
     (unspec_volatile:SHORT
-      [(match_operand:SHORT 2 "<cas_short_expected_pred>" "rn")        ;; 
expected
+      [(match_operand:SHORT 2 "<cas_short_expected_pred>"
+                             "r<cas_short_expected_imm>")      ;; expected
        (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ")      ;; desired
        (match_operand:SI 4 "const_int_operand")                        ;; 
is_weak
        (match_operand:SI 5 "const_int_operand")                        ;; mod_s
diff --git a/gcc/config/aarch64/constraints.md 
b/gcc/config/aarch64/constraints.md
index 
32a0fa60a198c714f7c0b8b987da6bc26992845d..03626d2faf87e0b038bf3b8602d4feb8ef7d077c
 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -213,6 +213,13 @@
   (and (match_code "const_int")
        (match_test "(unsigned) exact_log2 (ival) <= 4")))
 
+(define_constraint "Uph"
+  "@internal
+  A constraint that matches HImode integers zero extendable to
+  SImode plus_operand."
+  (and (match_code "const_int")
+       (match_test "aarch64_plushi_immediate (op, VOIDmode)")))
+
 (define_memory_constraint "Q"
  "A memory address which uses a single base register with no offset."
  (and (match_code "mem")
diff --git a/gcc/testsuite/gcc.dg/pr94368.c b/gcc/testsuite/gcc.dg/pr94368.c
new file mode 100644
index 
0000000000000000000000000000000000000000..1267b8220983ef1477a8339bdcc6369abaeca592
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94368.c
@@ -0,0 +1,25 @@
+/* PR target/94368 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic -O1 -fcommon" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+       {
+         __atomic_load_n (&e, 0);
+         if (foo (2))
+           __sync_val_compare_and_swap (&c, 0, f);
+         b = 1;
+         if (h == e)
+           break;
+       }
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}