Re: [PATCH] c++: P2036R3 - Change scope of lambda trailing-return-type [PR102610]

On Tue, Jul 08, 2025 at 12:15:03PM -0400, Jason Merrill wrote: > On 7/7/25 4:52 PM, Marek Polacek wrote: > > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > > > > -- >8 -- > > This patch is an attempt to implement P2036R3 along with P2579R0, fixing > > build breakages caused by P203

Re: [PATCH v2] testsuite: arm: Update function body for scheduler

On Wed, 9 Jul 2025 at 10:25, Torbjörn SVENSSON wrote: > > Ok for trunk and releases/gcc-15? > > Changes since v1: > - Removed the acceptance of LDR as it's only generated without > r15-7373-g5163cf2ae14. Since > I'm currently looking into gcc-14 release, and made the patch in that > scope, I r

Re: [Fortran, Patch, PR120711, v1] 1/(3) Fix out of bounds access in cleanup of array constructor

Le 09/07/2025 à 08:50, Andre Vehreschild a écrit : HI Harald, hi Mikael, why shall the testcase be invalid? The `list` is empty. Concatenating with it is valid in Fortran like in most other programming languages. The mapping of an empty list in gfortran is to have the array's data pointer set to

Re: [PATCH v2][PR117366] arm.cc: fix thumb1 size-optimized function prolog violates -ffixed-rX

Hi, Thanks for the patch, the code change looks sensible to me, but you'll have to wait for Richard (in cc) as he is the maintainer. However I have a few comments below: On Thu, 26 Jun 2025 at 00:57, Matt Parks wrote: > > Trying again, hopefully formatted correctly this time, and now including a

Re: [PATCH] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100]

Hi Robin, On 09/07/2025 11:11, Robin Dapp wrote: Hi Paul-Antoine, +;; Intermediate pattern for vfwmacc.vf and vfwmsac.vf used by combine +(define_insn_and_split "*extend_vf_" + [(set (match_operand:VWEXTF 0 "register_operand") +    (vec_duplicate:VWEXTF +  (float_extend: +    (match_op

Re: [PATCH][PR117468] arm.cc: fix thumb1 prologue high reg restore violates -ffixed-rX

Hi, Thanks for your patch, I think the same comments apply as the ones I just sent for your other patch (https://gcc.gnu.org/pipermail/gcc-patches/2025-July/689121.html) Christophe On Thu, 26 Jun 2025 at 01:35, Matt Parks wrote: > > Fixing issue with thumb1 code generation clobbering register.

Re: [PATCH v1] rs6000: Fix UBSAN runtime errors for powerpc64le-unknown-linux-gnu

Hi! On Wed, Jul 09, 2025 at 08:32:19PM +0530, Kishan Parmar wrote: > Ping! > > Please review. I did review this, in Message-ID: <20250626155019.go17...@gate.crashing.org> Date: Thu, 26 Jun 2025 10:50:19 -0500 https://inbox.sourceware.org/gcc-patches/20250626155019.go17...@gate.crashing.org/ Did

Re: [PATCH] aarch64: Extend HVLA permutations to big-endian

On 7/9/25 11:00, Richard Sandiford wrote: External email: Use caution opening links or attachments Richard Sandiford writes: TARGET_VECTORIZE_VEC_PERM_CONST has code to match the SVE2.1 "hybrid VLA" DUPQ, EXTQ, UZPQ{1,2}, and ZIPQ{1,2} instructions. This ma

Re: [PATCH v2] testsuite: arm: Update function body for scheduler

Hi Christophe, On 2025-07-09 17:31, Christophe Lyon wrote: On Wed, 9 Jul 2025 at 10:25, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-15? Changes since v1: - Removed the acceptance of LDR as it's only generated without r15-7373-g5163cf2ae14. Since I'm currently looking into gcc-

RE: [PATCH v1] RISCV: Remove the v extension requirement for sat scalar run test

>> * gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c: Ditto. > Spot checked. Note this uses "RISC-V" so it's not going to be picked up > in the patchwork meeting. Oops, should be a typo here. > It does seem to be causing some testing problems: It seems the CI does pick up the latest code, I wi

Re: [PATCH v1] RISCV: Remove the v extension requirement for sat scalar run test

On 7/9/25 7:19 PM, Li, Pan2 wrote: * gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c: Ditto. Spot checked. Note this uses "RISC-V" so it's not going to be picked up in the patchwork meeting. Oops, should be a typo here. It does seem to be causing some testing problems: It seems the

Re: [PATCH] Make the RTL frontend set REG_NREGS correctly

On Wed, Jul 9, 2025 at 4:05 PM Richard Sandiford wrote: > > While working on a new testcase that uses the RTL frontend, > I hit a bug where a (reg ...) that spans multiple hard registers > had REG_NREGS set to 1. This caused various things to misbehave. > For example, if the (reg ...) in question

[pushed] c++: add passing testcases [PR120243]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- These pass now; the first was fixed by r16-1507. PR c++/120243 gcc/testsuite/ChangeLog: * g++.dg/coroutines/torture/pr120243-unhandled-1.C: New test. * g++.dg/coroutines/torture/pr120243-unhandled-2.C: New test. --

Re: [PATCH 7/7] aarch64: Use BSL2N for DImode operands

On 7/7/25 06:20, Kyrylo Tkachov wrote: > External email: Use caution opening links or attachments > > > Hi all, > > The intent of the patch is similar to previous in the series. > Make more use of BSL2N when we have DImode operands in SIMD regs, > but still use the GP instructions when that's wher

Re: [PATCH] c++, libstdc++, v4: Implement C++26 P3068R5 - constexpr exceptions [PR117785]

On 7/9/25 2:36 PM, Jakub Jelinek wrote: On Wed, Jul 09, 2025 at 10:26:51AM -0400, Jason Merrill wrote: I don't understand this comment, at least in connection with the above snippet, that just handles the magic calls. Sorry I wasn't clear, the comment was about the existing code that follows t

[PATCH v2] arm.cc: fix thumb1 prologue high reg restore violates -ffixed-rX [PR117468]

This patch fixes PR117468: ARM thumb1 compilation using -ffixed-reg with r4-r7, without -Os (which prohibits use of high registers), produces bad high register restoration code that clobbers the fixed register. gcc/ChangeLog: PR target/117468 * arm.cc (thumb1_prologue_unused_call_c

RE: [PATCH v1] RISCV: Remove the v extension requirement for sat scalar run test

I see, thanks Jeff, just rerun it locally without new failures, will commit It soon. Pan -Original Message- From: Jeff Law Sent: Thursday, July 10, 2025 9:22 AM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken ; Liu,

[PATCH] Change bellow in comments to below

Hi! While I'm not a native English speaker, I believe all the uses of bellow (roar/bark/...) in comments in gcc are meant to be below (beneath/under/...). Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2025-07-10 Jakub Jelinek gcc/ * tree-vect-loop.cc (scale_pro

Re: [PATCH] Change bellow in comments to below

On Thu 2025-07-10 08:09:50, Jakub Jelinek wrote: > Hi! > > While I'm not a native English speaker, I believe all the uses > of bellow (roar/bark/...) in comments in gcc are meant to be > below (beneath/under/...). FWIW I went through the patch and I agree that all of these should be 'below', not

[PATCH] libatomic: Provide __atomic_test_and_set() alias

If the target does not support the atomic_flag_test_and_set() operation in hardware, the compiler emits a call to __atomic_test_and_set(). However, libatomic provided only __atomic_test_and_set_1(). Provide __atomic_test_and_set() as an alias. libatomic/ChangeLog: * libatomic_i.h (EXPOR

Re: [PATCH] aarch64: Extend HVLA permutations to big-endian

On Wed, Jul 9, 2025 at 7:07 AM Richard Sandiford wrote: > > TARGET_VECTORIZE_VEC_PERM_CONST has code to match the SVE2.1 > "hybrid VLA" DUPQ, EXTQ, UZPQ{1,2}, and ZIPQ{1,2} instructions. > This matching was conditional on !BYTES_BIG_ENDIAN. > > The ACLE code also lowered the associated SVE2.1 intr

Re: [PATCH v1] RISCV: Remove the v extension requirement for sat scalar run test

On 7/8/25 11:07 PM, pan2...@intel.com wrote: From: Pan Li The sat scalar run test should not require the v extension, thus take rv32 || rv64 instead of riscv_v for the requirement. The below test suites are passed for this patch series. * The rv64gcv fully regression test. * The rv32gcv ful

[pushed] c++: 'this' in lambda in noexcept-spec [PR121008]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- In r16-970 I changed finish_this_expr to look at current_class_type rather than current_class_ptr to accommodate explicit object lambdas. But here in a lambda in the noexcept-spec, the closure type doesn't yet have the function as its conte

[pushed] c++: generic lambda in template arg [PR121012]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- My r16-2065 adding missed errors for auto in a template arg in a lambda parameter also introduced a bogus error on this testcase, where the auto is both in a lambda parameter and in a template arg, but in the other order, which is OK. So we

Re: [Fortran, Patch, PR120711, v1] 1/(3) Fix out of bounds access in cleanup of array constructor

On Wed, Jul 09, 2025 at 08:50:08AM +0200, Andre Vehreschild wrote: > > why shall the testcase be invalid? See the 2nd bullet in Fortran 2023, 9.7.1.3 Allocation of allocatable variables. An allocatable variable has a status of "unallocated" if it is not allocated. ... An allocata

Re: [PATCH] aarch64: Fix endianness of DFmode vector constants

Hi Richard,   > aarch64_simd_valid_imm tries to decompose a constant into a repeating > series of 64 bits, since most Advanced SIMD and SVE immediate forms > require that.  (The exceptions are handled first.)  It does this by > building up a byte-level register image, lsb first.  If the image does

Re: [PATCH v1 0/2] Allow targets to avoid materializing split parameters via stack extension [PR/82106]

On 7/3/25 3:50 PM, Palmer Dabbelt wrote: This is really Jim's code, but it's been sitting around in Bugzilla for a while so I've picked it up. All I really did here is add a target hook and mangle some comments, but I think I understand enough about what's going on to try and get things movin

Re: [PATCH v2][PR117366] arm.cc: fix thumb1 size-optimized function prolog violates -ffixed-rX

Christophe, thank you very much for the detailed feedback. I re-posted the patches with your suggested changes to ChangeLog formatting, added line breaks for the long lines, and updated the test cases so you can now run them without the --target-board option. Regarding auto-merging, my changes a

[PATCH v3] arm.cc: fix thumb1 size-optimized function prolog violates -ffixed-rX [PR117366]

This patch fixes PR117366: arm thumb1 epilogue size optimizer violates -ffixed-r4. gcc/ChangeLog: PR target/117366 * arm.cc (thumb1_extra_regs_pushed): Take fixed regs into account. --- diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index bde06f3fa86..7bb829dbb04 100

Re: [AutoFDO] Fix get_original_name to strip only names that are generated after auto-profile

HI Honza, > On 9 Jul 2025, at 10:23 pm, Jan Hubicka wrote: > > External email: Use caution opening links or attachments > > >> >> I am seeing an ICEs in offline pass. >> >> >> during IPA pass: afdo_offline >> gmsh/src/mesh/meshGEdge.cpp:979:1: internal compiler error: in >> set_call_locati

[PATCH 1/2] RTEMS: Format sparc/t-rtems

Change the format to easier associate multilib options with dirnames. gcc/ChangeLog: * config/sparc/t-rtems: Format. --- gcc/config/sparc/t-rtems | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index beb

[PATCH 2/2] RTEMS: Add sparc/leon5 multilibs

gcc/ChangeLog: * config/sparc/t-rtems: Add -mcpu=leon5 and -msoft-float -mcpu=leon5 multilibs. --- gcc/config/sparc/t-rtems | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index 22c4a1b2635..a152a4c1d79

[PATCH] gcov: Split atomic bitwise-or for some targets

There are targets, which only offer 32-bit atomic operations (for example 32-bit RISC-V). For these targets, split the 64-bit atomic bitwise-or operation into two parts. For this test case int a(int i); int b(int i); int f(int i) { if (i) { return a(i); } else { return b(i); } }

[PATCH] RTEMS: Add riscv multilibs

gcc/ChangeLog: * config/riscv/t-rtems: Add -mstrict-align multilibs for targets without support for misaligned access in hardware. --- gcc/config/riscv/t-rtems | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/t-rtems b/gcc/config/ris

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