[PATCH] tree-optimization/120654 - ICE with range query from IVOPTs

The following ICEs as we hand down an UNDEFINED range to where it isn't expected. Put the guard that's there earlier. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. PR tree-optimization/120654 * vr-values.cc (range_fits_type_p): Check for undefined_p () be

[PATCH] fortran: Mention user variable in SELECT TYPE temporary variable names

From: Mikael Morin Regression-tested on x86_64-pc-linux-gnu. Ok for master? -- >8 -- The temporary variables that are generated to implement SELECT TYPE and TYPE IS statements have (before this change) a name depending only on the type. This can produce confusing dumps with code having multi

Re: [PATCH v1] RISC-V: Fix ICE for expand_select_vldi [PR120652]

Hi Pan, +(define_special_predicate "vectorization_factor_operand" + (match_code "const_int,const_poly_int")) + Does immediate_operand () work instead of a new predicate? -- Regards Robin

[PATCH] vregs: Use force_subreg when instantiating subregs [PR120721]

In this PR, we started with: (subreg:V2DI (reg:DI virtual-reg) 0) and vregs instantiated the virtual register to the argument pointer. But: (subreg:V2DI (reg:DI ap) 0) is not a sensible subreg, since the argument pointer certainly can't be referenced in V2DImode. This is (IMO correctly

Re: [PATCH v5 2/3][__bdos]Use the counted_by attribute of pointers in builtinin-object-size.

Hi, Sid, Thanks a lot for the review. I will update the testing cases per your suggestions. > On Jun 19, 2025, at 12:07, Siddhesh Poyarekar wrote: > > On 2025-06-16 18:08, Qing Zhao wrote: >> gcc/ChangeLog: >> * tree-object-size.cc (access_with_size_object_size): Handle pointers >> with count

Re: [PATCH v5 1/3][C FE] Extend "counted_by" attribute to pointer fields of structures.

> On Jun 18, 2025, at 17:23, Joseph Myers wrote: > > On Mon, 16 Jun 2025, Qing Zhao wrote: > >> +The counted_by attribute is not allowed for a pointer to @code{void}, > > @code{counted_by}. > > This patch is OK with that fix once the rest of this series is approved. Thanks a lot for the re

Re: [PATCH v4 1/4] Hard register constraints

On 5/20/25 3:22 AM, Stefan Schulze Frielinghaus wrote: Implement hard register constraints of the form {regname} where regname must be a valid register name for the target. Such constraints may be used in asm statements as a replacement for register asm and in machine descriptions. --- gcc/c

[PATCH] tree-optimization/120729 - limit compile time in uninit_analysis::prune_phi_opnds

The testcase in this PR shows, on the GCC 14 branch, that in some degenerate cases we can spend exponential time pruning always initialized paths through a web of PHIs. The following adds --param uninit-max-prune-work, defaulted to 10, to limit that to effectively O(1). Bootstrap and regtest

Re: [PATCH v2] Evaluate the object size by the size of the pointee type when the type is a structure with flexible array member which is annotated with counted_by.

> On Jun 18, 2025, at 20:51, Siddhesh Poyarekar wrote: > > On 2025-06-18 18:40, Qing Zhao wrote: Okay, I guess that I didn’t put enough attention on the above example previously, sorry about that... Read it multiple times this time, my question is for the following code po

[PATCH v2] RISC-V: Fix ICE for expand_select_vldi [PR120652]

From: Pan Li The will be one ICE when expand pass, the bt similar as below. during RTL pass: expand red.c: In function 'main': red.c:20:5: internal compiler error: in require, at machmode.h:323 20 | int main() { | ^~~~ 0x2e0b1d6 internal_error(char const*, ...) ../../../gcc/

Re: [PATCH v2] RISC-V: Fix ICE for expand_select_vldi [PR120652]

OK, thanks. -- Regards Robin

Re: [PATCH v2] RISC-V: Fix ICE for expand_select_vldi [PR120652]

On 6/20/25 7:04 AM, pan2...@intel.com wrote: From: Pan Li The will be one ICE when expand pass, the bt similar as below. during RTL pass: expand red.c: In function 'main': red.c:20:5: internal compiler error: in require, at machmode.h:323 20 | int main() { | ^~~~ 0x2e0b1d6 in

[PATCH] Add string_slice class.

Thanks for the pointer Joseph. This update adds tests to gcc/testsuite/g++.dg/warn/Wformat-gcc_diag-1.C as this seems to be where similar tests are done (eg, %D for tree). I couldn't find any tests for the actual output of string slice debug statements for the other format specifiers so haven't i

Re: [PATCH v5 3/3][C sanitizer] Use the counted_by attribute of pointers in array bound checker.

> On Jun 18, 2025, at 17:26, Joseph Myers wrote: > > On Mon, 16 Jun 2025, Qing Zhao wrote: > >> Current array bound checker only instruments ARRAY_REF, and the INDEX >> information is the 2nd operand of the ARRAY_REF. >> >> When extending the array bound checker to pointer references with >>

[PATCH] match: Simplify double not and double negate to a non_lvalue

From: Mikael Morin Regression tested on x86_64-linux. OK for master? -- 8< -- gcc/ChangeLog: * match.pd (`-(-X)`, `~(~X)`): Add a NON_LVALUE_EXPR wrapper to the simplification of doubled unary operators NEGATE_EXPR and BIT_NOT_EXPR. gcc/testsuite/ChangeLog: *

[committed] amdgcn: allow SImode in VCC_HI [PR120722]

This patch isn't fully tested yet, but it fixes the build failure, so that will do for now. SImode was not allowed in VCC_HI because there were issues, way back before the port went upstream, so it's possible we'll find out what those issues were again soon. gcc/ChangeLog: PR target/1207

[PATCH] s390: Fix float vector extract for pre-z13

Also provide the vec_extract patterns for floats on pre-z13 machines to prevent ICEing in those cases. Bootstrapped and regtested on s390. gcc/ChangeLog: * config/s390/vector.md (VF): Don't restrict modes. * config/s390/vector.md (VEC_SET_SINGLEFLOAT): Ditto. gcc/testsuite/Chang

[PATCH] AArch64: Disable TARGET_CONST_ANCHOR

TARGET_CONST_ANCHOR appears to trigger too often, even on simple immediates. It inserts extra ADD/SUB instructions even when a single MOV exists. Disable it to improve overall code quality: on SPEC2017 it removes 1850 ADD/SUB instructions and 630 spill instructions, and SPECINT is ~0.06% faster on

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Re: [PATCH, 4 of 4] Use vector pair for memory operations with -mcpu=future

Hi Mike, On 14/06/25 2:13 pm, Michael Meissner wrote: > This is patch #4 of 4 to add -mcpu=future support to the PowerPC. I think this should be a separate patch in itself. As such, this patch is not required to enable the -mcpu=future option. > > In the development for the power10 processor, G

Re: [PATCH, 4 of 4] Use vector pair for memory operations with -mcpu=future

Hi! On Fri, Jun 20, 2025 at 10:38:30PM +0530, Surya Kumari Jangala wrote: > On 14/06/25 2:13 pm, Michael Meissner wrote: > > This is patch #4 of 4 to add -mcpu=future support to the PowerPC. > > I think this should be a separate patch in itself. As such, this > patch is not required to enable the

[COMMITTED] PR tree-optimization/120701 - Fix range wrap check and enhance verify_range.

I wasn't checking the underflow and overflow conditions well enough in the original patch for range bound snapping.  THe testcxsed in this PR has a [+INF, +INF] subrange with a bitmask that said it must be an even value. The lower bound calculation overflowed (+INF + 1}, but it was not detect

[PATCH] x86: Don't use vmovdqu16/vmovdqu8 with non-EVEX registers

Don't use vmovdqu16/vmovdqu8 with non-EVEX registers even if AVX512BW is available. gcc/ PR target/120728 * config/i386/i386.cc (ix86_get_ssemov): Use vmovdqu16/vmovdqu8 only with EVEX registers. gcc/testsuite/ PR target/120728 * gcc.target/i386/pr120728.c: New test. -- H.J. From fb8db1e46aa

Re: [PATCH] x86: Get the widest vector mode from MOVE_MAX

On Thu, Jun 19, 2025 at 1:27 PM H.J. Lu wrote: > > Since MOVE_MAX defines the maximum number of bytes that an instruction > can move quickly between memory and registers, use it to get the widest > vector mode in vector loop when inlining memcpy and memset. > > gcc/ > > PR target/120708 > * config

Re: [PATCH 0/2] Memory leak fixes in prime paths [PR120634]

Thanks, pushed. On 6/20/25 12:18, Richard Biener wrote: On Thu, Jun 19, 2025 at 11:21 PM Jørgen Kvalsvik wrote: Hi, These patches fixes a memory leak in the prime paths, and some in the selftests that show up in make selftest-valgrind. After applying these patches on my x86-64-linux-gnu syst

Re: [PATCH 0/2] Memory leak fixes in prime paths [PR120634]

On Thu, Jun 19, 2025 at 11:21 PM Jørgen Kvalsvik wrote: > > Hi, > > These patches fixes a memory leak in the prime paths, and some in the > selftests that show up in make selftest-valgrind. After applying these > patches on my x86-64-linux-gnu system and make selftest-valgrind: OK. Thanks, Richa

Re: [RFC PATCH] gimple-simulate: Add a gimple IR interpreter/simulator

On Thu, Jun 19, 2025 at 12:13 PM Mikael Morin wrote: > > Le 18/06/2025 à 16:51, Richard Biener a écrit : > > On Wed, Jun 18, 2025 at 11:23 AM Mikael Morin > > wrote: > >> > >> From: Mikael Morin > >> > >> Hello, > >> > >> I'm proposing here an interpretor/simulator of the gimple IR. > >> It pro

[PATCH] mklog.py: Add main function

Hi, This adds a main() function to mklog.py (like e.g. check_GNU_style.py has), which makes it easier to import and invoke from another python script. This is useful when using a wrapper script to set up the python environment. Smoke tested by using the modified mklog.py to generate the ChangeLo

Re: [PATCH v5 2/3][__bdos]Use the counted_by attribute of pointers in builtinin-object-size.

> On Jun 19, 2025, at 12:16, Siddhesh Poyarekar wrote: > > On 2025-06-19 12:07, Siddhesh Poyarekar wrote: >> On 2025-06-16 18:08, Qing Zhao wrote: >>> gcc/ChangeLog: >>> >>> * tree-object-size.cc (access_with_size_object_size): Handle pointers >>> with counted_by. >> This should probab

RE: [PATCH v1] RISC-V: Fix ICE for expand_select_vldi [PR120652]

> Does immediate_operand () work instead of a new predicate? Thanks Robin, the immediate_operand works well here, let me send v2 if no surprise from test. Pan -Original Message- From: Robin Dapp Sent: Friday, June 20, 2025 5:29 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...

[PATCH v1 1/3] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

From: Pan Li This patch would like to combine the vec_duplicate + vsaddu.vv to the vsaddu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if

[PATCH v1 0/3] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

From: Pan Li This patch would like to introduce the combine of vec_dup + vsaddu.vv into vsaddu.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 2, 15 in test. There will be two cases for the combine: Case 0:

Extend afdo inliner to introduce speculative calls

Hi, this patch makes the AFDO's VPT to happen during early inlining. This should make the einline pass inside afdo pass unnecesary, but some inlining still happens there - I will need to debug why that happens and will try to drop the afdo's inliner incrementally. get_inline_stack_in_node can now

[to-be-committed][RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

The RISC-V prefetch support is broken in a few ways. This addresses the data side prefetch problems. I'd mistakenly thought this BZ was a prefetch.i related (which has deeper problems). The basic problem is we were accepting any valid address when in fact there are restrictions. This patch

Re: [PATCH] AArch64: Disable TARGET_CONST_ANCHOR

On Fri, Jun 20, 2025, 4:47 PM Wilco Dijkstra wrote: > > TARGET_CONST_ANCHOR appears to trigger too often, even on simple > immediates. > It inserts extra ADD/SUB instructions even when a single MOV exists. > Disable it to improve overall code quality: on SPEC2017 it removes > 1850 ADD/SUB instruc