PATCH v2] x86: Enable *mov_(and|or_store) only for -Oz

2025-05-25 Thread H.J. Lu
On Sun, May 25, 2025 at 8:12 AM H.J. Lu wrote: > > On Sun, May 25, 2025 at 7:47 AM H.J. Lu wrote: > > > > commit ef26c151c14a87177d46fd3d725e7f82e040e89f > > Author: Roger Sayle > > Date: Thu Dec 23 12:33:07 2021 + > > > > x86: PR target/103773: Fix wrong-code with -Oz from pop to memo

Re: [PATCH] Enable mcf thread model for aarch64-*-mingw*.

2025-05-25 Thread LIU Hao
在 2025-5-16 16:50, LIU Hao 写道: This is a leftover of d6d7afcdbc04adb0ec42a44b2d7e05600945af42. After this change, configuration files of all three thread models are in 'libgcc/config/mingw/'. The patch has been bootstrapped on {x86_64,i686}-w64-mingw32. ARM64 port is still working in progress a

Re: [PATCH] i386: Quote user-defined symbols in assembly in Intel syntax

2025-05-25 Thread Jonathan Yong
On 5/20/25 3:06 AM, LIU Hao wrote: 在 2025-5-13 17:18, LIU Hao 写道: Hello, Attached is a patch for PR 53929, but is also required by PR 80881. Ping. Also I just notice that Clang also quotes mangled MSVC++ symbols in this way, at least since Clang 3.5, so it's accepted by both GAS and LLVM:

Re: [PATCH] Enable mcf thread model for aarch64-*-mingw*.

2025-05-25 Thread Jonathan Yong
On 5/16/25 8:50 AM, LIU Hao wrote: This is a leftover of d6d7afcdbc04adb0ec42a44b2d7e05600945af42. After this change, configuration files of all three thread models are in 'libgcc/config/mingw/'. The patch has been bootstrapped on {x86_64,i686}-w64-mingw32. ARM64 port is still working in prog

[PATCH v3] x86: Enable *mov_(and|or) only for -Oz

2025-05-25 Thread H.J. Lu
On Sun, May 25, 2025 at 7:02 PM H.J. Lu wrote: > > On Sun, May 25, 2025 at 8:12 AM H.J. Lu wrote: > > > > On Sun, May 25, 2025 at 7:47 AM H.J. Lu wrote: > > > > > > commit ef26c151c14a87177d46fd3d725e7f82e040e89f > > > Author: Roger Sayle > > > Date: Thu Dec 23 12:33:07 2021 + > > > > > >

Re: [PATCH] aarch64: Use LDR for first-element loads for Advanced SIMD

2025-05-25 Thread Dhruv Chawla
On 08/05/25 18:43, Richard Sandiford wrote: External email: Use caution opening links or attachments Dhruv Chawla writes: This patch modifies Advanced SIMD assembly generation to emit an LDR instruction when a vector is created using a load to the first element with the other elements being z

Re: [AUTOFDO][AARCH64] Add support for profilebootstrap

2025-05-25 Thread Andrew Pinski
On Tue, May 20, 2025 at 3:09 AM Kugan Vivekanandarajah wrote: > > Thanks Richard for the review. > > > On 20 May 2025, at 2:47 am, Richard Sandiford > > wrote: > > > > External email: Use caution opening links or attachments > > > > > > Kugan Vivekanandarajah writes: > >> diff --git a/Makefile.

Re: [AUTOFDO][AARCH64] Add support for profilebootstrap

2025-05-25 Thread Kugan Vivekanandarajah
> On 26 May 2025, at 2:25 pm, Andrew Pinski wrote: > > External email: Use caution opening links or attachments > > > On Tue, May 20, 2025 at 3:09 AM Kugan Vivekanandarajah > wrote: >> >> Thanks Richard for the review. >> >>> On 20 May 2025, at 2:47 am, Richard Sandiford >>> wrote: >>> >>> Ex

Re: [PATCH] fortran: add constant input support for trig functions with half-revolutions

2025-05-25 Thread Steve Kargl
On Sun, May 25, 2025 at 04:56:48AM +, Yuao Ma wrote: > > Thanks for your review! I've updated the patch. > > > this range_check() is unneeded. > > Done. > > > As a side note, the error message is slightly misleading > > (although it will not be issued). Technically, x = -1 or 1 > > are all

[PATCH v1 0/3] RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost

2025-05-25 Thread pan2 . li
From: Pan Li This patch would like to introduce the combine of vec_dup + vxor.vv into vxor.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15 in test. There will be two cases for the combine: Case 0: | .

[PATCH v1 3/3] RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2

2025-05-25 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vxor.vv combine to vxor.vx, with the GR2VR cost is 0, 1 and 2. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add as

[PATCH v2] RISC-V: Add minimal support of double trap extension 1.0

2025-05-25 Thread Jerry Zhang Jian
Add support of double trap extension [1], enabling GCC to recognize the following extensions at compile time. New extensions: - ssdbltrp - smdbltrp [1] https://github.com/riscv/riscv-double-trap/releases/download/v1.0/riscv-double-trap.pdf gcc/ChangeLog: * config/riscv/riscv-ext.def

[pushed] c++: dump_template_bindings tweak

2025-05-25 Thread Jason Merrill
Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- in r12-1100 we stopped printing template bindings like T = T. The check for this relied on TREE_CHAIN of a TEMPLATE_TYPE_PARM holding the declaration of that type-parameter. This should be written as TYPE_STUB_DECL. In addition, TYPE_STUB