AREG, DREG, CREG and AD_REGS are kept in ix86_class_likely_spilled_p to
avoid the following regressions with
$ make check RUNTESTFLAGS="--target_board='unix{-m32,}'"
FAIL: gcc.dg/pr105911.c (internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1863)
FAIL: gcc.dg/pr105911.c (test
On 4/28/25 17:26, Andrew MacLeod wrote:
I have committed this patch to trunk after bootstrap/regression
testing again on trunk.
I'll get to gcc14/15 once I flush the current queue.
Andrew
On 4/17/25 06:44, Richard Biener wrote:
On Wed, Apr 16, 2025 at 10:55 PM Andrew MacLeod
wrote:
This
On 4/28/25 17:26, Andrew MacLeod wrote:
I have committed this patch to trunk after bootstrap/regression
testing again on trunk.
I'll get to gcc14/15 once I flush the current queue.
Andrew
On 1/23/25 04:39, Richard Biener wrote:
On Wed, Jan 22, 2025 at 12:49 AM Andrew MacLeod
wrote:
This p
On Tue, Apr 29, 2025 at 11:52 PM Jonathan Wakely wrote:
> On Tue, 29 Apr 2025 at 14:55, Tomasz Kaminski wrote:
> >
> >
> >
> > On Tue, Apr 29, 2025 at 2:55 PM Luc Grosheintz
> wrote:
> >>
> >> This implements std::extents from according to N4950 and
> >> contains partial progress towards PR107
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64
On Tue, Apr 29, 2025 at 3:53 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 9:34 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 2:33 PM H.J. Lu wrote:
> > >
> > > On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wro
On Tue, Apr 29, 2025 at 4:25 PM Andrew Pinski wrote:
>
> When we have an empty function, things can go wrong with
> cfi_startproc/cfi_endproc and a few other things like exceptions. So if
> the only thing the function does is a call to __builtin_unreachable,
> let's expand that to a __builtin_trap
---
gcc/sreal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/sreal.h b/gcc/sreal.h
index 8700807a131..c5aef1f3a82 100644
--- a/gcc/sreal.h
+++ b/gcc/sreal.h
@@ -118,7 +118,7 @@ public:
return min;
}
- /* Global minimum sreal can hold. */
+ /* Global maximum
On Wed, Apr 30, 2025 at 12:00 AM Andrew MacLeod wrote:
>
>
> On 3/28/25 10:36, Andrew MacLeod wrote:
> > On 3/28/25 03:19, Richard Biener wrote:
> >> On Fri, Mar 28, 2025 at 12:28 AM Andrew MacLeod
> >> wrote:
> >>> This patch fixes both 119471 and the remainder of 110992.
> >>>
> >>> At issue is
On Wed, Apr 30, 2025 at 12:00 AM Andrew MacLeod wrote:
>
>
> On 4/28/25 17:26, Andrew MacLeod wrote:
> > I have committed this patch to trunk after bootstrap/regression
> > testing again on trunk.
> >
> > I'll get to gcc14/15 once I flush the current queue.
> >
> > Andrew
> >
> >
> > On 4/17/25 06
On Wed, Apr 30, 2025 at 12:00 AM Andrew MacLeod wrote:
>
>
> On 4/28/25 17:26, Andrew MacLeod wrote:
> > I have committed this patch to trunk after bootstrap/regression
> > testing again on trunk.
> >
> > I'll get to gcc14/15 once I flush the current queue.
> >
> > Andrew
> >
> > On 1/23/25 04:39,
On Mon, Apr 28, 2025 at 07:27:31PM +0200, Josef Melcr wrote:
> As for the attribute, I am honestly not too sure about what to do, as clang
> is
> not consistent in with its own indexing, be it with the unknown values, or
> with
> 'this'. I've tried to remain consistent with GCC's indexing style. I
Seems CI still fail:
https://github.com/ewlu/gcc-precommit-ci/issues/3282#issue-3030037257
Executing on host:
/home/ewlu/precommit-08/_work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-newlib-stage2/gcc/xgcc
-B/home/ewlu/pre
commit-08/_work/gcc-precommit-ci/gcc-precommit-
On 29/04/2025 08:55, Jonathan Wakely wrote:
On Mon, 28 Apr 2025, 21:37 François Dumont, wrote:
Much better indeed, there is only the aligned_storage adaptation left.
It will simplify my big versioned namespace patch to use cxx11
abi, very
nice !
libstdc++: [_GLIBCX
Hi Dongyan:
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c
> b/gcc/testsuite/gcc.target/riscv/arch-46.c
> new file mode 100644
> index ..fb2bdf72597f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-optio
On Tue, 29 Apr 2025 at 14:55, Tomasz Kaminski wrote:
>
>
>
> On Tue, Apr 29, 2025 at 2:55 PM Luc Grosheintz
> wrote:
>>
>> This implements std::extents from according to N4950 and
>> contains partial progress towards PR107761.
>>
>> If an extent changes its type, there's a precondition in the s
Although we already try to set the mode needed to FRM_DYN after a function call,
there are still some corner cases where both FRM_DYN and FRM_DYN_CALL may appear
on incoming edges.
Therefore, we use TARGET_MODE_CONFLUENCE to tell GCC that FRM_DYN, FRM_DYN_CALL,
and FRM_DYN_EXIT modes are compatib
Hi,
As we will be landing patches for extends, this will become a separate
patch series.
I would prefer, if you could commit per layout, and start with layout_right
(default)
I try to provide prompt responses, so if that works better for you, you can
post a patch
only with this layout first, as mo
Kind of surprise that this change doesn't make any of the existing frm tests
fail(given we have many frm tests).
No comment from myside.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, April 29, 2025 11:35 AM
To: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64
Thanks Robin for help.
> as I suggested initializes total with an estimate of the mode size (total = 8
> for me) before we get to riscv_rtx_cost. This makes the rest of the
> costs (which we assume to be relative to 4) inaccurate.
I see, that explains how cost value 8 comes from.
> Then we sho
Random-typo-spotting-mode activated:
On Sat, 19 Apr 2025, Andrew Pinski wrote:
> +++ b/gcc/testsuite/gcc.dg/tree-ssa/calloc-10.c
> +/* zeroing out via a CONSTRUCTOR should be treated similarly as a msmet and
"memset"
> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/calloc-11.c
> b/gcc/testsuite/gc
LGTM
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2025-04-29 11:35
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li;
vineetg
CC: Kito Cheng
Subject: [PATCH] RISC-V: Allow different dynamic floating point mode to be
merged [PR119832]
Although we already try to set
> -Original Message-
> From: Jan Hubicka
> Sent: Wednesday, April 30, 2025 4:11 AM
> To: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ro...@nextmovesoftware.com; ubiz...@gmail.com
> Subject: Make ix86 cost of VEC_SELECT equivalent to SUBREG same as of
> SUBREG
>
> Hi,
> this patch (partly
On 3/28/25 10:36, Andrew MacLeod wrote:
On 3/28/25 03:19, Richard Biener wrote:
On Fri, Mar 28, 2025 at 12:28 AM Andrew MacLeod
wrote:
This patch fixes both 119471 and the remainder of 110992.
At issue is we do not recognize that if
"a * b != 0" , then neither "a" nor "b" can be zero.
LGTM, but pending for the spec ratified, also a minor comment is the
link seems dead, we may use
https://github.com/riscv/riscv-isa-manual/pull/1907 instead
On Fri, Mar 21, 2025 at 8:56 AM Mingzhu Yan wrote:
>
> This patch support svrsw60t59b extension[1].
> To enable GCC to recognize and process
Because MIPS function symbol is generated in the prologue function,
this nop generation should be done in prologue.
OK for trunk?
PR target/99217
gcc/ChangeLog:
* config/mips/mips.cc (mips_start_function_definition):
Implements the functionality of '-fpatchable-function-e
On 3/28/25 05:25, Jakub Jelinek wrote:
On Fri, Mar 28, 2025 at 08:12:35AM +0100, Richard Biener wrote:
On Thu, Mar 27, 2025 at 8:14 PM Andrew MacLeod wrote:
This patch backports the ASSUME support that was rewritten in GCC 15.
Its slightly more complicated than the port to GCC 14 was in that
Skip sub-RTXes of the memory operand if stack access register is
not mentioned in the operand.
gcc/ChangeLog:
* config/i386/i386.cc (ix86_update_stack_alignment): Skip sub-RTXes
of the memory operand if stack access register is not mentioned in
the operand.
Bootstrapped and regressio
These patch makes following changes to _Pres_type values:
* _Pres_esc is replaced with separate _M_debug flag.
* _Pres_s, _Pres_p do not overlap with _Pres_none.
* hexadecimal presentation use same values for pointer, integer
and floating point types.
Instead of `_M_reserved` and `_M_reserve
On Tue, Apr 29, 2025 at 9:56 AM H.J. Lu wrote:
>
> Don't expand UNSPEC_TLS_LD_BASE to a call so that the RTL local copy
> propagation pass can eliminate multiple __tls_get_addr calls.
__tls_get_addr needs to be called with 16-byte aligned stack, I don't
think the compiler will correctly handle re
On Tue, Apr 29, 2025 at 10:58 AM Jonathan Wakely wrote:
> This will hardly make a dent in the very slow compile times for
> but it seems worth doing anyway.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/regex_compiler.h: Replace _GLIBCXX17_CONSTEXPR
> with constexpr and disable
On Tue, Apr 29, 2025 at 11:05 AM Jonathan Wakely wrote:
> Replace remaining uses of _GLIBCXX17_CONSTEXPR for constexpr-if, so that
> we always use constexpr-if in C++11 and C++14. Diagnostic pragmas are
> used to suppress diagnostics.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/char_tr
MOVS instructions allow segment override of their source operand, e.g.:
rep movsq %gs:(%rsi), (%rdi)
where %rsi is the address of the source location (with %gs segment override)
and %rdi is the address of the destination location.
The testcase improves from (-O2 -mno-sse -mtune=generic):
Fixed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119317
Tested on AArch64 using the test case provided by the bug
reporter:
int fun()
{
main:
while(1)
continue main;
}
Without the fix, this program failed to compile:
test.c: In function ‘fun’:
test.c:5:14: error: ‘continue’ statement
Uses the FTM infrastructure to create an internal feature testing macro
for partial availability of mdspan; which is then used to hide the
contents of the header mdspan when compiling against a standard prior to
C++23.
libstdc++-v3/ChangeLog:
* include/bits/version.def: Add internal featu
Implement the parts of layout_left that depend on layout_right; and the
parts of layout_right that don't depend on layout_stride.
libstdc++/ChangeLog:
* include/std/mdspan (layout_right): New class.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 147 +++
This patch series follows up on:
https://gcc.gnu.org/pipermail/libstdc++/2025-April/061078.html
As agreed, I'm appending commits that add the layouts to this patch
series. Each layout is added in a separate commit and tests are added in
the immediately following commit.
Changes since v4 to std::e
This implements std::extents from according to N4950 and
contains partial progress towards PR107761.
If an extent changes its type, there's a precondition in the standard,
that the value is representable in the target integer type. This
precondition is not checked at runtime.
The precondition fo
Adds tests for layout_right and for the parts of layout_left that depend
on layout_right.
libstdc++/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add
tests for layout_stride.
* testsuite/23_containers/mdspan/layouts/ctors.cc: Add tests for
A prior commit added std::extents, this commit adds the tests. The bulk
is focussed on testing the constructors. These are split into three
groups:
1. the ctor from other extents and the copy ctor,
2. the ctor from a pack of integer-like objects,
3. the ctor from shapes, i.e. span and array.
For
Implements the parts of layout_left that don't depend on any of the
other layouts.
libstdc++/ChangeLog:
* include/std/mdspan (layout_left): New class.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 179
1 file changed, 179 insertion
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look
OK for trunk/15/14?
-- >8 --
In r15-123 and r14-11434 we unconditionally set processing_template_decl
when substituting the context of an UNBOUND_CLASS_TEMPLATE, in order to
handle instantiation of the dependently scoped friend dec
Implements the remaining parts of layout_left and layout_right; and all
of layout_stride.
libstdc++/ChangeLog:
* include/std/mdspan(layout_stride): New class.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 227
1 file changed, 227 i
Named loops (C2y) could not previously be compiled with
-O1 and -ggdb2 or higher because the label preceding
a loop (or switch) could not be found when using such
command lines.
This could be observed by compiling
gcc/gcc/testsuite/gcc.dg/c2y-named-loops-1.c with
the provoking command line (or any
Implements a suite of tests for the currently implemented parts of
layout_left. The individual tests are templated over the layout type, to
allow reuse as more layouts are added.
libstdc++/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: New test.
* testsu
Implements the tests for layout_stride and for the features of the other
two layouts that depend on layout_stride.
libstdc++/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add
tests for layout_stride.
* testsuite/23_containers/mdspan/layouts/ctor
Seems like the testcase will fail
https://github.com/ewlu/gcc-precommit-ci/issues/3278#issuecomment-2837806049
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c
> b/gcc/testsuite/gcc.target/riscv/predef-19.c
> index 2b90702192b..b29e60f9b99 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr
From: yulong
This version is same as v5, but rebase to trunk, send out to trigger CI.
This commit adds intrinsics support for Xsfvcp extension.
Diff with V4: Delete the sifive_vector.h file.
Co-Authored by: Jiawei Chen
Co-Authored by: Shihua Liao
Co-Authored by: Yixuan Chen
gcc/ChangeLog:
On Tue, 29 Apr 2025 at 13:59, Luc Grosheintz wrote:
>
> Creates a nearly empty header mdspan and adds it to the build-system and
> Doxygen config file.
>
> libstdc++-v3/ChangeLog:
>
> * doc/doxygen/user.cfg.in: Add .
> * include/Makefile.am: Ditto.
> * include/Makefile.in:
From: yulong
This commit adds testcases for Xsfvcp.
Co-Authored by: Jiawei Chen
Co-Authored by: Shihua Liao
Co-Authored by: Yixuan Chen
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
I see, let the vec_dup enter the rtx_cost again to append the total to vmv, I
have a try testing. For example with below change:
+ switch (rcode)
+ {
+ case VEC_DUPLICATE:
+ *total += get_vector_costs ()->regmove->GR2VR * COSTS_N_INSNS (1);
+ break;
+
On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wrote:
> > > >
> > > > For targets, like x86, which define TARGET_PROMO
LGTM, and pushed to the trunk :)
On Mon, Apr 28, 2025 at 10:04 AM 曾治金 wrote:
>
> Hi, according to Jeff's requirement
> (https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681864.html), I divide
> the change of riscv_register_move_cost into separate patch. Please help to
> review. Thanks.
>
>
On Tue, 29 Apr 2025 at 13:54, Luc Grosheintz wrote:
>
> This implements std::extents from according to N4950 and
> contains partial progress towards PR107761.
>
> If an extent changes its type, there's a precondition in the standard,
> that the value is representable in the target integer type. T
在 2025-4-29 13:03, LIU Hao 写道:
This fixes a long-standing issue that GCC used to assume 16-byte stack alignment on i686-w64-mingw32,
which is not always the case for callbacks from system libraries.
CC Zeb Figura
This patch looks a bit risky. The overall effect of `__attribute__((__force_ali
The following makes PRE handle &ptr->field the same as VN by
treating it as a POINTER_PLUS_EXPR when possible and thus as
'nary'. To facilitate this the patch splits out vn_pp_nary_for_addr
and adds const overloads for vec::last. The patch also avoids
handling an effective zero offset as POINTER_
On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
> > >
> > > On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wr
On Tue, Apr 29, 2025 at 5:52 PM Uros Bizjak wrote:
>
> MOVS instructions allow segment override of their source operand, e.g.:
>
> rep movsq %gs:(%rsi), (%rdi)
>
> where %rsi is the address of the source location (with %gs segment override)
> and %rdi is the address of the destination location
Hi all,
Here is the updated patch that address some of the @Jeff Law comments .
P8700 don't have a vector engine and we support the insns type till
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.md#L358
and schedule module enabled the same .
---
gcc/config/riscv/mips
On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
On Tue, Apr 29, 2025 at 6:49 PM Uros Bizjak wrote:
>
> On Tue, Apr 29, 2025 at 12:41 PM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 5:52 PM Uros Bizjak wrote:
> > >
> > > MOVS instructions allow segment override of their source operand, e.g.:
> > >
> > > rep movsq %gs:(%rsi), (%rdi)
> > >
On Tue, Apr 29, 2025 at 2:33 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
> > >
> > > On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wr
I see, let the vec_dup enter the rtx_cost again to append the total to vmv, I
have a try testing. For example with below change:
+ switch (rcode)
+ {
+ case VEC_DUPLICATE:
+ *total += get_vector_costs ()->regmove->GR2VR * COSTS_N_INSNS
(1);
+ break;
+
This RFC series shows the steps that I believe are relevant to using automatic
make depencies, and optionally automatic make rules, in the aarch64 backend. I
believe the same steps and caveats would apply to other backends as well.
This builds upon the work by Tom Tromey in 2013 (see e.g. [1]), w
On Tue, Apr 29, 2025 at 12:58 PM Tomasz Kaminski
wrote:
>
>
> On Tue, Apr 29, 2025 at 9:28 AM Tomasz Kamiński
> wrote:
>
>> These patch makes following changes to _Pres_type values:
>> * _Pres_esc is replaced with separate _M_debug flag.
>> * _Pres_s, _Pres_p do not overlap with _Pres_none.
>>
On Tue, Apr 29, 2025 at 9:28 AM Tomasz Kamiński wrote:
> These patch makes following changes to _Pres_type values:
> * _Pres_esc is replaced with separate _M_debug flag.
> * _Pres_s, _Pres_p do not overlap with _Pres_none.
> * hexadecimal presentation use same values for pointer, integer
>
On Tue, Apr 29, 2025 at 12:41 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 5:52 PM Uros Bizjak wrote:
> >
> > MOVS instructions allow segment override of their source operand, e.g.:
> >
> > rep movsq %gs:(%rsi), (%rdi)
> >
> > where %rsi is the address of the source location (with %gs segmen
Jennifer Schmitz writes:
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index f7bccf532f8..1c06b8528e9 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -6416,13 +6416,30 @@ aarch64_stack_protect_canary_mem (machine_mode mode,
Creates a nearly empty header mdspan and adds it to the build-system and
Doxygen config file.
libstdc++-v3/ChangeLog:
* doc/doxygen/user.cfg.in: Add .
* include/Makefile.am: Ditto.
* include/Makefile.in: Ditto.
* include/precompiled/stdc++.h: Ditto.
* inclu
On Tue, 29 Apr 2025 at 13:54, Luc Grosheintz wrote:
>
> This implements std::extents from according to N4950 and
> contains partial progress towards PR107761.
>
> If an extent changes its type, there's a precondition in the standard,
> that the value is representable in the target integer type. T
This might miss some dependencies when doing an incremental build where
the previous build did not include generated dependency files, and the
.cc file has not subsequently changed (but another dependency has).
gcc/ChangeLog:
* config/aarch64/t-aarch64: Remove explicit .o dependencies.
The change to gcc/configure is a hack to illustrate where we need extra
arguments available. If the rest of the change is desirable, then we
could define a new variable to include these extra directories.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
6dbe880c9d45369a0128d79f5fa30ca07faf953
The following makes get_later_stmt handle stmts from different
basic-blocks in the case they are orderd and otherwise asserts.
Bootstrap/regtest running on x86_64-unknown-linux-gnu.
* tree-vectorizer.h (get_later_stmt): Robustify against
stmts in different BBs, assert when they ar
This also improves consistency of the compile commands, and eliminates
an ALL_SPPFLAGS typo.
gcc/ChangeLog:
* config/aarch64/t-aarch64: Use $(COMPILE) and $(POSTCOMPILE)
diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64
index
59571948479c0857df2cca70b18df6c5d9a72
The following adds checks that when we search for a vector stmt
insert location we arrive at one where all required operand defs
are dominating the insert location. At the moment any such
failure only blows up during SSA verification.
There's the long-standing issue that we do not verify there
ex
On Tue, Apr 29, 2025 at 9:34 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 2:33 PM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
>
On Tue, Apr 29, 2025 at 2:55 PM Luc Grosheintz
wrote:
> This implements std::extents from according to N4950 and
> contains partial progress towards PR107761.
>
> If an extent changes its type, there's a precondition in the standard,
> that the value is representable in the target integer type.
On Tue, 29 Apr 2025 at 13:56, Luc Grosheintz wrote:
>
> Implements the parts of layout_left that don't depend on any of the
> other layouts.
>
> libstdc++/ChangeLog:
N.B. this needs to be libstdc++-v3/Changelog with "-v3", or the git
hooks will reject it. Similarly in patches 6/10 to 10/10.
Ther
On Tue, Apr 29, 2025 at 11:27 AM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 10:08 AM Hongtao Liu wrote:
> >
> > On Mon, Apr 28, 2025 at 5:07 PM H.J. Lu wrote:
> > >
> > > On Mon, Apr 28, 2025 at 4:26 PM H.J. Lu wrote:
> > > >
> > >
> > > > > > This is what my patch does:
> > > > > But it iterat
On Tue, Apr 29, 2025 at 2:51 PM Liu, Hongtao wrote:
>
>
>
> > -Original Message-
> > From: H.J. Lu
> > Sent: Tuesday, April 29, 2025 1:58 PM
> > To: Hongtao Liu
> > Cc: GCC Patches ; Uros Bizjak
> > ; Liu, Hongtao
> > Subject: Re: [PATCH] i386: Add
> > ix86_expand_unsigned_small_int_cst
> -Original Message-
> From: H.J. Lu
> Sent: Tuesday, April 29, 2025 2:59 PM
> To: Hongtao Liu
> Cc: GCC Patches ; Liu, Hongtao
> ; Uros Bizjak
> Subject: [PATCH v3] x86: Add a pass to remove redundant all 0s/1s vector
> load
>
> On Tue, Apr 29, 2025 at 11:27 AM H.J. Lu wrote:
> >
>
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64
On Tue, Apr 29, 2025 at 11:01 AM Jonathan Wakely wrote:
> This allows removing the _Target_handler class template, because it's no
> longer needed to prevent instantiating invalid specializations of
> _Function_handler.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/std_function.h (_Targe
On Tue, Apr 29, 2025 at 10:49 AM Jonathan Wakely wrote:
> I made a last-minute change to Nina's r10-200-gf4e678ef74b272
> implementation of P1165R1 (consistent allocator propagation for
> operator+ on strings), so that the rvalue+rvalue case assumes that COW
> strings do not support stateful allo
On Tue, 29 Apr 2025, Richard Sandiford wrote:
> Pengfei Li writes:
> > This patch implements the folding of a vector addition followed by a
> > logical shift right by 1 (add + lsr #1) on AArch64 into an unsigned
> > halving add, allowing GCC to emit NEON or SVE2 UHADD instructions.
> >
> > For ex
Don't expand UNSPEC_TLS_LD_BASE to a call so that the RTL local copy
propagation pass can eliminate multiple __tls_get_addr calls.
gcc/
PR target/81501
* config/i386/i386-protos.h (ix86_split_tls_local_dynamic_base_64):
New.
* config/i386/i386.cc (ix86_split_tls_local_dynamic_base_64): New.
(legi
Bootstrapped and regtested on x86_64-pc-linux-gnu (so far just
modules.exp), OK for trunk and 15 if full regtest succeeds?
-- >8 --
In r15-9136-g0210bedf481a9f we started erroring for inline variables
that exposed TU-local entities in their definition, as such variables
would need to have their d
On Tue, Apr 29, 2025 at 3:49 AM H.J. Lu wrote:
>
> Since TARGET_PROMOTE_FUNCTION_RETURN is no longer used, remove its
> reference from target.def.
>
> PR target/119985
> * target.def: Remove TARGET_PROMOTE_FUNCTION_RETURN reference.
> * doc/tm.texi: Regenerated.
>
> OK for master?
OK.
Richard.
From: "hongtao.liu"
> another thing, you can save the walk over PHI args by using
>
> gimple_phi_arg_location (phi, tmp_e->dest_idx);
>
Changed, use gimple_phi_arg_location_from_edge (phi, tmp_e);
For an empty BB with all debug_stmt, it will be ignored by
afdo_set_bb
From: Arthur Cohen
Hi everyone,
We noticed inconsistent errors when running name-resolution 2.0 on
certain files, where an invalid error was triggered and the message was
from the `funny_ice` error finalizer function we had added as an easter
egg. We realized yesterday that the undefined value w
On Tue, Apr 29, 2025 at 10:21 AM liuhongt wrote:
>
> From: "hongtao.liu"
>
> > another thing, you can save the walk over PHI args by using
> >
> > gimple_phi_arg_location (phi, tmp_e->dest_idx);
> >
> Changed, use gimple_phi_arg_location_from_edge (phi, tmp_e);
>
>
>
Pengfei Li writes:
> This patch implements the folding of a vector addition followed by a
> logical shift right by 1 (add + lsr #1) on AArch64 into an unsigned
> halving add, allowing GCC to emit NEON or SVE2 UHADD instructions.
>
> For example, this patch helps improve the codegen from:
> a
On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wrote:
>
> For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return
> true, all integer arguments smaller than int are passed as int:
>
> [hjl@gnu-tgl-3 pr14907]$ cat x.c
> extern int baz (char c1);
>
> int
> foo (char c1)
> {
> return baz (
On Tue, Apr 29, 2025 at 1:26 AM wrote:
>
> From: Arthur Cohen
>
> Hi everyone,
>
> We noticed inconsistent errors when running name-resolution 2.0 on
> certain files, where an invalid error was triggered and the message was
> from the `funny_ice` error finalizer function we had added as an easter
All of reduce, transform_reduce, exclusive_scan, and inclusive_scan,
transform_exclusive_scan, and transform_inclusive_scan have a
precondition that the type of init meets the Cpp17MoveConstructible
requirements. It isn't required to be copy constructible, so when
passing it to the next internal fu
On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wrote:
> >
> > For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return
> > true, all integer arguments smaller than int are passed as int:
> >
> > [hjl@gnu-tgl-3 pr14907]$ cat x.c
> >
April 29, 2025 at 10:39 AM, "Andrew Pinski" mailto:pins...@gmail.com?to=%22Andrew%20Pinski%22%20%3Cpinskia%40gmail.com%3E >
wrote:
>
> On Tue, Apr 29, 2025 at 1:26 AM wrote:
>
> >
> > From: Arthur Cohen
> >
> > Hi everyone,
> >
> > We noticed inconsistent errors when running name-resolu
I made a last-minute change to Nina's r10-200-gf4e678ef74b272
implementation of P1165R1 (consistent allocator propagation for
operator+ on strings), so that the rvalue+rvalue case assumes that COW
strings do not support stateful allocators. I don't think that was true
when the change went in, and c
Simplify std::vector's use of std::__relocate_a by using 'if constexpr'
even in C++11 and C++14, with diagnostic pragmas to disable warnings.
This allows us to call std::__relocate_a directly, instead of via
_S_relocate and tag distpatching.
Preserve _S_relocate so that explicit instantiations sti
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