Re: [PATCH] libgccjit: Fix GGC segfault when using -flto

Here's the updated patch. The failure was due to the test being in the test array while it should not have been there since it changes the context. Thanks for the review. On Sun, 2023-11-12 at 18:03 -0500, David Malcolm wrote: > On Fri, 2023-11-10 at 18:14 -0500, David Malcolm wrote: > > On Fri,

Re: [PATCH] libgccjit: Add vector permutation and vector access operations

All of these are fixed in this new patch. Thanks for the review. On Mon, 2023-11-20 at 18:05 -0500, David Malcolm wrote: > On Fri, 2023-11-17 at 17:36 -0500, Antoni Boucher wrote: > > Hi. > > This patch adds a vector permutation and vector access operations > > (bug > > 112602). > > > > This was

[PATCH] btf: fix PR debug/112768

PR debug/112768 - btf: fix asm comment output for BTF_KIND_FUNC* kinds The patch adds a small function to abstract out the detail and return the name of the type. The patch also fixes the issue of BTF_KIND_FUNC appearing in the comments with a 'null' string. For btf-function-6.c testcase, after

Re: [PATCH] preprocessor: Reinitialize frontend parser after loading a PCH [PR112319]

On Thu, Nov 30, 2023 at 4:19 PM Marek Polacek wrote: > > On Wed, Nov 01, 2023 at 05:54:57PM -0400, Lewis Hyatt wrote: > > Hello- > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112319 > > > > This is a one-line patch to fix the GCC 14 regression noted in the > > PR. Bootstrap + regtest all la

[PATCH] RISC-V: Vectorized str(n)cmp and strlen.

Hi, this adds vectorized implementations of strcmp and strncmp as well as strlen. strlen falls back to the previously implemented rawmemchr. Also, it fixes a rawmemchr bug causing a SPEC2017 execution failure: We would only ever increment the source address by 1 regardless of the input type. The

[PATCH] btf: fix PR debug/112656

PR debug/112656 - btf: function prototypes generated with name With this patch, all BTF_KIND_FUNC_PROTO will appear anonymous in the generated BTF section. As noted in the discussion in the bugzilla, the number of BTF_KIND_FUNC_PROTO types output varies across targets (BPF with -mco-re vs non-BPF

Re: [PATCH v5] c++: implement P2564, consteval needs to propagate up [PR107687]

On 11/23/23 11:46, Marek Polacek wrote: v5 greatly simplifies the code. Indeed, it's much cleaner now. I still need a new ff_ flag to signal that we can return immediately after seeing an i-e expr. That's still not clear to me: + /* In turn, maybe promote the function we find ourselv

Re: [PATCH] htdocs/git.html: correct spelling and use git in example

On Thu, 30 Nov 2023, Jonny Grant wrote: > ChangeLog: > > htdocs/git.html: change example to use git:// and correct > spelling repostiory -> repository . git:// (unencrypted / unauthenticated) is pretty widely considered obsolescent, I'm not sure adding a use of it (a

Re: [PATCH] RISC-V: Vectorized str(n)cmp and strlen.

On 11/30/23 15:22, Robin Dapp wrote: Hi, this adds vectorized implementations of strcmp and strncmp as well as strlen. strlen falls back to the previously implemented rawmemchr. Also, it fixes a rawmemchr bug causing a SPEC2017 execution failure: We would only ever increment the source addre

[PATCH] RISC-V: Fix VSETVL PASS regression

This patch fix 2 regression (one is bug regression, the other is performance regression). Those 2 regressions are both we are comparing ratio for same AVL in wrong place. 1. BUG regression: avl_single-84.c: f0: li a5,999424 add a1,a1,a5 li a4,299008

Re: [PATCH] RISC-V: Vectorized str(n)cmp and strlen.

Hi, Robin. Thanks for working on this. I know this is a tedious work. A couple comments here: - if (TARGET_ZBB || TARGET_XTHEADBB) + if (TARGET_VECTOR && stringop_strategy & STRINGOP_STRATEGY_VECTOR) +{ + bool ok = riscv_vector::expand_strcmp (result, src1, src2, bytes_rtx, +

Re: [PATCH] RISC-V: Vectorized str(n)cmp and strlen.

Ah. I see: --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2336,9 +2336,7 @@ (define_expand "cpymem" (use (match_operand:SI 3 "const_int_operand"))])] "" { - if (riscv_vector::expand_block_move (operands[0], operands[1], operands[2])) -DONE; - else if (

Re: [RFA] New pass for sign/zero extension elimination

> Date: Sun, 19 Nov 2023 17:47:56 -0700 > From: Jeff Law > Locally we have had this enabled at -O1 and above to encourage testing, > but I'm thinking that for the trunk enabling at -O2 and above is the > right thing to do. Yes. > Thoughts, comments, recommendations? Sounds great! It'd be ni

Re: [V2] New pass for sign/zero extension elimination -- not ready for "final" review

On Thu, 2023-11-30 at 08:44 -0700, Jeff Law wrote: > > > On 11/29/23 02:33, Xi Ruoyao wrote: > > On Mon, 2023-11-27 at 23:06 -0700, Jeff Law wrote: > > > This has (of course) been tested on rv64.  It's also been bootstrapped > > > and regression tested on x86.  Bootstrap and regression tested (C

[RFC] i386: Remove Xeon Phi ISA support

Hi all, Since Knight Landing and Knight Mill microarchitectures were EOL in 2019 and previously ICC and ICX has removed the support and emitted errors, we would also like to remove the support in GCC to reduce maintainence effort. The deprecated Xeon Phi ISAs are AVX512PF, AVX512ER, AVX5124VNNIW,

[PATCH] i386: Mark Xeon Phi ISAs as deprecated

Since Knight Landing and Knight Mill microarchitectures are EOL, we would like to remove its support in GCC 15. In GCC 14, we will first emit a warning for the usage. gcc/ChangeLog: * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append "-mno-" for Xeon Phi ISAs.

Re: [PATCH] testsuite: scev: expect fail on ilp32

> From: Hans-Peter Nilsson > Date: Thu, 30 Nov 2023 18:09:10 +0100 > I intend to post two alternative patches to get this > resolved: > 1: Move the tests to gcc.target/i386/scev-[3-5].c > 2: gcc.dg/tree-ssa/scev-[3-5].c skipped for arm*, xfailed >only on h8300-*-* and ia32. Correction: h8300

[PATCH] Take register pressure into account for vec_construct/scalar_to_vec when the components are not loaded from memory.

> Hmm, I would suggest you put reg_needed into the class and accumulate > over all vec_construct, with your patch you pessimize a single v32qi > over two separate v16qi for example. Also currently the whole block is > gated with INTEGRAL_TYPE_P but register pressure would be also > a concern for f

[patch-2, rs6000] guard fctid on PPC64 and powerpc 476 [PR112707]

Hi, The "fctid" is supported on 64-bit Power processors and powerpc 476. It need a guard to check it. The patch fixes the issue. Bootstrapped and tested on x86 and powerpc64-linux BE and LE with no regressions. Is this OK for trunk? Thanks Gui Haochen ChangeLog rs6000: guard fctid on PPC64 a

[patch-1, rs6000] enable fctiw on old archs [PR112707]

Hi, SImode in float register is supported on P7 above. It causes "fctiw" can be generated on old 32-bit processors as the output operand of fctiw insn is a SImode in float/double register. This patch fixes the problem by adding an expand and an insn pattern for fctiw. The output of new pattern is

Re: [PATCH] RISC-V: Fix VSETVL PASS regression

All regressions (zve64d/zvl128b/zvl256b/zvl512b/zvl1024b) passed. juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-12-01 08:51 To: gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong Subject: [PATCH] RISC-V: Fix VSETVL PASS regression This patch fix 2 regression (one is

Re: [PATCH] testsuite: scev: expect fail on ilp32

> From: Hans-Peter Nilsson > Date: Thu, 30 Nov 2023 18:09:10 +0100 Richard B.: > > > In the end we might need to move/duplicate the test to some > > > gcc.target/* dir and restrict it to a specific tuning. > > I intend to post two alternative patches to get this > resolved: > 1: Move the tes

Re: [PATCH] testsuite: scev: expect fail on ilp32

> From: Hans-Peter Nilsson > Date: Thu, 30 Nov 2023 18:09:10 +0100 > I intend to post two alternative patches to get this > resolved: > 2: gcc.dg/tree-ssa/scev-[3-5].c skipped for arm*, xfailed >only on h8300-*-* and ia32. (Except as mentioned, the XPASS issue does not apply to h8300; it's

[PATCH] c++: lambda capture and explicit object parm

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- More adjustments to allow for explicit object parameters in lambdas. This has no practical effect until that patch goes in, but applying this separately seems reasonable. gcc/cp/ChangeLog: * semantics.cc (finish_non_static_data_me

Ping: [PATCH v2] Only allow (int)trunc(x) to (int)x simplification with -ffp-int-builtin-inexact [PR107723]

Ping. On Fri, 2023-11-24 at 17:09 +0800, Xi Ruoyao wrote: > With -fno-fp-int-builtin-inexact, trunc is not allowed to raise > FE_INEXACT and it should produce an integral result (if the input is not > NaN or Inf).  Thus FE_INEXACT should not be raised. > > But (int)x may raise FE_INEXACT when x i

Re: [PATCH v6 1/1] c++: Initial support for P0847R7 (Deducing This) [PR102609]

I ran into another issue while devising tests for redeclarations of xobj member functions as static member functions and vice versa. I am pretty sure by the literal wording of the standard, this is well formed. template concept Constrain = true; struct S { void f(this auto, Constrain auto) {};

Re: [PATCH] s390: Fix builtin-classify-type-1.c on s390 too [PR112725]

On 11/30/23 17:34, Jakub Jelinek wrote: > On Wed, Nov 29, 2023 at 07:27:20PM +0100, Jakub Jelinek wrote: >> Given that the s390 backend defines pretty much the same target hook >> as rs6000, I believe it suffers (at least when using -mvx?) the same >> problem as rs6000, though admittedly this is so

Re: [PATCH] gcov: Fix __LIBGCC_HAVE_LIBATOMIC definition

On Thu, Nov 30, 2023 at 5:21 PM Sebastian Huber wrote: > > In libgcov we use defined (__LIBGCC_HAVE_LIBATOMIC), so we must define it only > if needed (vs. #if __LIBGCC_HAVE_LIBATOMIC). For consistency wouldn't it be better to change the user side in libgcc? > gcc/c-family/ChangeLog: > >

[PATCH] RISC-V: Support highpart register overlap for widen vx/vf instructions

This patch leverages the same approach as vwcvt. Before this patch: .L5: add a3,s0,s1 add a4,s6,s1 add a5,s7,s1 vsetvli zero,s0,e32,m4,ta,ma vle32.v v16,0(s1) vle32.v v12,0(a3) mv s1,s2 vle32.v v8,0(a4) vle32

Re: [PATCH] i386: Mark Xeon Phi ISAs as deprecated

On Fri, Dec 1, 2023 at 3:22 AM Haochen Jiang wrote: > > Since Knight Landing and Knight Mill microarchitectures are EOL, we > would like to remove its support in GCC 15. In GCC 14, we will first > emit a warning for the usage. I think it's better to keep supporting -mtune/arch=knl without diagnos

Re: [PATCH] testsuite: scev: expect fail on ilp32

On Fri, 1 Dec 2023, Hans-Peter Nilsson wrote: > > From: Hans-Peter Nilsson > > Date: Thu, 30 Nov 2023 18:09:10 +0100 > > Richard B.: > > > > In the end we might need to move/duplicate the test to some > > > > gcc.target/* dir and restrict it to a specific tuning. > > > > I intend to post tw

Re: Ping: [PATCH] Allow target attributes in non-gnu namespaces

On Thu, Nov 30, 2023 at 3:12 PM Richard Sandiford wrote: > > Ping OK. Thanks, Richard. > Richard Sandiford writes: > > This is a ping+rebase of the patch below. I've also optimised the > > handling of ignored attributes so that we don't register empty tables. > > There was also a typo in the

Re: [PATCH v2] doc: Update the status of build directory not fully separated

On Thu, Nov 30, 2023 at 2:42 PM Xi Ruoyao wrote: > > Recently there are some people building GCC with srcdir == objdir and > the attempts just failed [1]. So stop to say "it should work". OTOH > objdir as a subdirectory of srcdir works: we've built GCC in LFS [2] > and BLFS [3] this way for deca

Re: [PATCH] s390x: Fix PR112753

On 11/30/23 16:45, Juergen Christ wrote: > Commit 466b100e5fee808d77598e0f294654deec281150 introduced a bug in > s390_md_asm_adjust if vector extensions are not available. Fix the control > flow of this function to not adjust long double values. > > gcc/ChangeLog: > > * config/s390/s390.cc

[PATCH] lower-bitint: Fix _BitInt .{ADD,SUB}_OVERFLOW lowering [PR112750]

Hi! The .{ADD,SUB}_OVERFLOW lowering is implemented by performing normal addition/subtraction (perhaps extended to even more bits than normally by continuing with extended values of operands after running of normal bits) and in addition to that trying to compute if certain sets of bits are either

RE: [PATCH] i386: Mark Xeon Phi ISAs as deprecated

> -Original Message- > From: Richard Biener > Sent: Friday, December 1, 2023 3:04 PM > To: Jiang, Haochen > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; > ubiz...@gmail.com > Subject: Re: [PATCH] i386: Mark Xeon Phi ISAs as deprecated > > On Fri, Dec 1, 2023 at 3:22 AM Haochen Jiang > wr

[PATCH] lower-bitint: Fix ICE on bitint-39.c

Hi! torture/bitint-39.c ICEs with -O1; the problem is that the finish_arith_overflow code in one spot replaces use_stmt with an assignment or cast, but if unlucky and m_gsi iterator is the same statement, when the code later tree clobber = build_clobber (TREE_TYPE (var), CLOBBER_EOL);

[PATCH v2 1/3] LoongArch: Adjust D version strings.

gcc/ChangeLog: * config/loongarch/loongarch-d.cc: Undefine LoongArch32. Define LoongArch_SF, LoongArch_F32, LoongArch_F64 gcc/d/ChangeLog: * dmd/cond.d: Same. * implement-d.texi: Same. --- gcc/config/loongarch/loongarch-d.cc | 27 ++- gcc/

[PATCH v2 3/3] libphobos: LoongArch hardware support.

libphobos/ChangeLog: * src/std/math/hardware.d: Implement FP control. * libdruntime/config/loongarch/switchcontext.S: New file. --- .../config/loongarch/switchcontext.S | 133 ++ libphobos/src/std/math/hardware.d | 53 +++ 2 files changed,

[PATCH v2 0/3] LoongArch D support

This patchset is based on Zixing Liu's initial support patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631260.html Update v1 -> v2: Rebased onto the dmd/druntime upstream state. Regtested on loongarch64-linux-gnu with the following result: === libphobos Summary ==

[PATCH v2 2/3] libphobos: Update build scripts for LoongArch64.

libphobos/ChangeLog: * m4/druntime/cpu.m4: Support loongarch* targets. * libdruntime/Makefile.am: Same. * libdruntime/Makefile.in: Regenerate. * configure: Regenerate. --- libphobos/configure | 21 ++- libphobos/libdruntime/Makefile.am | 3 + lib

[PATCH v2] RISC-V: Bugfix for legitimize move when get vec mode in zve32f

From: Pan Li If we want to extract 64bit value but ELEN < 64, we use RVV vector mode with EEW = 32 to extract the highpart and lowpart. However, this approach doesn't honor DFmode when movdf pattern when ZVE32f and of course results in ICE when zve32f. This patch would like to reuse the approach

Re: [PATCH] lower-bitint: Fix _BitInt .{ADD,SUB}_OVERFLOW lowering [PR112750]

On Fri, 1 Dec 2023, Jakub Jelinek wrote: > Hi! > > The .{ADD,SUB}_OVERFLOW lowering is implemented by performing normal > addition/subtraction (perhaps extended to even more bits than normally by > continuing with extended values of operands after running of normal bits) > and in addition to that

Re: [PATCH] lower-bitint: Fix ICE on bitint-39.c

On Fri, 1 Dec 2023, Jakub Jelinek wrote: > Hi! > > torture/bitint-39.c ICEs with -O1; the problem is that the > finish_arith_overflow code in one spot replaces use_stmt with an > assignment or cast, but if unlucky and m_gsi iterator is the same statement, > when the code later > tree clobbe

[PATCH] lower-bitint: Fix up maximum addition/subtraction/multiplication result computations

Hi! When debugging PR112750, I've noticed some issues in the computation of precisions and the following patch attempts to fix those. The pass uses range_to_prec function, which possibly using ranger returns minimum precision of some operand in the style that libgcc _BitInt entrypoints expect, i.

RE: RE: [PATCH v1] RISC-V: Bugfix for legitimize move when get vec mode in zve32f

Got it, will have a try for the suggestion. Pan From: juzhe.zh...@rivai.ai Sent: Thursday, November 30, 2023 3:54 PM To: Li, Pan2 ; gcc-patches Cc: Wang, Yanzhang ; kito.cheng Subject: Re: RE: [PATCH v1] RISC-V: Bugfix for legitimize move when get vec mode in zve32f I see. Is it possible to

Re: [PATCH] combine: Fix ICE in try_combine on pr112494.c [PR112560]

Hi! On Wed, Nov 29, 2023 at 02:20:03PM +0100, Uros Bizjak wrote: > On Wed, Nov 29, 2023 at 1:25 PM Richard Biener > wrote: > > On Wed, Nov 29, 2023 at 10:35 AM Uros Bizjak wrote: > I was assuming that if the CC reg is not used inside the comparison, > then the mode of CC reg is irrelevant. We ca

Re: [PATCH] Fortran: fix TARGET attribute of associating entity in ASSOCIATE [PR112764]

Hi Harald, The original testcase is accepted by the two other brands to which I have access. OK for mainline and, I would suggest, 13-branch. Thanks Paul On Wed, 29 Nov 2023 at 21:16, Harald Anlauf wrote: > Dear all, > > the attached simple patch fixes the handling of the TARGET > attribute

[PATCH] aarch64: modify Ampere CPU tunings on reassociation/FMA

This patch modifies tunings for ampere1/ampere1a/ampere1b, to: 1. Allow reassociation on FP additions. 2. Avoid generating loop-dependant FMA chains. Added a tuning option for this. Bootstrapped and tested. Is this ok for trunk? Thanks, Di Zhao gcc/ChangeLog: * config/aarch64/aarch64-t

Re: [PATCH] Set AVOID_256FMA_CHAINS TO m_GENERIC as it's generally good to new platforms

Any comments? On Wed, Nov 22, 2023 at 12:17 PM liuhongt wrote: > > From: "Zhang, Annita" > > Avoid_fma_chain was enabled in m_SAPPHIRERAPIDS, m_ALDERLAKE and > m_CORE_HYBRID. It can also be enabled in m_GENERIC to improve the > performance of -march=x86-64-v3/v4 with -mtune=generic set by > defa

Re: [PATCH] testsuite: scev: expect fail on ilp32

On Thu, 30 Nov 2023, Alexandre Oliva wrote: > On Nov 29, 2023, Hans-Peter Nilsson wrote: > > >> XPASS: gcc.dg/tree-ssa/scev-3.c scan-tree-dump-times ivopts "&a" 1 > >> XPASS: gcc.dg/tree-ssa/scev-4.c scan-tree-dump-times ivopts "&a" 1 > >> XPASS: gcc.dg/tree-ssa/scev-5.c scan-tree-dump-times ivo

Re: [PATCH] combine: Fix ICE in try_combine on pr112494.c [PR112560]

On Thu, Nov 30, 2023 at 9:21 AM Segher Boessenkool wrote: > > Hi! > > On Wed, Nov 29, 2023 at 02:20:03PM +0100, Uros Bizjak wrote: > > On Wed, Nov 29, 2023 at 1:25 PM Richard Biener > > wrote: > > > On Wed, Nov 29, 2023 at 10:35 AM Uros Bizjak wrote: > > I was assuming that if the CC reg is not

[PATCH] libgo, libstdc++: Regenerate GCC_CHECK_ASSEMBLER_HWCAP users

After Author: Rainer Orth Date: Thu Nov 30 10:06:23 2023 +0100 libiberty: Disable hwcaps for sha1.o the gcc-autoregen bot correctly complained that the libgo and libstdc++ configure scripts hadn't been regenerated. I'd have commited the following as obvious (just whitespace change), but

[PATCH] doc: Update the status of build directory not fully separated

Recently there are some people building GCC with srcdir == objdir and the attempts just failed [1]. So stop to say "it should work". OTOH objdir as a subdirectory of srcdir works (at least for LFS [2] and BLFS [3]). [1]: https://gcc.gnu.org/pipermail/gcc-help/2023-November/143068.html [2]: https

Re: [PATCH] Add support for function attributes and variable attributes

Ping David. :) Le jeu. 23 nov. 2023 à 22:59, Antoni Boucher a écrit : > David: I found back the comment you made. Here it is: > >I see you have patches to add function and variable attributes; I >wonder if this would be cleaner internally if there was a >recording::attribute class, r

[PATCH] testsuite/arm: Fix bfloat16_vector_typecheck_[12].c tests

After commit r14-5617-gb8592186611, int32x[24]_t types now use elements of 'long int' type instead of 'int' on arm-eabi (it's still 'int' on arm-linux-gnueabihf). Both are 32-bit types anyway. This patch adjust the two tests so that they optionnally accept 'long ' before 'int' in the expected err

[COMMITTED] ada: Constant_Indexing used when context requires a variable

From: Steve Baird In the case of a call with a formal parameter of mode other than "IN" where the corresponding actual parameter is a generalized indexing and the indexable container has both Constant_Indexing and Variable_Indexing aspects specified, the generalized indexing must be interpreted a

[COMMITTED] ada: Fix wrong finalization for qualified aggregate of limited type in allocator

From: Eric Botcazou This happens with -gnata when the limited type has controlled components and a predicate, because the predicate check generated for the aggregate causes the creation of a temporary that is used as the expression of the allocator. Now this combination is illegal for a limited

[COMMITTED] ada: Fix predicate check failure in Expand_Allocator_Expression

From: Eric Botcazou The For_Special_Return_Object flag needs to be accessed on entry of the procedure in case the allocator is rewritten during the processing. gcc/ada/ * exp_ch4.adb (Expand_Allocator_Expression): Add Special_Return boolean constant to hold the value of For_Spec

[COMMITTED] ada: Add comment describing Partition_Elaboration_Policy dependency.

From: Steve Baird Add a comment in the spec for the default (as opposed to hie) version of Ada.Real_Time.Timing_Events indicating that it is incompatible with a a Partition_Elaboration_Policy specification specifying a policy other than Concurrent. gcc/ada/ * libgnarl/a-rttiev.ads: add

[COMMITTED] ada: Too-strict conformance checking for formal discriminated type

From: Steve Baird The discriminant subtype conformance check for an actual parameter corresponding to a generic formal discriminated type was too strict and could incorrectly reject legal instantiations. gcc/ada/ * sem_ch12.adb (Validate_Discriminated_Formal_Type): Replace Entit

[COMMITTED] ada: Crash initializing component of private record type

From: Javier Miranda The compiler may crash processing the full type declaration of a private record type that initializes a component with a call to a function instantiated in the private part of the package. gcc/ada/ * freeze.adb (Declared_In_Expanded_Body): New subprogram. (I

[COMMITTED] ada: Name resolution in expanded instances

From: Steve Baird In building the tree for an instance of a generic, expansion sets entity fields on names that refer to things declared outside of the instance, but leaves the entity field unset on names that should end up referring to things declared within the instance. These will instead be s

[COMMITTED] ada: Remove GNATcheck violations

From: Sheri Bernstein Remove GNATcheck violations by refactoring code and also using pragma Annotate to exempt them. gcc/ada/ * libgnat/i-cstrin.adb (Free): Rewrite code so there is only one return, to remove Improper_Returns violation. (Position_Of_Nul): Add pragma to e

[COMMITTED] ada: Fix spelling of functions with(out) "side effects"

From: Yannick Moy Correct spelling does not include an hyphen. Fix comments and one error message. Also fix other mispellings of "side-effect" or "side effect" depending on the case (adjective should have hyphen), and "side-effect-free" with double hyphen as an adjective. gcc/ada/ * ch

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