I confirm it does. I realized it when finalizing our patch for
attributes support.
Le jeu. 9 nov. 2023 à 21:49, David Malcolm a écrit :
>
> On Thu, 2023-11-09 at 21:03 +0100, Guillaume Gomez wrote:
> > Hi,
> >
> > This patch adds the `get_restrict` method declaration for
> > the C++ interface as
On Thu, 2023-11-09 at 21:51 +0100, Guillaume Gomez wrote:
> I confirm it does. I realized it when finalizing our patch for
> attributes support.
Excellent; thanks for the fix.
Dave
Bootstrapped and regtested on x86_64-pc-linux-gnu.
-- >8 --
A TEMPLATE_DECL does not have module attachment flags associated with
it, so this patch extracts the result from the template to read the
flags from there instead.
As a drive-by fix we also group the error with its informative note.
MAINTAINERS: Add myself to write after approval
Signed-off-by: Jeff Law
ChangeLog:
* MAINTAINERS: Add myself.
diff --git a/MAINTAINERS b/MAINTAINERS
index 30cb530a3b1..c43167d9a75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -445,6 +445,7 @@ Wei Guozhi
Hello-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111918
This patch fixes the behavior of `#pragma GCC diagnostic pop' for permissive
error diagnostics such as -Wnarrowing (in C++11). Those currently do not
return to the correct state after the last pop; they become effectively
simple warnings
On Nov 8, 2023, at 7:55 AM, Alexandre Oliva wrote:
>
> gcc.target/i386/pr95126-m32-[34].c expect push instructions that are
> only present with -mno-accumulate-outgoing-args, so make that option
> explicit rather than dependent on tuning.
>
> Regstrapped on x86_64-linux-gnu, also tested with gcc
On Nov 8, 2023, at 8:29 AM, Alexandre Oliva wrote:
>
> On Nov 5, 2023, Mike Stump wrote:
>
>> that, otherwise, I'll approve this version.
>
> FWIW, this version is not usable as is. Something went wrong in my
> testing, and several regressions only visible in hosted mode made to the
> versio
On Thu, 9 Nov 2023, Jakub Jelinek wrote:
> The main reason to add these is to support arbitrary unsigned (for
> clrsb/ffs signed) bit-precise integer types and also __int128 which
> wasn't supported by the existing builtins, so that e.g.
> type-generic functions could then support not just bit-pr
On Nov 8, 2023, at 5:49 PM, Alexandre Oliva wrote:
>
> LTS GNU/Linux distros from 2018, still in use, don't have
> pthread_cond_clockwait. There's no trivial way to detect it so as to
> make the test conditional, but there's an easy enough way to silence
> the fail due to lack of the function in
On 11/5/23 10:06, waffl3x wrote:
Bootstrapped and tested on x86_64-linux with no regressions.
I originally threw this e-mail together last night, but threw in the
towel when I thought I saw tests failing and went to sleep. I did a
proper bootstrap and comparison and whatnot and found that there
Yes, those tests that triggered the ICE now pass.
Maxim
On Thu, 9 Nov 2023 at 16:26, Jeff Law wrote:
>
>
> On 11/6/23 06:01, Maxim Blinov wrote:
> > From: Maxim Blinov
> >
> > This patch is based on and intended for the
> vendors/riscv/gcc-13-with-riscv-opts branch - please apply if looks OK.
I'm going to be traveling for the next two weeks (Plumbers and then
Thanksgiving), so I won't be at the patchwork syncs.
Hi.
This patch adds support for getting the CPU features in libgccjit (bug
112466)
There's a TODO in the test:
I'm not sure how to test that gcc_jit_target_info_arch returns the
correct value since it is dependant on the CPU.
Any idea on how to improve this?
Also, I created a CStringHash to be ab
Reduce implicit usage of line_table global, and move source printing to
within diagnostic_context.
No functional change intended.
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-5300-g8625aa24669669.
gcc/ChangeLog:
* diagnostic-show-locus.cc (layout:
On 11/9/23 04:55, Nathaniel Shead wrote:
I'm not sure if this is just papering over a general issue of clones not being
exported/imported, or if this is just an exception to the general case of
clones being able to be freely regenerated with no other issues.
Alternatively, would it be better to
On 11/9/23 16:06, Nathaniel Shead wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu.
-- >8 --
A TEMPLATE_DECL does not have module attachment flags associated with
it, so this patch extracts the result from the template to read the
flags from there instead.
oh yeah. my original plan
Hi,
I added the BPF related issue and the solution in the section Appendix 4 Known
issues.
No change to other parts.
Send this V3 for record purpose.
Qing
Represent the missing dependence for the "counted_by" attribute and its
con
On Thu, 2023-11-09 at 17:27 -0500, Antoni Boucher wrote:
> Hi.
> This patch adds support for getting the CPU features in libgccjit
> (bug
> 112466)
>
> There's a TODO in the test:
> I'm not sure how to test that gcc_jit_target_info_arch returns the
> correct value since it is dependant on the CPU.
On Thu, 9 Nov 2023 at 19:32, Arsen Arsenović wrote:
>
> This allows us to add features to freestanding which allow specifying
> non-default allocators (generators, collections, ...) without having to
> modify them.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/memoryfwd.h: Remove HOSTED c
Jonathan Wakely writes:
> OK
Thanks, pushed (tests did pass).
Have a lovely night.
--
Arsen Arsenović
signature.asc
Description: PGP signature
On Thu, Nov 09, 2023 at 05:57:39PM -0500, Nathan Sidwell wrote:
> On 11/9/23 04:55, Nathaniel Shead wrote:
> > I'm not sure if this is just papering over a general issue of clones not
> > being
> > exported/imported, or if this is just an exception to the general case of
> > clones being able to b
Since cond_copysign has been support into match.pd (middle-end).
We don't need to support conditional copysign by RTL combine pass.
Instead, we can support it by direct explicit cond_copysign optab.
conditional copysign tests are already available in the testsuite.
No need to add tests.
gcc/Chan
On 11/5/23 10:06, waffl3x wrote:
I had wanted to write about some of my frustrations with trying to
write a test for virtual specifiers and errors/warnings for
shadowing/overloading virtual functions, but I am a bit too tired at
the moment and I don't want to delay getting this up for another nig
On 11/9/23 18:29, Nathaniel Shead wrote:
On Thu, Nov 09, 2023 at 05:57:39PM -0500, Nathan Sidwell wrote:
On 11/9/23 04:55, Nathaniel Shead wrote:
I'm not sure if this is just papering over a general issue of clones not being
exported/imported, or if this is just an exception to the general case
gcc/testsuite/ChangeLog:
* gcc.target/bpf/ldxdw.c: Fix regexp with expected result.
---
gcc/testsuite/gcc.target/bpf/ldxdw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/bpf/ldxdw.c
b/gcc/testsuite/gcc.target/bpf/ldxdw.c
index 0985ea3e6ac..
On 11/9/23 16:33, Juzhe-Zhong wrote:
Since cond_copysign has been support into match.pd (middle-end).
We don't need to support conditional copysign by RTL combine pass.
Instead, we can support it by direct explicit cond_copysign optab.
conditional copysign tests are already available in the
On 11/9/23 15:43, 钟居哲 wrote:
Hi. Robin.
[ ... ]
You may need a development version of binutils to get the zfh/zvfh
support and unreleased patches to get zfb/zvfb support.
Probably the easiest thing to do would be to look in the gcc.log file at
those failures and see what the excess failur
On 11/9/23 14:58, Marek Polacek wrote:
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
-- >8 --
Here we are wrongly parsing
int y(auto(42));
which uses the C++23 cast-to-prvalue feature, and initializes y to 42.
However, we were treating the auto as an implicit template paramet
This patch fixes the pseudo-c BPF assembly syntax used for
*mulsidi3_zeroextend, which was being emitted as:
rN *= wM
instead of the proper way to denote a mul32 in pseudo-C syntax:
wN *= wM
Includes test.
Tested in bpf-unknown-none-gcc target in x86_64-linux-gnu host.
gcc/ChangeLog:
On 11/8/23 16:59, Patrick Palka wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?
-- >8 --
Here when building up the non-dependent .* expression, we crash from
fold_convert on 'b.a' due to this (templated) COMPONENT_REF having an
IDENTIFIER_NODE instead of F
On 11/7/23 14:52, Patrick Palka wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look
OK for trunk?
-- >8 --
The capture decltype handling in finish_decltype_type wasn't looking
through implicit INDIRECT_REF (added by convert_from_reference), which
caused us to incorrectly re
Hi.
See answers below.
On Thu, 2023-11-09 at 18:04 -0500, David Malcolm wrote:
> On Thu, 2023-11-09 at 17:27 -0500, Antoni Boucher wrote:
> > Hi.
> > This patch adds support for getting the CPU features in libgccjit
> > (bug
> > 112466)
> >
> > There's a TODO in the test:
> > I'm not sure how to
On 11/7/23 14:52, Patrick Palka wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?
OK.
-- >8 --
We usually don't see capture proxies in finish_decltype_type because
process_outer_var_ref is a no-op inside an unevaluated context and
so a use of a capture in
On 11/7/23 10:08, Patrick Palka wrote:
bootstrapped and regtested on x86_64-pc-linxu-gnu, does this look OK for trunk?
-- >8 --
In the COMPOUND_EXPR case of tsubst_expr, we were redundantly clearing
the tf_decltype flag when substituting the LHS and also neglecting to
propagate it when substitu
When zero extracting a single bit bitfield from bits 16..31 on the H8 we
currently generate some pretty bad code.
The fundamental issue is we can't shift efficiently and there's no
trivial way to extract a single bit out of the high half word of an
SImode value.
What usually happens is we us
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, November 9, 2023 11:12 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH v1] Internal-fn: Add FLOATN support for l/ll roun
Yes. No regression. Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 07:56
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Move cond_copysign from combine pattern to autovec
pattern
On 11/9/23 16:33, Juzhe-Zhong wrote:
> Since
On 11/8/23 04:09, Mary Bennett wrote:
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
Bikeshedding alert... Usually we keep constraint names pretty small. It
helps when you've got patterns that may have many constraints.
I am already using master branch.
The FAIL is:
xgcc: fatal error: Cannot find suitable multilib set for
'-march=rv64imafdcv_zicsr_zifencei_zfhmin_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvl128b_zvl32b_zvl64b'/'-mabi=lp64d'
I will update binutils again today to see whether it can fix the issue.
On 11/9/23 18:09, juzhe.zh...@rivai.ai wrote:
I am already using master branch.
The FAIL is:
xgcc: fatal error: Cannot find suitable multilib set for
'-march=rv64imafdcv_zicsr_zifencei_zfhmin_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvl128b_zvl32b_zvl64b'/'-mabi=lp64d'
That's an multilib conf
How to fix it ? I am pretty noob on testing CI.
Can Robin fix that?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:11
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.
On 11/9/23 18:09, juzhe.zh...@rivai.ai
On 11/9/23 18:12, juzhe.zh...@rivai.ai wrote:
How to fix it ? I am pretty noob on testing CI.
Can Robin fix that?
It's most likely a problem on your side with how you've configured the
toolchain. I don't think this is somethign Robin can fix for you.
jeff
On 11/5/23 11:50, Richard Sandiford wrote:
This patch adds a way for targets to ask that selected mode changes
be brought forward, through a combination of:
(1) requiring a mode in blocks where the entity was previously
transparent
(2) pushing the transition at the head of a block onto
I am using --with-arch=rv32gcv --with-abi=ilp32d
I change dg-additional-option into dg-option of all those tests.
Issues gone.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:15
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V/testsuit
On 11/2/23 17:45, Patrick O'Neill wrote:
Testcases in g++.dg/vect rely on check_vect_support_and_set_flags
to set dg-do-what-default and avoid running vector tests on non-vector
targets. The three testcases in this patch overwrite the default with
dg-do run.
Removing the dg-do run directive r
On 11/7/23 08:18, Juzhe-Zhong wrote:
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97428.c: Add additional compile option for riscv.
I don't guess we know if other targets would benefit from this option.
The only reference in gcc-testresults to pr97428.c is an armv7 run from
2022. So le
Thanks Jeff. Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:26
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH V3] test: Fix FAIL of pr97428.c for RVV
On 11/7/23 08:18, Juzhe-Zhong wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/pr97428.c: Add additi
On Thu, 9 Nov 2023, Jeff Law wrote:
> > Can we have the insn costing reverted to correct calculation?
> What needs to happen is that code needs to be extended, not reverted. Many
> codes have to be synthesized based on the condition and the true/false arms.
> That's not currently accounted for.
On 11/3/23 00:18, Patrick O'Neill wrote:
On non-vector targets dejagnu attempts dg-do compile for pr95401.cc.
This produces a command like this:
g++ pr95401.cc pr95401a.cc -S -o pr95401.s
which isn't valid (gcc does not accept multiple input files when using
-S with -o).
This patch adds requ
On 11/6/23 05:23, Richard Sandiford wrote:
Later patches add more calls to get_attribute_namespace.
For scoped attributes, this is a simple operation on tree pointers.
But for normal GNU attributes (the vast majority), it involves a
call to get_identifier ("gnu"). This patch caches the identi
Hi all,
This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
support, it makes a lot easier to add them comparing to the August version.
Detail for AVX10 is shown below:
Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
It describes the Intel Advan
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Add avx10_set and version and detect avx10.1.
(cpu_indicator_init): Handle avx10.1-512.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_256_SET): New.
(OPTION_MASK_
When I'm working on PR112443, I notice there's some misoptimizations: after we
fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend fails to combine it
back to v{,p}blendv{v,ps,pd} since the pattern is too complicated, so I think
maybe we should hanlde it in the gimple level.
The dump is like
Hi Maxim and Alexander,
Thanks a lot for the review comments!
on 2023/11/10 01:40, Alexander Monakov wrote:
>
> On Thu, 9 Nov 2023, Maxim Kuvyrkov wrote:
>
>> Hi Kewen,
>>
>> Below are my comments. I don't want to override Alexander's review, and if
>> the patch looks good to him, it's fine to
Hi,
on 2023/11/9 09:31, HAO CHEN GUI wrote:
> Hi,
> This patch enables vector mode for by pieces equality compare. It
> adds a new expand pattern - cbrnachv16qi4 and set MOVE_MAX_PIECES
> and COMPARE_MAX_PIECES to 16 bytes when P8 vector enabled. The compare
> relies both move and compare instru
On Thu, Nov 9, 2023 at 5:52 PM liuhongt wrote:
>
> When I'm working on PR112443, I notice there's some misoptimizations: after we
> fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend fails to combine it
> back to v{,p}blendv{v,ps,pd} since the pattern is too complicated, so I think
> maybe
On Fri, Nov 10, 2023 at 10:11 AM Andrew Pinski wrote:
>
> On Thu, Nov 9, 2023 at 5:52 PM liuhongt wrote:
> >
> > When I'm working on PR112443, I notice there's some misoptimizations: after
> > we
> > fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend fails to combine
> > it
> > back to v
Although current GCC didn't cause ICE when I create FP16 vec_init case
with -march=rv64gcv (no ZVFH), current vec_init pattern looks wrong.
Since V_VLS FP16 predicate is TARGET_VECTOR_ELEN_FP_16, wheras vec_init
needs vfslide1down/vfslide1up.
It makes more sense to robustify the vec_init patterns
This patch is a small optimization for vector initialization.
Discovered when I am evaluating benchmarks.
Consider this following case:
void foo3 (int8_t *out, int8_t x, int8_t y)
{
v16qi v = {y, y, y, y, y, y, y, x, x, x, x, x, x, x, x, x};
*(v16qi*)out = v;
}
Before this patch:
vse
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
* config/i386/i386-expand.cc
(ix86_expand_vector_init_duplicate): Handle V4HF/V4BF and
V2HF/V2BF.
(ix86_expand_vector_init_one_nonzero): Ditto.
(ix86_expand_vector
On 11/9/23 10:40, Alexander Monakov wrote:
On Thu, 9 Nov 2023, Maxim Kuvyrkov wrote:
Hi Kewen,
Below are my comments. I don't want to override Alexander's review, and if
the patch looks good to him, it's fine to ignore my concerns.
My main concern is that this adds a new entity -- forcef
On 11/9/23 18:57, Kewen.Lin wrote:
Hi Maxim and Alexander,
Thanks a lot for the review comments!
on 2023/11/10 01:40, Alexander Monakov wrote:
On Thu, 9 Nov 2023, Maxim Kuvyrkov wrote:
Hi Kewen,
Below are my comments. I don't want to override Alexander's review, and if
the patch looks
On 10/4/23 12:28, Brendan Shanks wrote:
Hi,
This patch implements pex_unix_exec_child using posix_spawn when
available.
This should especially benefit recent macOS (where vfork just calls
fork), but should have equivalent or faster performance on all
platforms.
In addition, the implementatio
On 11/6/23 05:24, Richard Sandiford wrote:
decl_attributes and comp_type_attributes both had code that
iterated over one list of attributes and looked for coresponding
attributes in another list. This patch makes those lookups
namespace-aware.
Tested on aarch64-linux-gnu & x86_64-linux-gnu.
> > I'm unfortunately going down a rabbit hole again.
> >
> > --function.h:608
> > `/* If pointers to member functions use the least significant bit to
> > indicate whether a function is virtual, ensure a pointer to this function
> > will have that bit clear. */ #define MINIMUM_METHOD_BOUNDARY
Ahh, I should have updated my progress last night after all, it would
have saved us some time. Regardless, it's nice to see we independently
came to the same conclusions.
Side note, would you prefer I compile the lambda and by-value fixes
into a new version of this patch? Or as a separate patch? O
On 11/8/23 09:00, Joern Rennecke wrote:
On Fri, 29 Sept 2023 at 14:54, Jeff Law wrote:
... Joern can you post a follow-up manual twiddle so
that other ports can follow your example and avoid this problem?
THanks,
jeff
The attached patch makes the scan-assembler* directives ignore the LT
When I'm working on PR112443, I notice there's some misoptimizations:
after we fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend
fails to combine it back to v{,p}blendv{v,ps,pd} since the pattern is
too complicated, so I think maybe we should hanlde it in the gimple
level.
The dump is like
lgtm Replied Message Frompan2...@intel.comDate11/10/2023 14:22 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Support vec_init for trailing same element
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Friday, November 10, 2023 2:32 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Support vec_init for trailing same element
lgtm
Replied Message
From
pan2
Hello Richard:
On 09/11/23 6:21 pm, Richard Biener wrote:
> On Wed, Nov 8, 2023 at 4:00 PM Ajit Agarwal wrote:
>>
>> tree-ssa-loop-ivopts : Add live analysis in regs used in decision making.
>>
>> Add live anaysis in regs used calculation in decision making of
>> selecting ivopts candidates.
>>
Ping
On 03/11/23 1:14 pm, Surya Kumari Jangala wrote:
> Hi Segher,
> I have incorporated changes in the code as per the review comments provided
> by you
> for version 2 of the patch. Please review.
>
> Regards,
> Surya
>
>
> rs6000/p8swap: Fix incorrect lane extraction by vec_extract() [PR10
Ping ^2.
On 23/10/23 2:02 pm, Ajit Agarwal wrote:
>
>
> Ping ^1.
>
> Forwarded Message
> Subject: [PING ^0][PATCH v2] rs6000: Add new pass for replacement of
> contiguous addresses vector load lxv with lxvp
> Date: Sun, 15 Oct 2023 17:43:24 +0530
> From: Ajit Agarwal
> To:
ping!
Forwarded Message
Subject: [PING ^0] [PATCH v2 3/4] Improve functionality of ree pass with
various constants with AND operation.
Date: Sun, 15 Oct 2023 18:28:51 +0530
From: Ajit Agarwal
To: gcc-patches
CC: Jeff Law , Vineet Gupta ,
Richard Biener , Segher Boessenkool
,
The t0 register is used as a temporary register for interrupts, so it needs
special treatment. It is necessary to avoid using "th.ldd" in the interrupt
program to stop the subsequent operation of the t0 register, so they need to
exchange positions in the function "riscv_for_each_saved_reg".
gcc/Ch
Hi Richard,
Thanks so much for your comments.
在 2023/11/9 19:41, Richard Biener 写道:
> I'm not sure if the testcase is valid though?
>
> @defbuiltin{{void} __builtin_return (void *@var{result})}
> This built-in function returns the value described by @var{result} from
> the containing function.
Ping!
Ok for trunk.
Thanks & Regards
Ajit
Forwarded Message
Subject: [PATCH V15 4/4] ree: Improve ree pass using defined abi interfaces
Date: Sun, 29 Oct 2023 16:14:17 +0530
From: Ajit Agarwal
To: gcc-patches , Jeff Law ,
Vineet Gupta , Bernhard Reutner-Fischer
CC: Richard
On Thu, Nov 9, 2023 at 9:25 PM Vladimir Makarov wrote:
>
>
> On 11/7/23 22:47, Lehua Ding wrote:
> >
> > Lehua Ding (7):
> >ira: Refactor the handling of register conflicts to make it more
> > general
> >ira: Add live_subreg problem and apply to ira pass
> >ira: Support subreg liv
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