Although current GCC didn't cause ICE when I create FP16 vec_init case
with -march=rv64gcv (no ZVFH), current vec_init pattern looks wrong.
Since V_VLS FP16 predicate is TARGET_VECTOR_ELEN_FP_16, wheras vec_init
needs vfslide1down/vfslide1up.
It makes more sense to robustify the vec_init patterns which split them
into 2 patterns (one is integer, the other is float) like other
autovectorization patterns.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_init<mode><vel>): Split patterns.
---
gcc/config/riscv/autovec.md | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..868b47c8af7 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -373,7 +373,19 @@
;; -------------------------------------------------------------------------
(define_expand "vec_init<mode><vel>"
- [(match_operand:V_VLS 0 "register_operand")
+ [(match_operand:V_VLSI 0 "register_operand")
+ (match_operand 1 "")]
+ "TARGET_VECTOR"
+ {
+ riscv_vector::expand_vec_init (operands[0], operands[1]);
+ DONE;
+ }
+)
+
+;; We split RVV floating-point because we are going to
+;; use vfslide1down/vfslide1up for FP16 which need TARGET_ZVFH.
+(define_expand "vec_init<mode><vel>"
+ [(match_operand:V_VLSF 0 "register_operand")
(match_operand 1 "")]
"TARGET_VECTOR"
{
--
2.36.3
