Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

On Mon, 21 Aug 2023, Juzhe-Zhong wrote: > This patch exports 'compute_antinout_edge' and 'compute_earliest' as global > scope > which is going to be used in VSETVL PASS of RISC-V backend. > > The demand fusion is the fusion of VSETVL information to emit VSETVL which > dominate and pre-config fo

RE: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API

To double confirm, you mean this declaration ? +static CONSTEXPR const widen_freducop vfwredusum_frm_obj; Pan From: juzhe.zh...@rivai.ai Sent: Monday, August 21, 2023 2:40 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Support RVV VF

Re: Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

Hi, Richi. This patch is how I use LCM functions: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627953.html >> they are just necessary >> to compute pre_edge_lcm_avs which I see you already do. In Phase 4 I use pre_edge_lcm_av to PRE fo current VSETVL cfg information. However, it's no

[PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

From: Pan Li We have EMIT hook in mode switching already, which will insert the insn before in most cases. However, in some arch like RISC-V, it requires the additional insn to be inserted after when meet a call. | | <- EMIT HOOK, insert the insn before. +---+ | ptr->insn

Re: [PATCH] Testsuite, LTO: silence warning to make test pass on Darwin

On Sun, Aug 20, 2023 at 12:24 PM FX Coudert via Gcc-patches wrote: > > Hi, > > On darwin (both x86_64-apple-darwin and aarch64-apple-darwin) we see the > following test failure: > > FAIL: gcc.dg/lto/20091013-1 c_lto_20091013-1_2.o assemble, -fPIC -r -nostdlib > -O2 -flto > > which is due to this

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 3:20 AM Hongtao Liu via Gcc-patches wrote: > > On Sun, Aug 20, 2023 at 6:44 AM ZiNgA BuRgA via Gcc-patches > wrote: > > > > Hi, > > > > With the proposed design of these switches, how would I restrict AVX10.1 > > to particular AVX-512 subsets? > We can't, avx10.1 is taken

Re: [PATCH] MATCH: [PR111002] Sink view_convert for vec_cond

On Mon, Aug 21, 2023 at 5:22 AM Andrew Pinski via Gcc-patches wrote: > > Like convert we can sink view_convert into vec_cond but > we can only do it if the element types are nop_conversions. > This is to allow conversion between signed and unsigned types only. > Rather than between integer and flo

Re: Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

Hi. Richi. I'd like to share more details that I want to do in VSETVL PASS. Consider this following case: for for for ... for VSETVL demand: RATIO = 32 and TU policy. For this simple case, 'pre_edge_lcm_av' can perfectly work for us, will hoist "vsetvli e32,tu

Re: [PATCH] Add -Wdisabled-optimization warning for not optimizing sibling calls

On Fri, Aug 18, 2023 at 7:13 PM Bradley Lucier wrote: > > On 8/17/23 3:54 AM, Richard Biener wrote: > > I think it needs a new category, 'inline' is probably the "closest" > > existing one > > but that also tends to be noisy. Maybe 'call' would be a good name? We > > could > > report things li

Re: Intel AVX10.1 Compiler Design and Support

Thanks for the responses! It'd be unfortunate if AVX10 adoption is desired, yet there's no way to compile existing 256-bit code to be compatible with it. Relying on SDE to check the output isn't a particularly viable solution. It looks like `-mavx512vl -mprefer-vector-width=256` is my best bet

Re: Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

On Mon, 21 Aug 2023, juzhe.zh...@rivai.ai wrote: > Hi. Richi. > I'd like to share more details that I want to do in VSETVL PASS. > > Consider this following case: > > for > for > for > ... > for >VSETVL demand: RATIO = 32 and TU policy. > > For this simple case

Re: Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

>> Thanks for the explanation, exporting the functions is OK. Thanks. >> It would be nice to put these internal functions into a class or a >> namespace given their non LCM name. Hi, Richi. I saw there is a function "extern void compute_available (sbitmap *, sbitmap *, sbitmap *, sbitmap *);" whi

[PATCH] tree-optimization/111070 - fix ICE with recent ifcombine fix

We now got test coverage for non-SSA name bits so the following amends the SSA_NAME_OCCURS_IN_ABNORMAL_PHI checks. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. Richard. PR tree-optimization/111070 * tree-ssa-ifcombine.cc (ifcombine_ifandif): Check we have

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 09:36:16AM +0200, Richard Biener via Gcc-patches wrote: > > On Sun, Aug 20, 2023 at 6:44 AM ZiNgA BuRgA via Gcc-patches > > wrote: > > > > > > Hi, > > > > > > With the proposed design of these switches, how would I restrict AVX10.1 > > > to particular AVX-512 subsets? > > W

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 4:09 PM Jakub Jelinek wrote: > > On Mon, Aug 21, 2023 at 09:36:16AM +0200, Richard Biener via Gcc-patches > wrote: > > > On Sun, Aug 20, 2023 at 6:44 AM ZiNgA BuRgA via Gcc-patches > > > wrote: > > > > > > > > Hi, > > > > > > > > With the proposed design of these switches

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 04:28:20PM +0800, Hongtao Liu wrote: > We have an undocumented option mavx10-max-512bit. How it is called internally is one thing, but it is weird to use avx10 in an option name which would be meant for finding common subset of -mavx512xxx and -mavx10.1-256. Jakub

Re: Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

Hi, Richi. I found when I try this in lcm.h: namespace lcm { void compute_available (sbitmap *, sbitmap *, sbitmap *, sbitmap *); void compute_antinout_edge (sbitmap *, sbitmap *, sbitmap *, sbitmap *); void compute_earliest (struct edge_list *, int, sbitmap *, sbitmap *, sbitmap *,

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 4:38 PM Jakub Jelinek wrote: > > On Mon, Aug 21, 2023 at 04:28:20PM +0800, Hongtao Liu wrote: > > We have an undocumented option mavx10-max-512bit. > > How it is called internally is one thing, but it is weird to use > avx10 in an option name which would be meant for findin

Re: RE: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API

Yes. I wonder why some floating-point rounding mode has HAS_FRM, some doesn't have? juzhe.zh...@rivai.ai From: Li, Pan2 Date: 2023-08-21 15:10 To: juzhe.zh...@rivai.ai; gcc-patches CC: Wang, Yanzhang; kito.cheng Subject: RE: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsi

[PATCH] debug/111080 - avoid outputting debug info for unused restrict qualified type

The following applies some maintainance with respect to type qualifiers and kinds added by later DWARF standards to prune_unused_types_walk. The particular case in the bug is not handling (thus marking required) all restrict qualified type DIEs. I've found more DW_TAG_*_type that are unhandled, lo

Re: Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

On Mon, 21 Aug 2023, juzhe.zh...@rivai.ai wrote: > Hi, Richi. > > I found when I try this in lcm.h: > > namespace lcm { > void compute_available (sbitmap *, sbitmap *, sbitmap *, sbitmap *); > void compute_antinout_edge (sbitmap *, sbitmap *, sbitmap *, sbitmap *); > void compute_earliest (struc

Re: Intel AVX10.1 Compiler Design and Support

Another way (not saying this is better, just throwing out ideas) is to break AVX10.1 into all the AVX-512 subsets. So you'd have something like -mavx10.1-256-vl, -mavx10.1-512-vbmi etc. * -mavx10.1-256  would effectively be an alias for all the 128+256-bit subsets, and set the __AVX10_1__ defin

Re: [PATCH] LCM: Export 2 helpful functions as global for VSETVL PASS use in RISC-V backend

Committed, thanks Richard. On 2023/8/21 17:12, Richard Biener via Gcc-patches wrote: On Mon, 21 Aug 2023, juzhe.zh...@rivai.ai wrote: Hi, Richi. I found when I try this in lcm.h: namespace lcm { void compute_available (sbitmap *, sbitmap *, sbitmap *, sbitmap *); void compute_antinout_edge (

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 10:28 AM Hongtao Liu wrote: > > On Mon, Aug 21, 2023 at 4:09 PM Jakub Jelinek wrote: > > > > On Mon, Aug 21, 2023 at 09:36:16AM +0200, Richard Biener via Gcc-patches > > wrote: > > > > On Sun, Aug 20, 2023 at 6:44 AM ZiNgA BuRgA via Gcc-patches > > > > wrote: > > > > > >

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 11:34 AM Richard Biener wrote: > > On Mon, Aug 21, 2023 at 10:28 AM Hongtao Liu wrote: > > > > On Mon, Aug 21, 2023 at 4:09 PM Jakub Jelinek wrote: > > > > > > On Mon, Aug 21, 2023 at 09:36:16AM +0200, Richard Biener via Gcc-patches > > > wrote: > > > > > On Sun, Aug 20,

[committed] libstdc++: Remove reliance on unspecified behaviour in std::rethrow_if_nested test

This is the patch resolving the non-portable test that Iain raised in: https://gcc.gnu.org/pipermail/libstdc++/2023-August/056534.html Tested x86_64-linux. Pushed to trunk. Backports would be OK, but I don't think they are needed. -- >8 -- This test case calls std::set_terminate while there is

[PATCH] tree-optimization/111082 - bogus promoted min

vectorize_slp_instance_root_stmt promotes operations with undefined overflow to unsigned arithmetic but fails to consider operations that do not overflow like MIN which it turned into MIN with wrong signedness and in the case of the PR an unsupported operation. The following rectifies this. Bootst

Re: Intel AVX10.1 Compiler Design and Support

On Mon, Aug 21, 2023 at 5:35 PM Richard Biener wrote: > > On Mon, Aug 21, 2023 at 10:28 AM Hongtao Liu wrote: > > > > On Mon, Aug 21, 2023 at 4:09 PM Jakub Jelinek wrote: > > > > > > On Mon, Aug 21, 2023 at 09:36:16AM +0200, Richard Biener via Gcc-patches > > > wrote: > > > > > On Sun, Aug 20,

[PATCH] Adjust testcase for Intel GDS.

gcc/testsuite/ChangeLog: * gcc.target/i386/avx512f-pr88464-2.c: Add -mgather to options. * gcc.target/i386/avx512f-pr88464-3.c: Ditto. * gcc.target/i386/avx512f-pr88464-4.c: Ditto. * gcc.target/i386/avx512f-pr88464-6.c: Ditto. * gcc.target/i386/avx51

Re: [PATCH] tree-optimization/111048 - avoid flawed logic in fold_vec_perm

On Mon, 21 Aug 2023 at 12:26, Richard Biener wrote: > > On Sat, 19 Aug 2023, Prathamesh Kulkarni wrote: > > > On Fri, 18 Aug 2023 at 14:52, Richard Biener wrote: > > > > > > On Fri, 18 Aug 2023, Richard Sandiford wrote: > > > > > > > Richard Biener writes: > > > > > The following avoids running

Re: [PATCH] tree-optimization/111048 - avoid flawed logic in fold_vec_perm

Prathamesh Kulkarni writes: > On Mon, 21 Aug 2023 at 12:26, Richard Biener wrote: >> >> On Sat, 19 Aug 2023, Prathamesh Kulkarni wrote: >> >> > On Fri, 18 Aug 2023 at 14:52, Richard Biener wrote: >> > > >> > > On Fri, 18 Aug 2023, Richard Sandiford wrote: >> > > >> > > > Richard Biener writes:

[PATCH V5] VECT: Support loop len control on EXTRACT_LAST vectorization

Co-Authored-By: Kewen.Lin Hi, @Richi and @Richard, base on previous disscussion, I simpily fix issuses for powerpc and s390 with your suggestions: - machine_mode len_load_mode = get_len_load_store_mode -(loop_vinfo->vector_mode, true).require (); - machine_mode len_store_mode = get_len_loa

[PATCH] Fix gcc.dg/vect/bb-slp-46.c FAIL

When relaxing vectorization of possibly overflowing reductions I failed to update a testcase that will now vectorize and no longer test for what it was written for. The following replaces the vectorizable add with a division. Tested on x86_64-unknown-linux-gnu, pushed. * gcc.dg/vect/bb-s

Re: [PATCH][RFC] tree-optimization/92335 - Improve sinking heuristics for vectorization

On Mon, 21 Aug 2023 at 12:27, Richard Biener wrote: > > On Sat, 19 Aug 2023, Prathamesh Kulkarni wrote: > > > On Fri, 18 Aug 2023 at 17:11, Richard Biener wrote: > > > > > > On Fri, 18 Aug 2023, Richard Biener wrote: > > > > > > > On Thu, 17 Aug 2023, Prathamesh Kulkarni wrote: > > > > > > > > >

[PATCH] Fix gcc.dg/vect/bb-slp-subgroups-2.c with 256bit vectors

The following adds vect128, vect256 and vect512 effective targets and adjusts gcc.dg/vect/bb-slp-subgroups-2.c accordingly. Tested on x86_64-unknown-linux-gnu, pushed. * gcc.dg/vect/bb-slp-subgroups-2.c: Properly handle the vect256 case. --- gcc/testsuite/gcc.dg/vect/bb-slp-subgr

[PATCH] Fix FAIL: gcc.target/i386/pr87007-5.c

The following fixes the gcc.target/i386/pr87007-5.c testcase which changed code generation again after the recent sinking improvements. We now have vxorps %xmm0, %xmm0, %xmm0 vsqrtsd d2(%rip), %xmm0, %xmm0 and an unnecessary xor again in one case, the other vsqrtsd has a register

RE: RE: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API

By design, HAS_FRM must be present if this insn honor FRM. For example, if one insn don't honor FRM, there should be only one declaration as below. static CONSTEXPR const binop vfmax_obj; But if one insn honors FRM, there will be 2 declaration as below for code reuse. static CONSTEXPR const bin

Re: [PATCH] Fix FAIL: gcc.target/i386/pr87007-5.c

On Mon, Aug 21, 2023 at 8:25 PM Richard Biener via Gcc-patches wrote: > > The following fixes the gcc.target/i386/pr87007-5.c testcase which > changed code generation again after the recent sinking improvements. > We now have > > vxorps %xmm0, %xmm0, %xmm0 > vsqrtsd d2(%rip), %xmm

Re: [PATCH] Fix FAIL: gcc.target/i386/pr87007-5.c

On Mon, Aug 21, 2023 at 8:40 PM Hongtao Liu wrote: > > On Mon, Aug 21, 2023 at 8:25 PM Richard Biener via Gcc-patches > wrote: > > > > The following fixes the gcc.target/i386/pr87007-5.c testcase which > > changed code generation again after the recent sinking improvements. > > We now have > > >

Re: [PATCH] Fix FAIL: gcc.target/i386/pr87007-5.c

On Mon, 21 Aug 2023, Hongtao Liu wrote: > On Mon, Aug 21, 2023 at 8:25?PM Richard Biener via Gcc-patches > wrote: > > > > The following fixes the gcc.target/i386/pr87007-5.c testcase which > > changed code generation again after the recent sinking improvements. > > We now have > > > > vxo

Re: [PATCH] Fix FAIL: gcc.target/i386/pr87007-5.c

On Mon, Aug 21, 2023 at 8:59 PM Richard Biener wrote: > > On Mon, 21 Aug 2023, Hongtao Liu wrote: > > > On Mon, Aug 21, 2023 at 8:25?PM Richard Biener via Gcc-patches > > wrote: > > > > > > The following fixes the gcc.target/i386/pr87007-5.c testcase which > > > changed code generation again afte

Re: [PATCH] RISC-V/testsuite: Add missing conversion tests.

On 8/18/23 13:32, Robin Dapp wrote: Hi, this patch adds some missing tests for vf[nw]cvt. Regards Robin gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Add tests. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv

Re: [PATCH 1/2] RISC-V: Add quotes to #error messages

On 8/17/23 21:52, Tsukasa OI wrote: From: Tsukasa OI In commit 1aaf3a64e92a ("[PATCH] RISC-V: Deduplicate #error messages in testsuite"), the author made a mistake to miss the test after adding quotes around extension names. To avoid future errors and for consistency with other #error uses

Re: [committed][RISC-V] Fix 20010221-1.c with zicond

On Tue, 8 Aug 2023, Jeff Law wrote: > > I wonder however why do we need so much more code, including the middle > > end too, to support this ISA extension than we do for the very same set of > > MIPSr6 instructions under ISA_HAS_SEL, hmm... > Because it doesn't handle as many cases as we're hand

Re: RISC-V: Added support for CRC.

Thank you for the review. I'm already working on suggested changes. The answers to the few questions are attached here. Thanks, Mariam On Wed, Aug 16, 2023 at 8:59 AM Jeff Law wrote: > > > On 8/3/23 13:37, Mariam Harutyunyan via Gcc-patches wrote: > > This patch adds CRC support for the RISC-V

Re: [PATCH V5] VECT: Support loop len control on EXTRACT_LAST vectorization

On Mon, 21 Aug 2023, Juzhe-Zhong wrote: > Co-Authored-By: Kewen.Lin > > Hi, @Richi and @Richard, base on previous disscussion, I simpily fix issuses > for > powerpc and s390 with your suggestions: > > - machine_mode len_load_mode = get_len_load_store_mode > -(loop_vinfo->vector_mode, true

[COMMITTED] [frange] Return false if nothing changed in union_nans().

When one operand is a known NAN, we always return TRUE from union_nans(), even if no change occurred. This patch fixes the oversight. gcc/ChangeLog: * value-range.cc (frange::union_nans): Return false if nothing changed. (range_tests_floats): New test. --- gcc/value-rang

Re: [RFC PATCH v2 1/2] RISC-V: __builtin_riscv_pause for all environment

On 8/16/23 02:33, Philipp Tomsich wrote: Could we use the underlying 'fence' instruction (unless the assembler rejects the specific form that is needed) instead of the hex-insn? Should this also check HAVE_AS_MARCH_ZIHINTPAUSE (which must then also be added to configure.ac)? It seems reasona

Re: [PATCH] gimple_fold: Support COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold

Juzhe-Zhong writes: > Hi, Richard and Richi. > > Currently, GCC support COND_LEN_FMA for floating-point **NO** -ffast-math. > It's supported in tree-ssa-math-opts.cc. However, GCC failed to support > COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS. > > Consider this following case: > #define TEST_TYPE(T

Re: [PATCH] gimple_fold: Support COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold

Richard Biener writes: > On Wed, 16 Aug 2023, Juzhe-Zhong wrote: > >> Hi, Richard and Richi. >> >> Currently, GCC support COND_LEN_FMA for floating-point **NO** -ffast-math. >> It's supported in tree-ssa-math-opts.cc. However, GCC failed to support >> COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS. >>

Re: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

On 8/21/23 01:26, pan2...@intel.com wrote: From: Pan Li We have EMIT hook in mode switching already, which will insert the insn before in most cases. However, in some arch like RISC-V, it requires the additional insn to be inserted after when meet a call. | | <- EMIT HOOK, i

Re: [PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg

On 8/17/23 20:53, Pan Li via Gcc-patches wrote: From: Pan Li As suggested by kito, we will add new frm_opt_type template arg to the op class, to avoid the duplicated function expand. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class

Re: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API

On 8/17/23 02:05, Pan Li via Gcc-patches wrote: From: Pan Li This patch would like to support the rounding mode API for the VFWREDUSUM.VS as the below samples * __riscv_vfwredusum_vs_f32m1_f64m1_rm * __riscv_vfwredusum_vs_f32m1_f64m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * c

Re: [PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg

Just one nit from me: plz add assertion to OP_TYPE_vx to make sure NO FRM_OP == HAS_FRM there On Mon, Aug 21, 2023 at 11:04 PM Jeff Law via Gcc-patches wrote: > > > > On 8/17/23 20:53, Pan Li via Gcc-patches wrote: > > From: Pan Li > > > > As suggested by kito, we will add new frm_opt_type templ

Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

Hi Juzhe, thanks, this is a reasonable approach and improves readability noticeably. LGTM but I'd like to wait for other opinions (e.g. by Kito) as I haven't looked closely into the vsetvl pass before and cannot entirely review it quickly. As we already have good test coverage there is not much t

Patch ping Re: [PATCH 0/12] GCC _BitInt support [PR102989]

Hi! On Wed, Aug 09, 2023 at 08:14:14PM +0200, Jakub Jelinek via Gcc-patches wrote: > Jakub Jelinek (12): > expr: Small optimization [PR102989] > lto-streamer-in: Adjust assert [PR102989] > phiopt: Fix phiopt ICE on vops [PR102989] > Middle-end _BitInt support [PR102989] > _BitInt lowerin

[PATCH] s390: Fix some builtin definitions

Bootstrapped and regtested on s390. Ok for mainline? gcc/ChangeLog: * config/s390/s390-builtins.def (s390_vec_signed_flt): Fix builtin flag. (s390_vec_unsigned_flt): Ditto. (s390_vec_revb_flt): Ditto. (s390_vec_reve_flt): Ditto. (s390_vclfnhs): Fix

[PATCH] s390: Fix builtins vec_rli and verll

The second argument of these builtins is an unsigned immediate. For vec_rli the API allows immediates up to 64 bits whereas the instruction verll only allows immediates up to 32 bits. Since the shift count equals the immediate modulo vector element size, truncating those immediates is fine. Boot

Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

I think I could do some details review tomorrow on the plane, I am free from the meeting hell tomorrow :p Robin Dapp via Gcc-patches 於 2023年8月21日 週一 23:24 寫道： > Hi Juzhe, > > thanks, this is a reasonable approach and improves readability noticeably. > LGTM but I'd like to wait for other opinio

RE: [PING][PATCH] arm: Remove unsigned variant of vcaddq_m

Ok. Thanks, Kyrill From: Stam Markianos-Wright Sent: Saturday, August 19, 2023 12:42 PM To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov ; Richard Earnshaw Subject: [PING][PATCH] arm: Remove unsigned variant of vcaddq_m (Pinging since I realised that this is required for my later Low Overhead

[OpenMP/offloading][RFC] How to handle target/device-specifics with C pre-processor (in general, inside 'omp declare variant')

RFC – and idea how to handle this best in GCC? See the two examples below for what we would like to support. * * * In GCC, we handle OpenMP (and OpenACC) by parsing the input file once, produce an internal representation (in LTO format) for offloading code and only at link time process it by pas

Re: [PATCH] aarch64: fix format specifier

On 18/08/2023 17:37, FX Coudert via Gcc-patches wrote: A rather trivial fix for fprintf() specifier of a HOST_WIDE_INT value. Tested on aarch64-apple-darwin. OK to commit? FX OK. R.

[PATCH] RISC-V: Add Types to Missing Bitmanip Instructions:

Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/ This patch updates the bitmanip instructions to ensure that no insn is left without a type attribute. Updates a total of 8 insns to have type "bitmanip" Tested for regressions using rv32/6

[PATCH] RISC-V: Add Types to Un-Typed Sync Instructions:

Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/ This patch updates the sync instructions to ensure that no insn is left without a type attribute. Updates a total of 6 insns to have type "atomic" Tested for regressions using rv32/64 mult

[PATCH] Fix tests sensitive to internal library allocations

Hi Here is a propocal to fix tests sensitive to libstdc++ internal allocations. Tested by restoring allocation in tzdb.cc. As announced I'm also adding a test to detect such allocations. If it is ok let me know if you prefer to see it in a different place.     libstdc++: Fix tests relying on

[no subject]

Hello, Hope you are doing well with the family. I noticed on LinkedIn. Can I share an idea here?

[RISCV][committed] Remove spurious newline in ztso sequence

amo-table-ztso-load-3 the coordination branch after merging up the Ztso changes due to a spurious newline in the output causing scan-function-body to fail. There's probably an over-zealous .* or similar regexp in the framework. I didn't see it in a quick scan, but could have easily missed i

Re: Patch ping Re: [PATCH 0/12] GCC _BitInt support [PR102989]

On Mon, 21 Aug 2023, Jakub Jelinek via Gcc-patches wrote: > Joseph, could I ask now at least for an overall design review of the > C patches (8-10,13) whether its interfaces with middle-end are ok, > so that Richi can review the middle-end parts? I am fine with the interface to the middle-end par

Re: [PATCH v7 4/5] OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic

On Fri, 18 Aug 2023 15:47:50 -0700 Julian Brown wrote: > This version of the patch scales back the previously-posted version to > merely add a diagnostic for incorrect usage of component accesses with > variably-indexed arrays of structs: the only permitted variant is > where we have multiple ind

[PATCH V2] Emit funcall external declarations only if actually used.

[Differences from V1: - Prototype for call_from_call_insn moved before comment block. - Reuse the `call' flag for SYMBOL_REF_LIBCALL. - Fallback to check REG_CALL_DECL in non-direct calls. - New test to check correct behavior for non-direct calls.] There are many places in GCC where alternative lo

Re: [PATCH] Fix tests sensitive to internal library allocations

On Mon, 21 Aug 2023 at 18:05, François Dumont via Libstdc++ wrote: > > Hi > > Here is a propocal to fix tests sensitive to libstdc++ internal allocations. Surely the enter() and exit() calls should be a constructor and destructor? The constructor could use count() to get the count, and then rest

Re: [PATCH] testsuite: Adjust g++.dg/gomp/pr58567.C to new compiler message

Hello Tobias, Tobias Burnus writes: > On 18.08.23 23:24, Thiago Jung Bauermann wrote: >> Tobias Burnus writes: >>> the patch looks good to me. Thanks! Can you commit the patch yourself or >>> do you need someone to do this for you? >> Thank you! I don't have commit access, so I would need som

Re: [PATCH] libgomp, testsuite: Do not call nonstandard functions on darwin

Hi FX, On 20.08.23 21:37, FX Coudert wrote: testsuite/libgomp.c/simd-math-1.c calls nonstandard functions that are not available on darwin (and possibly other systems?). Namely: * "gamma" which has been repaced by tgamma and lgamma as BSD's gamma == tgamma while glibc's gamma == lgamma. * __

Re: [PATCH] Remove XFAIL from gcc/testsuite/gcc.dg/unroll-7.c

Thiago Jung Bauermann via Gcc-patches writes: > This test passes since commit e41103081bfa "Fix undefined behaviour in > profile_count::differs_from_p", so remove the xfail annotation. > > Tested on aarch64-linux-gnu, armv8l-linux-gnueabihf and x86_64-linux-gnu. > > gcc/testsuite/ChangeLog: >

Re: [PATCH] libgomp, testsuite: Do not call nonstandard functions on darwin

On Mon, Aug 21, 2023 at 09:12:09PM +0200, Tobias Burnus wrote: > OK. — I'd prefer if you also changed + tested a fix for my (a) + (b) > remarks, but as those are unrelated, I understand if you don't and just > commit your Darwin patch. I don't like the #if !defined(__APPLE__) conditionals everywhe

[PATCH] Fortran: implement vector sections in DATA statements [PR49588]

Dear all, the attached patch implements vector sections in DATA statements. The implementation is simpler than the size of the patch suggests, as part of changes try to clean up the existing code to make it easier to understand, as ordinary sections (start:end:stride) and vector sections may actu

Re: [PATCH] libgomp, testsuite: Do not call nonstandard functions on darwin

> I don't like the #if !defined(__APPLE__) conditionals everywhere in the > test, I think much cleaner would be to add an effective target to test > for those functions I understand, I wanted to not just report the issue but propose an option. It seems a bit heavy to design an effective target ju

Re: [PATCH] libgomp, testsuite: Do not call nonstandard functions on darwin

On Mon, Aug 21, 2023 at 09:50:37PM +0200, FX Coudert wrote: > > I don't like the #if !defined(__APPLE__) conditionals everywhere in the > > test, I think much cleaner would be to add an effective target to test > > for those functions > > I understand, I wanted to not just report the issue but pro

Re: [PATCH] RISC-V: Support simplify (-1-x) for vector.

On Wed, 16 Aug 2023 at 14:12, yanzhang.wang--- via Gcc-patches wrote: > > From: Yanzhang Wang > > The pattern is enabled for scalar but not for vector. The patch try to > make it consistent and will convert below code, (CCing Richard S.) Hi, Sorry if this comment is not relevant to the patch but

Re: [PATCH] libgomp, testsuite: Do not call nonstandard functions on darwin

>> I understand, I wanted to not just report the issue but propose an option. >> It seems a bit heavy to design an effective target just for one test, >> though, no? > > It has the advantage of getting it right on all current and future targets. Something like this? (not tested yet) diff --gi

Re: [PATCH] libgomp, testsuite: Do not call nonstandard functions on darwin

On Mon, Aug 21, 2023 at 10:00:30PM +0200, FX Coudert wrote: > >> I understand, I wanted to not just report the issue but propose an option. > >> It seems a bit heavy to design an effective target just for one test, > >> though, no? > > > > It has the advantage of getting it right on all current

Re: [PATCH] Fix tests sensitive to internal library allocations

Here is the updated and tested patch. On 21/08/2023 20:07, Jonathan Wakely wrote: On Mon, 21 Aug 2023 at 18:05, François Dumont via Libstdc++ wrote: Hi Here is a propocal to fix tests sensitive to libstdc++ internal allocations. Surely the enter() and exit() calls should be a constructor and

Re: RISCV test infrastructure for d / v / zfh extensions

Hi Joern. > Hmm, you are right. I personally prefer my version because it allows > consistent naming of the > different tests, also easily extendible when new extensions need testing. > Although the riscv_vector name has the advantage that it is better > legible for people who are > not used to d

[PATCH 0/2] libstdc++: Documentation fixes.

This small patch-series fixes the 'doc-install-info' rule and updates the URI used for docbook-xsl. Bruno Victal (2): libstdc++: Fix 'doc-install-info' rule. libstdc++: Update docbook xsl URI. libstdc++-v3/acinclude.m4| 2 +- libstdc++-v3/doc/Makefile.am | 4 ++-- 2 files changed, 3 inse

[PATCH 2/2] libstdc++: Update docbook xsl URI.

The URI for namespaced docbook-xsl was updated to reflect the current DocBook upstream at . libstdc++-v3/Changelog: * acinclude.m4: Update docbook xsl URI. * configure: Regenerate. --- libstdc++-v3/acinclude.m4 | 2 +- 1 file changed, 1 insertion(+), 1 de

[PATCH 1/2] libstdc++: Fix 'doc-install-info' rule.

The info manual isn't moved to the expected location after generation which causes the install rule for it to fail. libstdc++-v3/Changelog: * doc/Makefile.in: Regenerate. * doc/Makefile.am: Fix 'doc-install-info' rule. Fix typo in commment. --- libstdc++-v3/doc/Makefile.a

Re: [PATCH 0/2] libstdc++: Documentation fixes.

On Mon, 21 Aug 2023, 21:33 Bruno Victal, wrote: > This small patch-series fixes the 'doc-install-info' rule > and updates the URI used for docbook-xsl. > Thanks! I'll get these committed tomorrow. > Bruno Victal (2): > libstdc++: Fix 'doc-install-info' rule. > libstdc++: Update docbook xs

Re: [PATCH 2/2] VR-VALUES: Rewrite test_for_singularity using range_op_handler

On Fri, Aug 11, 2023 at 8:08 AM Andrew MacLeod via Gcc-patches wrote: > > > On 8/11/23 05:51, Richard Biener wrote: > > On Fri, Aug 11, 2023 at 11:17 AM Andrew Pinski via Gcc-patches > > wrote: > >> So it turns out there was a simplier way of starting to > >> improve VRP to start to fix PR 110131

[PATCH] bpf: neg instruction does not accept an immediate

The BPF virtual machine does not support neg nor neg32 instructions with an immediate. The erroneous instructions were removed from binutils: https://sourceware.org/pipermail/binutils/2023-August/129135.html Change the define_insn so that an immediate cannot be accepted. >From testing, a neg-imm

Re: [PATCH] RISC-V: Add Types to Missing Bitmanip Instructions:

On 8/21/23 10:37, Edwin Lu wrote: This patch updates the bitmanip instructions to ensure that no insn is left without a type attribute. Updates a total of 8 insns to have type "bitmanip" Tested for regressions using rv32/64 multilib with newlib/linux. gcc/Changelog: * config/riscv/b

Re: [PATCH] Fix tests sensitive to internal library allocations

On Mon, 21 Aug 2023 at 21:20, François Dumont wrote: > > Here is the updated and tested patch. OK for trunk, thanks. We could consider it for the branches too (I'm going to remove the global strings on the gcc-13 branch tomorrow). > > On 21/08/2023 20:07, Jonathan Wakely wrote: > > On Mon, 21

Re: [PATCH] RISC-V: Add Types to Un-Typed Sync Instructions:

On 8/21/23 10:51, Edwin Lu wrote: Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/ This patch updates the sync instructions to ensure that no insn is left without a type attribute. Updates a total of 6 insns to have type "atomic" Te

Re: [PATCH] bpf: neg instruction does not accept an immediate

> The BPF virtual machine does not support neg nor neg32 instructions with > an immediate. > > The erroneous instructions were removed from binutils: > https://sourceware.org/pipermail/binutils/2023-August/129135.html > > Change the define_insn so that an immediate cannot be accepted. > > From te

Re: [PATCH] Remove XFAIL from gcc/testsuite/gcc.dg/unroll-7.c

Richard Sandiford writes: > Thiago Jung Bauermann via Gcc-patches writes: >> This test passes since commit e41103081bfa "Fix undefined behaviour in >> profile_count::differs_from_p", so remove the xfail annotation. >> >> Tested on aarch64-linux-gnu, armv8l-linux-gnueabihf and x86_64-linux-gnu.

RE: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API

Committed, thanks Jeff. Pan -Original Message- From: Jeff Law Sent: Monday, August 21, 2023 11:06 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic

RE: [PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg

Thanks Kito and Jeff for comments, will double check and address the comment in v2. Pan -Original Message- From: Kito Cheng Sent: Monday, August 21, 2023 11:07 PM To: Jeff Law Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V

Re: [PATCH V5] VECT: Support loop len control on EXTRACT_LAST vectorization

Hi Juzhe, on 2023/8/21 18:59, Juzhe-Zhong wrote: > Co-Authored-By: Kewen.Lin > > Hi, @Richi and @Richard, base on previous disscussion, I simpily fix issuses > for > powerpc and s390 with your suggestions: > > - machine_mode len_load_mode = get_len_load_store_mode > -(loop_vinfo->vector_m

[pushed 1/6] analyzer: convert note_adding_context to annotating_context

This is enabling work towards the context being able to inject events into diagnostic paths, rather than just notes after the warning. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-3371-ge40a935db29cfd. gcc/analyzer/ChangeLog: * region-model.cc

[pushed 3/6] analyzer: handle NULL inner context in region_model_context_decorator

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-3373-g1e7b0a5d7a45dc. gcc/analyzer/ChangeLog: * region-model.cc (region_model_context_decorator::add_event): Handle m_inner being NULL. * region-model.h (class region_model_context_decorat

[pushed 5/6] analyzer: add kf_fopen

Add checking to -fanalyzer that both params of calls to "fopen" are valid null-terminated strings. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-3375-g4325c82736d9e8. gcc/analyzer/ChangeLog: * kf.cc (class kf_fopen): New. (register_known_fun

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