Re: [PATCH] New finish_compare_by_pieces target hook (for x86).

On Sun, Jun 25, 2023 at 7:39 AM Roger Sayle wrote: > > > On Tue, 13 June 2023 12:02, Richard Biener wrote: > > On Mon, Jun 12, 2023 at 4:04 PM Roger Sayle > > wrote: > > > The following simple test case, from PR 104610, shows that memcmp () > > > == 0 can result in some bizarre code sequences on

Re: [PATCH 2/3] Don't use intermiediate type for FIX_TRUNC_EXPR when ftrapping-math.

On Mon, Jun 26, 2023 at 3:31 AM liuhongt via Gcc-patches wrote: > > > > Hmm, good question. GENERIC has a direct truncation to unsigned char > > > for example, the C standard generally says if the integral part cannot > > > be represented then the behavior is undefined. So I think we should be >

[PATCH V3] DSE: Add LEN_MASK_STORE analysis into DSE and fix LEN_STORE

From: Ju-Zhe Zhong Hi, Richi. This patch is adding LEN_MASK_STORE into DSE. My understanding is LEN_MASK_STORE is predicated by mask and len. No matter len is constant or not, the ao_ref should be the same as MASK_STORE. Wheras for LEN_STORE, when len is constant, we use (len - bias), otherwis

Re: [PATCH 1/3] Use cvt_op to save intermediate type operand instead of "subtle" vec_dest.

On Mon, 26 Jun 2023, liuhongt wrote: > When there're multiple operands in vec_oprnds0, vec_dest will be > overwrited to vectype_out, but in multi_step_cvt case, cvt_type is > expected. It caused an ICE when verify_gimple_in_cfg. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} and >

Re: [PATCH] GIMPLE_FOLD: Fix gimple fold for LEN_MASK_{LOAD,STORE}

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, previous I made a mistake on GIMPLE_FOLD of LEN_MASK_{LOAD,STORE}. > > We should fold LEN_MASK_{LOAD,STORE} (bias+len) == vf (nunits instead of > bytesize) && mask = all trues mask > > into: >MEM_REF [...]. > >

Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

Hi Juzhe, > Currently, we are able to generate step vector with base == 0: > { 0, 0, 2, 2, 4, 4, ... } > > ASM: > > vid > vand > > However, we do wrong for step vector with base != 0: > { 1, 1, 3, 3, 5, 5, ... } > > Before this patch, such case will run fail. > > After this patch, we are abl

Re: [PATCH V2] DSE: Add LEN_MASK_STORE analysis into DSE

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Add LEN_MASK_STORE. > (dse_optimize_stmt): Ditto. > > --- > gcc/tree-ssa-dse.cc | 27 +++ > 1 file changed, 27 in

Re: [PATCH] SCCVN: Fix repeating variable name "len"

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Line 3292: has variable name "len": tree mask = NULL_TREE, len = NULL_TREE, > bias = NULL_TREE; > Line 3349: has variable name "len": HOST_WIDE_INT start = 0, len = 0; > > Since they are never used simultaneously, such i

Re: [PATCH] SSCV: Add LEN_MASK_STORE into SCCVN

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, this patch is to add LEN_MASK_STORE into SCCVN. > > LEN_MASK_STORE is predicated by both len and mask together. > My understanding is that LEN_MASK_STORE has same rhs_off and offset as > MASK_STORE. > The size = MIN

[PATCH V2] GIMPLE_FOLD: Fix gimple fold for LEN_{MASK}_{LOAD,STORE}

From: Ju-Zhe Zhong Hi, previous I made a mistake on GIMPLE_FOLD of LEN_MASK_{LOAD,STORE}. We should fold LEN_MASK_{LOAD,STORE} (bias+len) == vf (nunits instead of bytesize) && mask = all trues mask into: MEM_REF [...]. This patch added testcase to test gimple fold of LEN_MASK_{LOAD,STORE}.

Re: [PATCH V3] DSE: Add LEN_MASK_STORE analysis into DSE and fix LEN_STORE

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, Richi. > > This patch is adding LEN_MASK_STORE into DSE. > > My understanding is LEN_MASK_STORE is predicated by mask and len. > No matter len is constant or not, the ao_ref should be the same as MASK_STORE. > > Whe

Re: [PATCH V2] GIMPLE_FOLD: Fix gimple fold for LEN_{MASK}_{LOAD,STORE}

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, previous I made a mistake on GIMPLE_FOLD of LEN_MASK_{LOAD,STORE}. > > We should fold LEN_MASK_{LOAD,STORE} (bias+len) == vf (nunits instead of > bytesize) && mask = all trues mask > > into: >MEM_REF [...]. > >

Re: [PATCH 3/3] [aarch64] Adjust testcase to match assembly output after r14-2007.

liuhongt writes: > The new assembly looks better than original one, so I adjust those testcases. The new loops are shorter, but they process only half the amount of data per iteration. The problem is that the new vectoriser code generates multiple statements but only costs one. I'll post a fix

Re: [PATCH][RFC] middle-end/110237 - wrong MEM_ATTRs for partial loads/stores

On Wed, Jun 21, 2023 at 3:49 PM Richard Biener via Gcc-patches wrote: > > The following addresses a miscompilation by RTL scheduling related > to the representation of masked stores. For that we have > > (insn 38 35 39 3 (set (mem:V16SI (plus:DI (reg:DI 40 r12 [orig:90 _22 ] [90]) >

Re: [PATCH][RFC] middle-end/110237 - wrong MEM_ATTRs for partial loads/stores

On Mon, 26 Jun 2023, Hongtao Liu wrote: > On Wed, Jun 21, 2023 at 3:49?PM Richard Biener via Gcc-patches > wrote: > > > > The following addresses a miscompilation by RTL scheduling related > > to the representation of masked stores. For that we have > > > > (insn 38 35 39 3 (set (mem:V16SI (plus

Re: [PATCH] RISC-V: Remove redundant vcond patterns

On Mon, 26 Jun 2023, Juzhe-Zhong wrote: > Previously, Richi has suggested that vcond patterns are only needed when > target > support comparison + select consuming 1 instruction. > > Now, I do the experiments on removing those "vcond" patterns, it works > perfectly. > > All testcases PASS. >

Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors

On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches wrote: > > Hi, > > Packed Boolean Vectors > -- > > I'd like to propose a feature addition to GNU Vector extensions to add packed > boolean vectors (PBV). This has been discussed in the past here[1] and a > variant

[PATCH] Issue a warning for conversion between short and __bf16 under TARGET_AVX512BF16.

__bfloat16 is redefined from typedef short to real __bf16 since GCC V13. The patch issues an warning for potential silent implicit conversion between __bf16 and short where users may only expect a data movement. To avoid too many false positive, warning is only under TARGET_AVX512BF16. Bootstrapp

Re: [PATCH] Add __builtin_iseqsig()

ping**2 > Le 6 juin 2023 à 20:15, FX Coudert a écrit : > > Hi, > > (It took me a while to get back to this.) > > This is a new and improved version of the patch at > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602932.html > It addresses the comment from Joseph that FE_INVALID shou

Re: [PATCH] RISC-V: Remove redundant vcond patterns

ok for trunk, thanks :) On Mon, Jun 26, 2023 at 4:44 PM Richard Biener via Gcc-patches wrote: > > On Mon, 26 Jun 2023, Juzhe-Zhong wrote: > > > Previously, Richi has suggested that vcond patterns are only needed when > > target > > support comparison + select consuming 1 instruction. > > > > Now

Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

Could you re-title this patch into something like "Support const vector expansion with xxx pattern", On Mon, Jun 26, 2023 at 3:52 PM Robin Dapp via Gcc-patches wrote: > > Hi Juzhe, > > > Currently, we are able to generate step vector with base == 0: > > { 0, 0, 2, 2, 4, 4, ... } > > > > ASM: > >

Re: [PATCH v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic

Hi, Jeff: I have filled out the form. May I ask if you have received my application? Is there anything else I need to do? Thanks. -- Li Xu > > >On 6/25/23 03:13, juzhe.zh...@rivai.ai wrote: >> LGTM. >> Thanks for fixing it. >Agreed.  I didn't see the V2 had already been posted. > >>

Re: [PATCH] Implement ipa_vr hashing.

PING*3 On Thu, Jun 22, 2023 at 7:49 AM Aldy Hernandez wrote: > > Ping*2 > > On Wed, Jun 14, 2023, 14:11 Aldy Hernandez wrote: >> >> PING >> >> On Sat, Jun 10, 2023 at 10:30 PM Aldy Hernandez wrote: >> > >> > >> > >> > On 5/29/23 16:51, Martin Jambor wrote: >> > > Hi, >> > > >> > > On Mon, May 2

Re: [PATCH] Implement ipa_vr hashing.

Errr, sorry about this ping. I was meant to re-ping my IPA patches after 7 days, but just realized it had been only 4. My bad. Aldy On Mon, Jun 26, 2023 at 11:22 AM Aldy Hernandez wrote: > > PING*3 > > On Thu, Jun 22, 2023 at 7:49 AM Aldy Hernandez wrote: > > > > Ping*2 > > > > On Wed, Jun 14

RE: [PATCH] SCCVN: Fix repeating variable name "len"

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Monday, June 26, 2023 3:53 PM To: Ju-Zhe Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [PATCH] SCCVN: Fix repeating variable name "len" On

[PATCH v1] RISC-V: Remove duplicated extern function_base decl

From: Pan Li Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.h: Remove duplicated decl. --- gcc/config/riscv/riscv-vector-builtins-bases.h | 5 - 1 file changed, 5 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/conf

[PATCH V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

From: Ju-Zhe Zhong Hi, Richi. It seems that we use nunits which is len + bias to iterate then we can simplify the codes. Also, I fixed behavior of len_store, Before this patch: (len - bias) * BITS_PER_UNIT After this patch: (len + bias) * BITS_PER_UNIT gcc/ChangeLog: * tree-

Re: [PATCH v1] RISC-V: Remove duplicated extern function_base decl

LGTM juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-26 17:36 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Remove duplicated extern function_base decl From: Pan Li Signed-off-by: Pan Li gcc/ChangeLog: * config/

Re: [PATCH v1] RISC-V: Remove duplicated extern function_base decl

Lgtm juzhe.zh...@rivai.ai 於 2023年6月26日 週一，17:40寫道： > LGTM > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-26 17:36 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Remove duplicated extern function_base

[PATCH] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern

From: Ju-Zhe Zhong Hi, Richi and Richard. This patch is adding LEN_MASK_{GATHER_LOAD,SCATTER_STORE} to allow targets handle flow control by mask and loop control by length on gather/scatter memory operations. Consider this following case: #include void f (uint8_t *restrict a, uint8_t *rest

[PATCH] tree-optimization/110392 - ICE with predicate analysis

Feeding not optimized IL can result in predicate normalization to simplify things so a predicate can get true or false. The following re-orders the early exit in that case to come after simplification and normalization to take care of that. Bootstrapped and tested on x86_64-unknown-linux-gnu, pus

RE: [PATCH] RISC-V: Remove redundant vcond patterns

Committed, thanks kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Monday, June 26, 2023 5:08 PM To: Richard Biener Cc: Juzhe-Zhong ; gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com; pal...@rivosinc.com; jeffreya...@gmail

RE: [PATCH v1] RISC-V: Remove duplicated extern function_base decl

Committed, thanks kito and juzhe. Pan From: Kito Cheng Sent: Monday, June 26, 2023 5:51 PM To: juzhe.zh...@rivai.ai Cc: Robin Dapp ; gcc-patches ; jeffreyalaw ; Li, Pan2 ; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Remove duplicated extern function_base decl Lgtm juzhe.zh...@rivai.ai

Re: [PATCH V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, Richi. It seems that we use nunits which is len + bias to iterate then we > can > simplify the codes. > > Also, I fixed behavior of len_store, > > Before this patch: >(len - bias) * BITS_PER_UNIT > After this pa

Re: Re: [PATCH V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

Hi, Richi. I am wondering whether it is true that :? TYPE_VECTOR_SUBPARTS (vectype).to_constant () Thanks. juzhe.zh...@rivai.ai From: Richard Biener Date: 2023-06-26 19:18 To: Ju-Zhe Zhong CC: gcc-patches; richard.sandiford Subject: Re: [PATCH V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE O

Re: Re: [PATCH V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > Hi, Richi. I am wondering whether it is true that :? > > TYPE_VECTOR_SUBPARTS (vectype).to_constant () Not necessarily. > Thanks. > > > juzhe.zh...@rivai.ai > > From: Richard Biener > Date: 2023-06-26 19:18 > To: Ju-Zhe Zhong > CC: gcc-patc

[PATCH] vect: Cost intermediate conversions

g:6f19cf7526168f8 extended N-vector to N-vector conversions to handle cases where an intermediate integer extension or truncation is needed. This patch adjusts the cost to account for these intermediate conversions. Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? Richard gcc/

[PATCH V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

From: Ju-Zhe Zhong Hi, Richi. It seems that we use nunits which is len + bias to iterate then we can simplify the codes. Also, I fixed behavior of len_store, Before this patch: (len - bias) * BITS_PER_UNIT After this patch: (len + bias) * BITS_PER_UNIT gcc/ChangeLog: * tree-

Re: [PATCH V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > From: Ju-Zhe Zhong > > Hi, Richi. It seems that we use nunits which is len + bias to iterate then we > can > simplify the codes. > > Also, I fixed behavior of len_store, > > Before this patch: >(len - bias) * BITS_PER_UNIT > After this pa

Re: Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

No, I don't think we can use first case (vid + vand -npatterns) for base != 0, since the first element value of vid is alway 0. Thanks. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-06-26 15:51 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw S

[PATCH] tree-optimization/110381 - preserve SLP permutation with in-order reductions

The following fixes a bug that manifests itself during fold-left reduction transform in picking not the last scalar def to replace and thus double-counting some elements. But the underlying issue is that we merge a load permutation into the in-order reduction which is of course wrong. Now, reduct

[PATCH V2] RISC-V: Support const vector expansion with step vector with base != 0

Currently, we are able to generate step vector with base == 0: { 0, 0, 2, 2, 4, 4, ... } ASM: vid vand However, we do wrong for step vector with base != 0: { 1, 1, 3, 3, 5, 5, ... } Before this patch, such case will run fail. After this patch, we are able to pass the testcase and generate the

Re: [PATCH] vect: Cost intermediate conversions

On Mon, Jun 26, 2023 at 1:58 PM Richard Sandiford via Gcc-patches wrote: > > g:6f19cf7526168f8 extended N-vector to N-vector conversions > to handle cases where an intermediate integer extension or > truncation is needed. This patch adjusts the cost to account > for these intermediate conversions

Re: Re: [PATCH V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

Hi, Richi. >> I think you can use ordered_min here? Alternatively doing ... I check the function of ordered_min: ordered_min (const poly_int_pod &a, const poly_int_pod &b) { if (known_le (a, b)) return a; else { if (N > 1) gcc_checking_assert (known_le (b, a)); return b

Re: Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

Sure. Sent it: https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622836.html juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-06-26 17:10 To: Robin Dapp CC: Juzhe-Zhong; gcc-patches; kito.cheng; palmer; palmer; jeffreyalaw Subject: Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

[PING] PATCH v5 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

All: Ok for trunk. Please review. Thanks & Regards Ajit On 01/06/23 10:53 am, Ajit Agarwal via Gcc-patches wrote: > Hello All: > > This new version of patch 4 use improve ree pass for rs6000 target using > defined ABI interfaces. > Bootstrapped and regtested on power64-linux-gnu. > > Review

[PING] [PATCH 3/4] ree: Improve functionality of ree pass for rs6000 target.

All: Ok for trunk. Please review. Thanks & Regards Ajit On 07/06/23 3:55 pm, Ajit Agarwal via Gcc-patches wrote: > Hello All: > > This patch provide functionality to improve ree pass for rs6000 target. > Eliminated sign_extend/zero_extend/AND with varying constants. > > Bootstrapped and regtes

Re: PATCH v5 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

All: Ok for trunk. Please review. Thanks & Regards Ajit On 01/06/23 10:53 am, Ajit Agarwal via Gcc-patches wrote: > Hello All: > > This new version of patch 4 use improve ree pass for rs6000 target using > defined ABI interfaces. > Bootstrapped and regtested on power64-linux-gnu. > > Review c

Re: Re: [PATCH V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

On Mon, 26 Jun 2023, juzhe.zh...@rivai.ai wrote: > Hi, Richi. > > >> I think you can use ordered_min here? Alternatively doing ... > > I check the function of ordered_min: > ordered_min (const poly_int_pod &a, const poly_int_pod &b) > { > if (known_le (a, b)) > return a; > else > {

[PING] PATCH v5 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

All: Ok for trunk. Please review. Thanks & Regards Ajit On 26/06/23 6:12 pm, Ajit Agarwal via Gcc-patches wrote: > All: > > Ok for trunk. Please review. > > Thanks & Regards > Ajit > > On 01/06/23 10:53 am, Ajit Agarwal via Gcc-patches wrote: >> Hello All: >> >> This new version of patch 4 us

Re: [PATCH] tree-optimization/110381 - preserve SLP permutation with in-order reductions

Richard Biener writes: > The following fixes a bug that manifests itself during fold-left > reduction transform in picking not the last scalar def to replace > and thus double-counting some elements. But the underlying issue > is that we merge a load permutation into the in-order reduction > whic

Re: [PATCH v6] tree-ssa-sink: Improve code sinking pass

On Sat, Jun 24, 2023 at 6:12 AM Ajit Agarwal wrote: > > Hello All: > > This patch improves code sinking pass to sink statements before call to reduce > register pressure. > Review comments are incorporated. > > For example : > > void bar(); > int j; > void foo(int a, int b, int c, int d, int e, in

Re: Re: [PATCH V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE

Hi，Richi.>> I guess it would be nice to re-formulate the loop in terms of >> the encoded VECTOR_CST elts, but then we need to generate >> the "extents" for set bits, not sure how to do that here. >> Note in the end we get HOST_WIDE_INT extents from adding >> the element size for each mask element w

[PATCH] aarch64: Remove architecture dependencies from intrinsics

Many intrinsics currently depend on both an architecture version and a feature, despite the corresponding instructions being available within GCC at lower architecture versions. LLVM has already removed these explicit architecture version dependences; this patch does the same for GCC, as well as r

Re: [PATCH v3] Add leafy mode for zero-call-used-regs

> On Jun 23, 2023, at 7:27 PM, Alexandre Oliva wrote: > > On Jun 23, 2023, Qing Zhao via Gcc-patches wrote: > >> It’s better to add this definition earlier in the list of the “three >> basic values”, to make it “four basic values”, like the following: > > Oh, my, sorry for being so dense, I

[COMMITTED] PR tree-optimization/110251 - Avoid redundant GORI calcuations.

When calculating ranges, GORI evaluates the chain of definitions until it finds the desired name.   _4 = (short unsigned int) c.2_1;   _5 = _4 + 65535;   a_lsm.19_30 = a;   _49 = _4 + 65534;   _12 = _5 & _49;   _46 = _12 + 65535;   _48 = _12 & _46;    <<--   if (_48 != 0) When evaluatin

RE: [PATCH V2] GIMPLE_FOLD: Fix gimple fold for LEN_{MASK}_{LOAD,STORE}

Committed as passed both the bootstrap and regression test, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Monday, June 26, 2023 4:17 PM To: Ju-Zhe Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [PAT

RE: [PATCH V3] DSE: Add LEN_MASK_STORE analysis into DSE and fix LEN_STORE

Committed as passed both the bootstrap and regression test, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Monday, June 26, 2023 4:15 PM To: Ju-Zhe Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [PAT

[committed] docs: Fix typo

gcc/ChangeLog: * doc/optinfo.texi: Fix "steam" -> "stream". diff --git a/gcc/doc/optinfo.texi b/gcc/doc/optinfo.texi index b91bba7bd10470b17ca5190688beee06ad3b87ab..5e8c97ef118786e68b7e46f3c802154cb9b57b83 100644 --- a/gcc/doc/optinfo.texi +++ b/gcc/doc/optinfo.texi @@ -100,7 +100,7 @@ that o

[PATCH] match.pd: Use element_mode instead of TYPE_MODE.

Hi, this patch changes TYPE_MODE into element_mode in a match.pd simplification. As the simplification can be called with vector types real_can_shorten_arithmetic would ICE in REAL_MODE_FORMAT which expects a scalar mode. Therefore, use element_mode instead of TYPE_MODE. Additionally, check if

Re: [PATCH] Change fma_reassoc_width tuning for ampere1

Philipp Tomsich writes: > Richard, > > OK for backport to GCC-13? Yeah, OK for GCC 13 too. Thanks, Richard > Thanks, > Philipp. > > On Thu, 22 Jun 2023 at 16:18, Richard Sandiford via Gcc-patches > wrote: >> >> Di Zhao OS via Gcc-patches writes: >> > This patch enables reassociation of floati

Re: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

On 6/25/23 12:45, Stefan O'Rear wrote: To clarify: are you proposing to make ra (or t1 in the hypothetical) a fixed register for all functions, or only those heuristically identified as potentially larger than 1MiB? And would this extend to forcing the creation of stack frames for all func

Re: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

LLVM will try to find scratch register even after RA to resolve the long jump issue. so maybe we could consider similar approach? And I guess the most complicate part would be the scratch register is not found, and require spill/reload after RA. Jeff Law via Gcc-patches 於 2023年6月26日 週一，22:31寫道： >

[PATCH] arm: Fix MVE intrinsics support with LTO (PR target/110268)

After the recent MVE intrinsics re-implementation, LTO stopped working because the intrinsics would no longer be defined. The main part of the patch is simple and similar to what we do for AArch64: - call handle_arm_mve_h() from arm_init_mve_builtins to declare the intrinsics when the compiler i

Re: [PATCH] arm: Fix MVE intrinsics support with LTO (PR target/110268)

On Mon, 26 Jun 2023 at 20:33, Christophe Lyon via Gcc-patches wrote: > > After the recent MVE intrinsics re-implementation, LTO stopped working > because the intrinsics would no longer be defined. > > The main part of the patch is simple and similar to what we do for > AArch64: > - call handle_arm

Re: [PATCH] arm: Fix MVE intrinsics support with LTO (PR target/110268)

On Mon, 26 Jun 2023 at 17:30, Prathamesh Kulkarni < prathamesh.kulka...@linaro.org> wrote: > On Mon, 26 Jun 2023 at 20:33, Christophe Lyon via Gcc-patches > wrote: > > > > After the recent MVE intrinsics re-implementation, LTO stopped working > > because the intrinsics would no longer be defined.

[PATCH 1/2] Mid engine setup [SU]ABDL

From: oluade01 This updates vect_recog_abd_pattern to recognize the widening variant of absolute difference (ABDL, ABDL2). gcc/ChangeLog: * internal-fn.cc (widening_fn_p, decomposes_to_hilo_fn_p): Add IFN_VEC_WIDEN_ABD to the switch statement. * internal-fn.def (VEC_WIDE

[PATCH 2/2] AArch64: New RTL for ABDL

From: oluade01 This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_widen_abdl_lo_, vec_widen_abdl_hi_): Expansions for abd vec widen optabs. (aarch64_abdl_insn): VQW based abdl RTL. * confi

Re: [PATCH] Move substitute_and_fold over to use simple_dce_from_worklist

On Sun, Jun 25, 2023 at 10:59 PM Jan-Benedict Glaw wrote: > > Hi Andrew, > > On Fri, 2023-05-05 08:17:19 -0700, Andrew Pinski via Gcc-patches > wrote: > > While looking into a different issue, I noticed that it > > would take until the second forwprop pass to do some > > forward proping and it w

Fix profile of forwardes produced by cd-dce

Hi, compiling the testcase from PR109849 (which uses std:vector based stack to drive a loop) with profile feedbakc leads to profile mismatches introduced by tree-ssa-dce. This is the new code to produce unified forwarder blocks for PHIs. I am not including the testcase itself since checking it fo

Re: [PATCH] Convert ipa_jump_func to use ipa_vr instead of a value_range.

Hi, On Mon, May 22 2023, Aldy Hernandez via Gcc-patches wrote: > This patch converts the ipa_jump_func code to use the type agnostic > ipa_vr suitable for GC instead of value_range which is integer specific. > > I've disabled the range cacheing to simplify the patch for review, but > it is handled

Re: [PATCH] Implement ipa_vr hashing.

Hi, On Mon, May 22 2023, Aldy Hernandez via Gcc-patches wrote: > Implement hashing for ipa_vr. When all is said and done, all these > patches incurr a 7.64% slowdown for ipa-cp, with is entirely covered by > the similar 7% increase in this area last week. So we get type agnostic > ranges with "i

Re: [PATCH] Convert remaining uses of value_range in ipa-*.cc to Value_Range.

Hi, On Mon, May 22 2023, Aldy Hernandez via Gcc-patches wrote: > Minor cleanups to get rid of value_range in IPA. There's only one left, > but it's in the switch code which is integer specific. > > OK? With the same request that... > > gcc/ChangeLog: > > * ipa-cp.cc (decide_whether_versio

[committed] libstdc++: Qualify calls to debug mode helpers

Tested x86_64-linux. Pushed to trunk. -- >8 -- These functions should be qualified to disable unwanted ADL. The overload of __check_singular_aux for safe iterators was previously being found by ADL, because it wasn't declared before __check_singular. Add a declaration so that it can be found by

[committed] libstdc++: Implement P2538R1 ADL-proof std::projected

Tested x86_64-linux. Pushed to trunk. -- >8 -- This was recently approved for C++26, but there's no harm in implementing it unconditionally for C++20 and C++23. As it says in the paper, it doesn't change the meaning of any valid code. It only enables things that were previously ill-formed for que

[committed] libstdc++: Fix std::format for pointers [PR110239]

Tested x86_64-linux. Pushed to trunk. -- >8 -- The formatter for pointers was casting to uint64_t which sign extends a 32-bit pointer and produces a value that won't fit in the provided buffer. Cast to uintptr_t instead. There was also a bug in the __parse_integer helper when converting a wide s

[Committed] IBM zSystems: Assume symbols without explicit alignment to be ok

A change we have committed back in 2015 relies on the backend requested ABI alignment to be applied to ALL symbols by the middle-end. However, this does not appear to be the case for external symbols. With this commit we assume all symbols without explicit alignment to be aligned according to the A

Re: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

On 6/26/23 08:50, Kito Cheng wrote: LLVM will try to find scratch register even after RA to resolve the long jump issue. so maybe we could consider similar approach? And I guess the most complicate part would be the scratch register is not found, and require spill/reload after RA. Right. An

[PATCH][committed] aarch64: Clean up some rounding immediate predicates

Hi all, aarch64_simd_rsra_rnd_imm_vec is now used for more than just RSRA and accepts more than just vectors so rename it to make it more truthful. The aarch64_simd_rshrn_imm_vec is now unused and can be deleted. No behavioural change intended. Bootstrapped and tested on aarch64-none-linux-gnu. P

[PATCH][committed] aarch64: Use instead of in scalar SQRSHRUN pattern

Hi all, In the scalar pattern for SQRSHRUN it's a bit clearer to use DWI instead of V2XWIDE to make it more clear that no vector modes are involved. No behavioural change intended. Bootstrapped and tested on aarch64-none-linux-gnu. Pushing to trunk. Thanks, Kyrill gcc/ChangeLog: * conf

Go patch committed: Support -fgo-importcfg

The gc Go compiler has a -importcfg option that takes a file that provides a mapping from import paths to the files that satisfy those imports. This is used by the go build tool to let the compiler read imported packages directly out of the build cache. Without this option the go build tool has t

Re: [PATCH] Improve DSE to handle stores before __builtin_unreachable ()

Hi, playing with testcases for path isolation and const function, I noticed that we do not seem to even try to isolate out of range array accesses: int a[3]={0,1,2}; test(int i) { if (i > 3) return test2(a[i]); return a[i]; } Here call to test2 is dead, since a[i] will acces

Re: Merge from trunk to gccgo branch

I merged trunk revision 3a39a31b8ae9c6465434aefa657f7fcc86f905c0 to the gccgo branch. Ian

Re: [PATCH] New finish_compare_by_pieces target hook (for x86).

Richard Biener via Gcc-patches writes: > On Sun, Jun 25, 2023 at 7:39 AM Roger Sayle > wrote: >> >> >> On Tue, 13 June 2023 12:02, Richard Biener wrote: >> > On Mon, Jun 12, 2023 at 4:04 PM Roger Sayle >> > wrote: >> > > The following simple test case, from PR 104610, shows that memcmp () >> >

Re: [PATCH] Move substitute_and_fold over to use simple_dce_from_worklist

On Mon, Jun 26, 2023 at 9:13 AM Andrew Pinski wrote: > > On Sun, Jun 25, 2023 at 10:59 PM Jan-Benedict Glaw wrote: > > > > Hi Andrew, > > > > On Fri, 2023-05-05 08:17:19 -0700, Andrew Pinski via Gcc-patches > > wrote: > > > While looking into a different issue, I noticed that it > > > would tak

Re: [PATCH] libstdc++: Synchronize PSTL with upstream

On Wed, May 17, 2023 at 12:32 PM Jonathan Wakely wrote: > -template > - _OutputIterator > -__brick_generate_n(_OutputIterator __first, _Size __count, _Generator > __g, /* is_vector = */ std::true_type) noexcept > +template > > Missing uglification on Size. > > +_RandomAccessIterator > +__brick

[PATCH] RISC-V: Add autovec FP int->float conversion.

Hi, this patch adds the autovec expander for vfcvt.f.x.v and tests for it. In addition, it modifies the zfhmin-1 test so it doesn't scan for "no vectorization" but rather check that we do not emit any (RTL) vector operations (other than float/float conversions) with a VNx..HFmode. Regards Robin

[PATCH] RISC-V: Add autovec FP widening/narrowing.

Hi, this patch adds FP widening and narrowing autovec expanders as well as tests. Conceptually similar to integer extension/truncation, we emulate _Float16 -> double by two vfwcvts and double -> _Float16 by two vfncvts. Optimizations to create widening operations will be added separately. Regar

[PATCH] RISC-V: Add autovect widening/narrowing Integer/FP conversions.

Hi, this patch implements widening and narrowing float-to-int and int-to-float autovec conversions and adds tests. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (2): New expander. (2): Dito. (2): Dito. (2): Dito. * config/riscv/vector-it

Re: [PATCH] Introduce hardbool attribute for C

Hi, Alexandre, > On Jun 23, 2023, at 10:38 PM, Alexandre Oliva wrote: > >> For normal Boolean variables, 0x00 is false, this is a reasonable init >> value with zero-initialization. > > *nod*. I was surprised by zero initialization of (non-hardened) > booleans even when pattern is requested, bu

Re: [PATCH v2 1/3] c++: Track lifetimes in constant evaluation [PR70331, PR96630, PR98675]

On Sun, 25 Jun 2023, Nathaniel Shead wrote: > On Fri, Jun 23, 2023 at 12:43:21PM -0400, Patrick Palka wrote: > > On Wed, 29 Mar 2023, Nathaniel Shead via Gcc-patches wrote: > > > > > This adds rudimentary lifetime tracking in C++ constexpr contexts, > > > allowing the compiler to report errors wi

Re: [PATCH] Move substitute_and_fold over to use simple_dce_from_worklist

On Mon, Jun 26, 2023 at 11:49 AM Andrew Pinski wrote: > > On Mon, Jun 26, 2023 at 9:13 AM Andrew Pinski wrote: > > > > On Sun, Jun 25, 2023 at 10:59 PM Jan-Benedict Glaw > > wrote: > > > > > > Hi Andrew, > > > > > > On Fri, 2023-05-05 08:17:19 -0700, Andrew Pinski via Gcc-patches > > > wrote:

Re: [PATCH 1/2] Mid engine setup [SU]ABDL

Thanks for doing this. Generally looks good, but some comments below. Oluwatamilore Adebayo writes: > From: oluade01 > > This updates vect_recog_abd_pattern to recognize the widening > variant of absolute difference (ABDL, ABDL2). > > gcc/ChangeLog: > > * internal-fn.cc (widening_fn_p, de

Re: [PATCH 2/2] AArch64: New RTL for ABDL

Oluwatamilore Adebayo writes: > From: oluade01 > > This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md > (vec_widen_abdl_lo_, vec_widen_abdl_hi_): > Expansions for abd vec widen optabs. > (aarch64_abdl_in

Re: [PATCH] RISC-V: Add autovec FP int->float conversion.

On 6/26/23 12:58, Robin Dapp wrote: Hi, this patch adds the autovec expander for vfcvt.f.x.v and tests for it. In addition, it modifies the zfhmin-1 test so it doesn't scan for "no vectorization" but rather check that we do not emit any (RTL) vector operations (other than float/float conversi

Re: Re: [PATCH] RISC-V: Add autovec FP int->float conversion.

LGTM too. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-06-27 05:50 To: Robin Dapp; gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai Subject: Re: [PATCH] RISC-V: Add autovec FP int->float conversion. On 6/26/23 12:58, Robin Dapp wrote: > Hi, > > this patch adds the autovec expander

Re: [PATCH] RISC-V: Add autovec FP widening/narrowing.

A comment here: - [(set_attr "type" "vshift") + [(set_attr "type" "vnshift") You should drop this change, otherwise LGTM. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-06-27 02:58 To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw CC: rdapp.gcc Subject: [PATCH] RISC-

Re: [PATCH] RISC-V: Add autovec FP widening/narrowing.

On 6/26/23 12:58, Robin Dapp wrote: Hi, this patch adds FP widening and narrowing autovec expanders as well as tests. Conceptually similar to integer extension/truncation, we emulate _Float16 -> double by two vfwcvts and double -> _Float16 by two vfncvts. Optimizations to create widening op

Re: [PATCH] RISC-V: Add autovect widening/narrowing Integer/FP conversions.

LGTM. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-06-27 02:59 To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw CC: rdapp.gcc Subject: [PATCH] RISC-V: Add autovect widening/narrowing Integer/FP conversions. Hi, this patch implements widening and narrowing float-to-i

Re: [PATCH] RISC-V: Add autovect widening/narrowing Integer/FP conversions.

On 6/26/23 12:59, Robin Dapp wrote: Hi, this patch implements widening and narrowing float-to-int and int-to-float autovec conversions and adds tests. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (2): New expander. (2): Dito. (2): Dito. (

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