From: Juzhe-Zhong
Currently mode switching incorrect codegen for the following case:
void fn (void);
void f (void * in, void *out, int32_t x, int n, int m)
{
for (int i = 0; i < n; i++) {
vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in
On Wed, May 24, 2023 at 11:21 PM Andrew MacLeod via Gcc-patches
wrote:
>
> This patch provide the framework for a gimple-range phi analyzer.
>
> Currently, the primary purpose is to give better initial values for
> members of a "phi group"
>
> a PHI group is defined as a a group of PHI nodes whos
On 3/20/23 07:33, Kewen.Lin wrote:
> Hi,
>
> One of my workmates found there is a warning like:
>
> libgcc/config/rs6000/morestack.S:402: Warning: ignoring
> incorrect section type for .init_array.0
>
> when compiling libgcc/config/rs6000/morestack.S.
>
> Since commit r13-6545 touched
LGTM, just a couple of comment tweaks:
Prathamesh Kulkarni writes:
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index d6fc94015fa..db7ca4c28c3 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -22332,6 +22332,46 @@ aarch64_un
Bootstrap && Regression on X86 passed.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-25 10:58
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V15] VECT: Add decrement IV iteration loop control by variable
amount support
From: Ju-Zhe Zhong
OK, I update the change log and modify a part of format. The attached file is
the new version.
-Original Message-
From: Hongtao Liu
Sent: Thursday, May 25, 2023 11:40 AM
To: Hu, Lin1
Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
ubiz...@gmail.com
Subject: Re: [PATCH] i386: Fix incorrect
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (register_frm): New function.
(DEF_RVV_FRM_ENUM): New macro.
(handle_pragma_vector): Add FRM enum
* config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
(RNE): Ditto.
Some minor nits.
+// There can be only one running at a time.
+static phi_analyzer *phi_analysis_object = NULL;
Shouldn't this be phi_analyzer_object to be more consistent? Similarly
throughout.
+// Create a new phi_group with members BM, initialvalue INIT_VAL, modifier
+// statement MOD,
From: Piotr Trojanek
Aliased parameters, just like parameters by-reference types, can safely
appear in consequences of Exceptional_Cases aspect.
gcc/ada/
* sem_res.adb (Resolve_Entity_Name): Allow aliased parameters; tune
error message.
Tested on x86_64-pc-linux-gnu, committed
From: Piotr Trojanek
Restrict references to formal parameters within the new SPARK aspect
Exceptional_Cases and allow occurrences of 'Old in this aspect.
gcc/ada/
* sem_attr.adb
(Analyze_Attribute_Old_Result): Allow uses of 'Old and 'Result within
the new aspect.
When Load_Unit fails to find the unit or encounters an error, the
Load_Fail procedure is called and an exception is raised, skipping the
restoration of the SPARK/Ghost context stored on procedure entry.
gcc/ada/
* rtsfind.adb (Load_RTU.Restore_SPARK_Context): New.
(Load_RTU): Use
From: Eric Botcazou
In particular, the scope depth of library units is 1 instead of 0.
gcc/ada/
* einfo.ads (Scope_Depth): Fix circular definition.
(Scope_Depth_Value): Fix value for library units.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/einfo.ads | 6
From: Piotr Trojanek
Tune warning about a possibly ineffective assignment to a formal
parameter that happens just before a raise statement.
The warning is now emitted for parameters of all by-copy types and not
just of scalar types (this gives more warnings), but is suppressed for
aliased parame
From: Bob Duff
...caused by moving code here from Atree.
gcc/ada/
* sinfo-utils.adb: Update comment to refer to
New_Node_Debugging_Output.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sinfo-utils.adb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
From: Ronan Desplanques
This patch does not change the behavior of the compiler, but is
intended to improve readability. It seizes an opportunity to move
a variable declaration to a smaller scope, so that it's clearer
that the variable is not used outside of that scope.
gcc/ada/
* sem_c
The error message was wrongly using % instead of & in the format string,
causing the displayed message to refer to incorrect names in some cases.
gcc/ada/
* sem_ch13.adb (Check_Aspect_At_Freeze_Point): fix format string,
use existing local Ident.
Tested on x86_64-pc-linux-gnu, co
From: Ronan Desplanques
This patch improves the way controlling access parameters are
handled in dispatch table wrappers. The constructions of both the
specifications and the bodies of wrappers are modified.
gcc/ada/
* freeze.adb (Build_DTW_Body): Add appropriate type conversions for
This change fixes 2 incorrect handlings of the aspect.
The arguments are now correctly resolved and the aspect is rejected on
non array types.
gcc/ada/
* sem_ch13.adb (Analyze_One_Aspect): Mark Aggregate aspect as
needing delayed resolution and reject the aspect on non-array
From: Piotr Trojanek
Fix minor inconsistencies with the recently added SPARK aspects
Exceptional_Cases and Subprogram_Variant, whose implementation is based
on Contract_Cases.
gcc/ada/
* aspects.ads
(Implementation_Defined_Aspect): Recently added aspects are
implementati
From: Eric Botcazou
It comes from an incorrect node sharing in the expanded tree.
gcc/ada/
* sem_ch3.adb (Find_Type_Of_Object): Copy the object definition when
building the subtype declaration in the case of a spec expression.
Tested on x86_64-pc-linux-gnu, committed on master.
From: Ronan Desplanques
This patch adds documentation to the subprogram Replace_Type in
Sem_Ch3. In particular, references to relevant parts of the Ada
reference manual are added.
gcc/ada/
* sem_ch3.adb (Replace_Type): Add more documentation.
Tested on x86_64-pc-linux-gnu, committed on
From: Bob Duff
...and other (minor) changes.
gcc/ada/
* gen_il-gen-gen_entities.adb (E_Label): Add
Entry_Cancel_Parameter. This is necessary because
Analyze_Implicit_Label_Declaration set the Ekind to E_Label.
Without this change, this field would fail the vanish
The compiler would crash when checking type relation between the
function's return type and the type of the expression used in the return
statement. It would not work if the function's return type is an access
type and the expression is not.
gcc/ada/
* sem_ch6.adb (Analyze_Function_Return
From: Bob Duff
More work-in-progress for changing E_Void checks to the flag.
gcc/ada/
* sem_ch9.adb (Analyze_Protected_Type_Declaration): Set the flag
for protected types.
(Analyze_Single_Protected_Declaration): Likewise, for singleton
protected objects.
From: Piotr Trojanek
Implementation of contract Subprogram_Variant and Exceptional_Cases was
based on the existing code for Contract_Cases, i.e. on the existing
occurrences of Aspect_Contract_Cases, Name_Contract_Cases and
Pragma_Contract_Cases. However, occurrences of "Contract_Cases" itself
in
From: Piotr Trojanek
When determining whether a call to protected function appears within
a pragma expression we can safely stop at the subprogram body.
Cleanup related to recently added support for a new SPARK aspects,
whose implementation was based on Contract_Cases.
gcc/ada/
* sem_u
From: Eric Botcazou
Get_Actual_Subtype can be used to access the Actual_Designated_Subtype of
explicit dereferences with a storage model. As a side effect, this also
handles the case where the prefix of the dereference is a formal parameter.
gcc/ada/
* exp_ch6.adb (Add_Simple_Call_By_Co
From: Piotr Trojanek
Contract Exceptional_Cases allows formal parameters to appear *in*
prefixes of attributes Old, but the code only allowed them to appear
*as* prefixes of those attributes.
For example, we now accetp expressions like "X.all'Old" that were
previously rejected.
gcc/ada/
From: Piotr Trojanek
Cleanup related to improved handling of expression functions in
GNATprove; semantics is unaffected.
gcc/ada/
* sem_ch6.adb (Analyze_Return_Type): Remove unused initial value.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_ch6.adb | 2 +-
1 fi
From: Ronan Desplanques
This patch does not change the behavior of the compiler and is
intended as a readability improvement.
gcc/ada/
* sem_ch3.adb (Replace_Type): Use existing constant wherever
possible.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_ch
From: Piotr Trojanek
Before calling routine In_Entity_Map we checked if the entity map is
present; inside this routine we checked this again.
Code cleanup; semantics is unaffected.
gcc/ada/
* sem_util.adb (Update_New_Entities): Remove redundant check for entity
map being presen
From: Piotr Trojanek
Parameter Scopes_In_EWA_OK of New_Copy_Tree was introduced in 2018 to
deal with expressions-with-actions (EWA) in the build-in-place
machinery. However, after changes made in 2022 it is no longer used by
any caller.
Cleanup related to handling of expression functions in GNAT
From: Piotr Trojanek
Routine Move_Aspects does nothing if its From parameter has no aspects.
There is no need to check this at the call sites.
Code cleanup related to changes in handling of expressions functions in
GNATprove; semantics is unaffected.
gcc/ada/
* par-ch7.adb (P_Package):
From: Eric Botcazou
This decouples the size of the types representing addresses and pointers,
which is Standard'Address_Size, from the size of the memory space, which
is System.Memory_Size (more precisely log2 of it). They are tied through
the definition of System.Address:
type Address is mod
From: Eric Botcazou
Standard'Address_Size is the value provided by the code generator for the
size of pointers, and it is set as the default size of every thin pointer
by the front-end. Now it is documented in the GNAT RM as having the value
of System.Address'Size, which is indeed the case on (c
From: Piotr Trojanek
Trivial mistakes in copied code.
gcc/ada/
* sem_prag.adb (Analyze_Pragma): Fix references to Exceptional_Cases in
code copied from handling of Subprogram_Variant.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_prag.adb | 6 +++---
1 f
From: Bob Duff
We had previously used Ekind = E_Void to indicate that a declaration is
self-hidden. We now use the Is_Not_Self_Hidden flag instead. This allows
us to avoid many "vanishing fields", which are (possibly-latent) bugs,
and we now enable the assertions in Atree that detect such bugs.
From: Javier Miranda
The compiler crashes processing an empty aggregate initializing
a component of a discriminated record type using the Ada 2022
notation (that is, []).
gcc/ada/
* exp_aggr.adb (Build_Record_Aggr_Code): Protect access to
aggregate components when the aggregate
Previous fix stopped the processing of the Aggregate aspect early,
skipping the call to Record_Rep_Item, making later call to
Resolve_Container_Aggregate fail.
Also, the previous fix would not handle correctly the case where the
type is private and the check for non-array type can only be done at
From: Steve Baird
In some common cases, a reference to Some_Type'Some_Streaming_Attribute
causes the needed subprogram to be generated "on demand". If there are
multiple such references (e.g., two calls to Some_Type'Write) then we
want to avoid generating multiple essentially-identical subprogram
From: Piotr Trojanek
Code cleanup; semantics is unaffected.
gcc/ada/
* einfo-utils.adb (Write_Entity_Info): Use procedural Next_Index.
* sem_aggr.adb (Collect_Aggr_Bounds): Reuse local constant.
(Resolve_Null_Array_Aggregate): Use procedural Next_Index.
Tested on x86_64
From: Piotr Trojanek
When creating a copy of a node list we called Copy_Entity for entities
and Copy_Separate_Tree for other nodes. This was unnecessary, because
the Copy_Separate_Tree when called on entities will just do Copy_Entity.
Code cleanup; semantics is unaffected.
gcc/ada/
* a
From: Piotr Trojanek
When determining whether attribute Old is evaluated conditionally, we
must also expect it to appear in the recently added contract
Exceptional_Cases.
gcc/ada/
* sem_util.adb (Determining_Expressions): Fix style; fix layout and
ordering of pragma names; expec
From: Piotr Trojanek
While visiting the AST as part of routine New_Copy_Tree we maintain
an EWA_Level variable in a stack-like fashion. This worked fine for
expression with actions nodes but not for quantified expressions.
gcc/ada/
* sem_util.adb (Visit_Node): Decrement EWA_Level with t
From: Javier Miranda
The compiler does not report warnings on the initialization
of arrays of null-excluding access type components by means
of iterated component association, when the expression
initializing each component is either a conditional
expression or a case expression that may initiali
From: Johannes Kliemann
gcc/ada/
* libgnat/system-vxworks7-ppc-kernel.ads: Enable
Support_Atomic_Primitives.
* libgnat/system-vxworks7-ppc-rtp-smp.ads: Likewise.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/libgnat/system-vxworks7-ppc-kernel.ads | 2
From: Eric Botcazou
Standard_Address is an internal entity that is meant to be a clone of
System.Address built at compilation startup. It needs to be seen as a
bona-fide address by the code generator. For the sake of completeness,
it is also given its modulus, although this does not matter in p
From: Tom Tromey
While experimenting, I introduced a compilation error into xsnamest.
This took a little while to track down because, while the error was in
the log, the build did not stop. This patch changes Make-generated.in
to require a successful build of this program.
gcc/ada/
* M
On Wed, 24 May 2023 at 21:15, Jason Merrill wrote:
> On Wed, May 24, 2023 at 5:00 AM Jonathan Wakely via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
>
>> On Wed, 24 May 2023 at 09:41, Xi Ruoyao wrote:
>>
>> > Wang Lei raised some concerns about Itanium C++ ABI, so let's ask a C++
>> > expert
> > On 5/17/23 03:03, Jin Ma wrote:
> >> For example:
> >> (define_insn "mov_lowpart_sidi2"
> >>[(set (match_operand:SI0 "register_operand" "=r")
> >> (subreg:SI (match_operand:DI 1 "register_operand" " r") 0))]
> >>"TARGET_64BIT"
> >>"mov\t%0,%1")
> >>
> >> (defin
When the last insn1 of BB1 and the first insn2 of BB2 are fusion, insn2 will
clear all dependencies in the function chain_to_prev_insn, resulting in insn2
may mov to any BB, and the program calculation result is wrong.
gcc/ChangeLog:
* sched-deps.cc (sched_macro_fuse_insns): Insns should
> -Original Message-
> From: Hu, Lin1
> Sent: Thursday, May 25, 2023 3:52 PM
> To: Hongtao Liu
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ubiz...@gmail.com
> Subject: RE: [PATCH] i386: Fix incorrect intrinsic signature for AVX512
> s{lli|rai|rli}
>
> OK, I update the change log an
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, May 18, 2023 12:14 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PATCH] aarch64: Implement vector FP absolute compare intrinsics
> with builtins
>
> Hi all,
>
> While optimising some vector math libra
The following makes expand_simple_operations expand POINTER_PLUS_EXPRs
with variable offset when the base is invariant. That will allow
to simplify address differences to offset differences in some cases.
Note the patch doesn't follow the variable off chain as I don't have
a testcase showing that'
Thanks, this looks functionally correct to me. And I agree it handles
the cases that previously needed multiplication.
But I think it regresses code quality when no multiplication was needed.
We can now generate duplicate IVs. Perhaps ivopts would remove the
duplicates, but it might be hard, bec
Hi,
this patch implements the autovec expanders for sign and zero extension
patterns as well as the accompanying truncations. In order to use them
additional mode_attr iterators as well as vectorizer hooks are required.
Using these hooks we can e.g. vectorize with VNx4QImode as base mode
and exte
"Jin Ma" writes:
>> > On 5/17/23 03:03, Jin Ma wrote:
>> >> For example:
>> >> (define_insn "mov_lowpart_sidi2"
>> >>[(set (match_operand:SI0 "register_operand" "=r")
>> >> (subreg:SI (match_operand:DI 1 "register_operand" " r") 0))]
>> >>"TARGET_64BIT"
>> >>"mov\t
Jin Ma writes:
> When the last insn1 of BB1 and the first insn2 of BB2 are fusion, insn2 will
> clear all dependencies in the function chain_to_prev_insn, resulting in insn2
> may mov to any BB, and the program calculation result is wrong.
>
> gcc/ChangeLog:
>
> * sched-deps.cc (sched_macro_
Hi, Robin.
>>+extern bool riscv_v_ext_mode_p (machine_mode mode);
No, we don't need it as global extern.
>> + if (riscv_v_ext_mode_p (vector_mode)
>>+ && multiple_p (BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul),
>>+ GET_MODE_SIZE (element_mode), &min_units))
use riscv_v_ext_vec
From: Naveen H S
This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type simila
From: Naveen H S
This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type simila
From: Naveen H S
This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type simila
From: Naveen H S
This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type simila
From: Naveen H S
This patch adds support scalar_storage_order attribute to C++ front-end.
It treats the opposite order fields similar as the packed fields are
treated such that they will not bind to references.
For arrays, the attributes applies to the inner type rather than the array
type simila
Hi Juzhe,
> use riscv_v_ext_vector_mode_p instead since riscv_v_ext_mode_p includes
> tuple modes.
> You should not use tuple modes in related_mode. Tuple modes will be used in
> array mode target hook and
> used by vec_load_lanes/vec_store_lanes.
Ah, thanks for catching this. Yes, vector_mod
Hi， Richard. Thanks for the comments.
>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
>> || !iv_rgc
>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>> != rgc->max_nscalars_per_iter * rgc->factor))
>> {
>> /* See whether zero-based IV would ever generate
On Thu, 25 May 2023 at 13:04, Richard Sandiford
wrote:
>
> LGTM, just a couple of comment tweaks:
>
> Prathamesh Kulkarni writes:
> > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> > index d6fc94015fa..db7ca4c28c3 100644
> > --- a/gcc/config/aarch64/aarch64.cc
> > ++
On Fri, Apr 28, 2023 at 05:22:52PM -0600, Sandra Loosemore wrote:
> OpenMP 5.0 removed the restriction that multiple collapsed loops must
> be perfectly nested, allowing "intervening code" (including nested
> BLOCKs) before or after each nested loop. In GCC this code is moved
> into the inner loop
--text follows this line--
On May 24, 2023, Richard Biener wrote:
> gimple_fold_builtin_memory_op tries to expand the call to a single
> load plus a single store so we can handle overlaps by first loading
> everything to registers and then storing:
*nod*, that's why I figured we could afford to
On May 25, 2023, "Kewen.Lin" wrote:
> Thanks for fixing, I tested this on ppc64le and ppc64 {-m64,-m32}
> well.
Thanks!
> I think this is for PR101169, could you add it as PR marker?
Nice, will do!
>> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 }
>> } } */
>> +/
Hi,
this patch implements abs2, vneg2 and vnot2 expanders
for integer vector registers and adds tests for them.
v2 is rebased against Juzhe's latest refactoring.
Regards
Robin
gcc/ChangeLog:
* config/riscv/autovec.md (2): Add vneg/vnot.
(abs2): Add.
* config/riscv/risc
Ping.
Thanks,
Kyrill
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 18, 2023 4:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] stor-layout, aarch64: Express SRA intrinsics with
"juzhe.zh...@rivai.ai" writes:
> Hi， Richard. Thanks for the comments.
>
>>> if (!LOOP_VINFO_USING_DECREMENTING_IV_P (loop_vinfo)
>>> || !iv_rgc
>>> || (iv_rgc->max_nscalars_per_iter * iv_rgc->factor
>>> != rgc->max_nscalars_per_iter * rgc->factor))
>>> {
> >> /* See
On Fri, Apr 28, 2023 at 05:22:53PM -0600, Sandra Loosemore wrote:
> OpenMP 5.0 removed the restriction that multiple collapsed loops must
> be perfectly nested, allowing "intervening code" (including nested
> BLOCKs) before or after each nested loop. In GCC this code is moved
> into the inner loop
Current ARC's TLS Local Dynamic model is using two anchors to access
data, namely `.tdata` and `.tbss`. This implementation is unnecessary
complicated. However, the TLS Local Dynamic model has better results
using Global Dynamic model and anchors.
gcc/ChangeLog;
* config/arc/arc.cc (arc_c
Hi Kyrill,
On 23/05/2023 11:14, Kyrylo Tkachov wrote:
> Hi Alex,
> diff --git a/gcc/testsuite/gcc.target/arm/pr109800.c
> b/gcc/testsuite/gcc.target/arm/pr109800.c
> new file mode 100644
> index 000..71d1ede13dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/pr109800.c
> @@ -0,0 +1,
Yeah. I see. Removing it will cause testcase run fail.
Now I found the issue, since you want to store the step in the iv_rgroup.
After I tried, the IR looks correct but create ICE:
0x18c8d41 process_bb
../../../riscv-gcc/gcc/tree-ssa-sccvn.cc:7933
0x18cb6d9 do_rpo_vn_1
../../../ris
On Thu, May 25, 2023 at 8:50 AM Richard Biener
wrote:
>
> On Wed, May 24, 2023 at 8:36 PM Alexander Monakov wrote:
> >
> >
> > On Wed, 24 May 2023, Richard Biener via Gcc-patches wrote:
> >
> > > I’d have to check the ISAs what they actually do here - it of course
> > > depends
> > > on RTL sema
> -Original Message-
> From: Alex Coplan
> Sent: Thursday, May 25, 2023 11:26 AM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
>
> Subject: Re: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
>
> Hi Kyrill,
>
+(define_expand "abs2"
+ [(set (match_operand:VI 0 "register_operand")
+(match_operand:VI 1 "register_operand"))]
+ "TARGET_VECTOR"
+{
+ rtx zero = gen_const_vec_duplicate (mode, GEN_INT (0));
+ machine_mode mask_mode = riscv_vector::get_mask_mode (mode).require ();
+ rtx mask = gen_reg_rt
On Thu, May 25, 2023 at 12:01 PM Alexandre Oliva wrote:
>
> --text follows this line--
> On May 24, 2023, Richard Biener wrote:
>
> > gimple_fold_builtin_memory_op tries to expand the call to a single
> > load plus a single store so we can handle overlaps by first loading
> > everything to regist
The following properly handles pattern matching generated COND_EXPRs
which can still have embedded compares in vectorizable_condition
which will always code generate the masked vector variant. We
were requiring vcond with embedded comparisons instead of also
allowing (as code generated) split comp
On Thu, 25 May 2023, juzhe.zh...@rivai.ai wrote:
> Yeah. I see. Removing it will cause testcase run fail.
> Now I found the issue, since you want to store the step in the iv_rgroup.
>
> After I tried, the IR looks correct but create ICE:
> 0x18c8d41 process_bb
> ../../../riscv-gcc/gcc/tre
On May 25, 2023, Richard Biener wrote:
> I mean we could do what RTL expansion would do later and do
> by-pieces, thus emit multiple loads/stores but not n loads and then
> n stores but interleaved.
That wouldn't help e.g. gcc.dg/memcpy-6.c's fold_move_8, because
MOVE_MAX and MOVE_MAX_PIECES cur
Hi!
On Thu, May 25, 2023 at 07:05:55AM -0300, Alexandre Oliva wrote:
> On May 25, 2023, "Kewen.Lin" wrote:
> > So both lp64 and ilp32 have the same count, could we merge it and
> > remove the selectors?
>
> We could, but... I thought I wouldn't, since they were different
> before, and they're l
On Thu, May 25, 2023 at 1:10 PM Alexandre Oliva wrote:
>
> On May 25, 2023, Richard Biener wrote:
>
> > I mean we could do what RTL expansion would do later and do
> > by-pieces, thus emit multiple loads/stores but not n loads and then
> > n stores but interleaved.
>
> That wouldn't help e.g. gcc
From: Ju-Zhe Zhong
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step" as in your patch.
If rg
Thank you so much for your patience.
Could you take a look at V16 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619652.html
whether it is ok for trunk ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-25 18:19
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
The zero-scratch-regs-3.c comes from below PATCH.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615494.html
Hi Yanzhang,
Could you please help to double check the issue reported by Robin? Aka: "
zero-scratch-regs-3.c seems to FAIL in vcondu but that already happens on
trunk."
Thanks a
MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 with
MVE_5 everywhere in mve.md and removes MVE_6 from iterators.md.
2023-05-25 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_6): Remove.
* config/arm/mve.md: Replace MVE_6 with MVE_5.
---
gcc/confi
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 25, 2023 11:48 AM
> To: Alex Coplan
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
>
> Su
> I think it's logically incorrect. For ABS, you want:
>
> operands[0] = operads[1] > 0 ? operands[1] : (-operands[1])
> So you should do this following sequence:
>
> vmslt v0,v1,0
> vneg v1,v1v0.t (should use Mask undisturbed)
Yes, this is the emitted sequence, but the vsetvli mask is indeed
Propagation of the stack pointer in cprop_hardreg is currenty forbidden
in all cases, due to maybe_mode_change returning NULL. Relax this
restriction and allow propagation when no mode change is requested.
gcc/ChangeLog:
* regcprop.cc (maybe_mode_change): Enable stack pointer propagation.
This pass tries to optimize memory offset calculations by moving them
from add immediate instructions to the memory loads/stores.
For example it can transform this:
addi t4,sp,16
add t2,a6,t4
shl t3,t2,1
ld a2,0(t3)
addi a2,1
sd a2,8(t2)
into the following (one instruction les
Implementation of the new RISC-V optimization pass for memory offset
calculations, documentation and testcases.
gcc/ChangeLog:
* config.gcc: Add riscv-fold-mem-offsets.o to extra_objs.
* config/riscv/riscv-passes.def (INSERT_PASS_AFTER): Schedule a new
pass.
* conf
This looks good to me. Just a couple of very minor cosmetic things:
juzhe.zh...@rivai.ai writes:
> @@ -753,17 +846,35 @@ vect_set_loop_condition_partial_vectors (class loop
> *loop,
> continue;
> }
>
> - /* See whether zero-based IV would ever generate all-false masks
>
On 1/1/1970 8:00 AM, Thomas Koenig wrote:
Hi Lipeng,
May I know any comment or concern on this patch, thanks for your time :)
Thanks for your patience in getting this reviewed.
A few remarks / questions.
Which strategy is used in this implementation, read-preferring or
write-preferring
From: Ju-Zhe Zhong
Fix format for Richard.
This patch is supporting decrement IV by following the flow designed by Richard:
(1) In vect_set_loop_condition_partial_vectors, for the first iteration of:
call vect_set_loop_controls_directly.
(2) vect_set_loop_controls_directly calculates "step
Thanks Richard so much.
I have sent V17 patch for commit (fix format as you suggested).
You don't need to reply that.
I am waiting for Richi's final approval.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-25 20:36
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [P
From: Pan Li
This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.
You can locate more information about ZVFH
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