Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

On 5/15/23 07:16, Jin Ma wrote: > > This patch adds the 'Zfa' extension for riscv, which is based on: > > https://github.com/riscv/riscv-isa-manual/commits/zfb > > > > The binutils-gdb for 'Zfa' extension: > > https://sourceware.org/pipermail/binutils/2023-April/127060.html > > > > What needs spe

Re: [PATCH v4] libgfortran: Replace mutex with rwlock

On 5/9/2023 10:32 AM, Zhu, Lipeng wrote: On 1/1/1970 8:00 AM, Bernhard Reutner-Fischer wrote: On Mon,  8 May 2023 17:44:43 +0800 Lipeng Zhu wrote: This patch try to introduce the rwlock and split the read/write to unit_root tree and unit_cache with rwlock instead of the mutex to increase

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

> This patch would like to align the stdint.h to the stdint-gcc.h for all > the RVV test files. Aka: > > stdint.h => stdint-gcc.h Looks good. Jeff already pre-approved so you can go ahead and install this on the trunk. Regards Robin

RE: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

Got it, thanks, will commit to trunk after pass the rvv test. Pan -Original Message- From: Robin Dapp Sent: Tuesday, May 16, 2023 3:11 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang ; jeffreya...@gmail.com

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. >> But we can't generate (vector) gimple that has undefined behaviour from >> (scalar) gimple that had defined behaviour. So something needs to change. >> Either we need to generate a different sequence, or we need to define >> what the behaviour of len_load/store/etc. are when the l

Re: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

"Li, Pan2" writes: > Kindly ping for this PATCH v3. The patch was sent on Saturday, so this is effectively pinging after one working day in most of Europe and America. That's too soon and comes across as aggressive. I realise you and others are working intensively on this. But in a sense that'

RE: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

Committed, thanks all. Pan -Original Message- From: Li, Pan2 Sent: Tuesday, May 16, 2023 3:17 PM To: Robin Dapp ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang ; jeffreya...@gmail.com Subject: RE: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. For case 2, I come up with this idea: +Case 2 (SLP multiple rgroup): + ... + _38 = (unsigned long) n_12(D); + _39 = _38 * 2; + _40 = MAX_EXPR <_39, 16>; + _41 = _40 - 16; + ... +

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Oh, I am sorry for incorrect typos in the last email, fix typos : Hi, Richard. For case 2, I come up with this idea: +Case 2 (SLP multiple rgroup): + ... + _38 = (unsigned long) n_12(D); + _39 = _38 * 2; + _40 = MAX_EXPR <_39, 16

Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

zfa requires/depend f, it means zfa implies f in current toolchain implementation, could you add that into riscv-common.cc? Also that means zfa is exclusive with Z[FDH]INX. Ref: https://github.com/riscv/riscv-isa-manual/issues/1020 On Tue, May 16, 2023 at 3:06 PM jinma wrote: > > On 5/15/23 07:

RE: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

I see, thanks Richard for reminding. I am sorry I failed to locate anywhere(doc or something else) mentioned such convention about ping, will follow the below convention in future. Pan -Original Message- From: Richard Sandiford Sent: Tuesday, May 16, 2023 3:30 PM To: Li, Pan2 Cc: gcc

Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]

Thanks for your comments, Richard. From: Richard Sandiford Date: Friday, May 12, 2023 at 1:02 AM To: Tejas Belagod Cc: gcc-patches@gcc.gnu.org , Tejas Belagod Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab] Tejas Belagod writes: > From: Tejas Belagod > > This PR optimizes an SV

Re: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

On Tue, 2023-05-16 at 07:55 +, Li, Pan2 via Gcc-patches wrote: > I see, thanks Richard for reminding. I am sorry I failed to locate > anywhere(doc or something else) mentioned such convention about ping, https://gcc.gnu.org/contribute.html suggests two week. > will follow the below convention

RE: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

Got it. Thank you! Pan -Original Message- From: Xi Ruoyao Sent: Tuesday, May 16, 2023 4:04 PM To: Li, Pan2 ; Richard Sandiford Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang ; jeffreya...@gmail.com; rguent...@suse.de Subject: Re: [PATCH v3] Ma

Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

"juzhe.zh...@rivai.ai" writes: > Oh, > I am sorry for incorrect typos in the last email, fix typos : > > Hi, Richard. > For case 2, I come up with this idea: > + Case 2 (SLP multiple rgroup): > + ... > + _38 = (unsigned long) n_12(D); > + _39 = _38 * 2

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. RVV infrastructure in RISC-V backend status: 1. All RVV instructions pattern related to intrinsics are all finished (They will be called not only by intrinsics but also autovec in the future). 2. In case of autovec, we finished len_load/len_store (They are temporary used and will be

Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

"juzhe.zh...@rivai.ai" writes: > Hi, Richard. > > RVV infrastructure in RISC-V backend status: > 1. All RVV instructions pattern related to intrinsics are all finished (They > will be called not only by intrinsics but also autovec in the future). > 2. In case of autovec, we finished len_load/len_

RE: [PATCH] aarch64: Add SVE instruction types

Hi Evandro, I created a new attribute so I didn’t have to extend the “type” attribute that lives in config/arm/types.md. As that attribute and file lives in the arm backend but SVE is AArch64-only I didn’t want to add logic to the arm backend as it’s not truly shared. The granularity has been s

[COMMITTED] ada: Restore proof of System.Arith_Double

From: Yannick Moy Use Assert_And_Cut to simplify proof of second part of the Scaled_Divide. Add intermediate assertions and simplify where necessary. gcc/ada/ * libgnat/s-aridou.adb: (Big3): Remove override made useless. (Lemma_Quot_Rem): Add new lemma and justify it, as

[COMMITTED] ada: Set Loop_Variant assertion policy to Ignore in both

From: Yannick Moy Set Loop_Variant assertion policy to Ignore in both. gcc/ada/ * libgnat/a-strsup.adb: Set assertion policy for Loop_Variant. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/libgnat/a-strsup.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

[COMMITTED] ada: Trivial refactoring in Instantiate_*_Body

Factor out Par_Vis/Install_Parent/Par_Installed in Instantiate_Package_Body and Instantiate_Subprogram_Body. gcc/ada/ * sem_ch12.adb (Instantiate_Package_Body): Simplify if/then/else. (Instantiate_Subprogram_Body): Likewise. Tested on x86_64-pc-linux-gnu, committed on master. --

[COMMITTED] ada: Missing dependency with -gnatc

From: Arnaud Charlet When using -gnatc, dependencies on preprocessor and config files were not recorded. gcc/ada/ * gnat1drv.adb: Ensure all dependencies are recorded even when not generating code. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/gnat1drv.adb |

[COMMITTED] ada: Introduce Cannot_Be_Superflat flag on N_Range nodes

From: Eric Botcazou The support of superflat arrays in the language generates an overhead that the code generator attempts to minimize, but it cannot handle too complex cases and it would be helpful if the front-end could lend a hand. This change introduces the Cannot_Be_Superflat flag on N_Rang

[COMMITTED] ada: Simplify dramatically ghost code for proof of System.Arith_Double

From: Yannick Moy Using Inline_For_Proof annotation on key expression functions makes it possible to remove hundreds of lines of ghost code that were previously needed to guide provers. gcc/ada/ * libgnat/s-aridou.adb (Big3, Is_Mult_Decomposition) (Is_Scaled_Mult_Decomposition):

[COMMITTED] ada: Add intermediate assertions for proof of Super_Tail

From: Yannick Moy Proof of Superbounded internal unit requires a little more help. gcc/ada/ * libgnat/a-strsup.adb: Add intermediate assertions. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/libgnat/a-strsup.adb | 6 ++ 1 file changed, 6 insertions(+) diff --gi

[COMMITTED] ada: Fix Ada representation of r_debug and link_map types

Both record types need to have their components 'aliased' to match their C version. The mismatch could be observed when using LTO: warning: type of 'r_debug' does not match original declaration [-Wlto-type-mismatch] /usr/include/link.h:66:23: note: type 'struct r_debug' should match

[COMMITTED] ada: Get name from entity if that's what's passed to Subprogram_Name

From: Richard Kenner gcc/ada/ * sem_util.adb (Subprogram_Name): If what's passed is already an entity, use that for the name. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/sem_util.adb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/ada/sem_util.ad

[COMMITTED] ada: Change Present_Expr field type to Uint

From: Richard Kenner We want the field to be initialized to No_Uint because we want to be able to test in GNAT LLVM whether we've already set it so we can be sure we only set it once. gcc/ada/ * gen_il-gen-gen_nodes.adb (Present_Expr): Type is now Uint. Tested on x86_64-pc-linux-gnu, c

[COMMITTED] ada: Implement inheritance of user-defined literal aspects for untagged types

From: Eric Botcazou In Ada 2022, user-defined literal aspects are nonoverridable but the named subprograms present in them can be overridden, including for untagged types. gcc/ada/ * sem_res.adb (Has_Applicable_User_Defined_Literal): Apply the same processing for derived untagge

[COMMITTED] ada: Fix typo in "pattern"

From: Tom Tromey I found a couple of spots using the typo "patterm" rather than the correct "pattern". gcc/ada/ * doc/gnat_ugn/building_executable_programs_with_gnat.rst (Switches_for_gnatbind): Fix typo. * libgnat/g-spipat.ads: Fix typo. * gnat_ugn.texi: Regener

[COMMITTED] ada: Add tags on style messages

From: Arnaud Charlet Similar to tags on warnings [-gnatwx], we add tags on style messages [-gnatyx] when -gnatw.d is enabled. gcc/ada/ * errout.ads: Update comment. * errout.adb (Skip_Msg_Insertion_Warning): Update to take e.g. -gnatyM into account. * erroutc.adb

[COMMITTED] ada: Bad handling of ASCII with -gnatyn

From: Arnaud Charlet ASCII is special cased but this wasn't taking into account all cases such as Standard.ASCII. gcc/ada/ * snames.ads-tmpl (Name_ASCII): New. * style.adb (Check_Identifier): Fix handling of ASCII. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/a

[COMMITTED] ada: Fix missing warning on aggregate with iterated component

From: Eric Botcazou This happens when the iterated component does not really iterate. gcc/ada/ * exp_aggr.adb (Expand_Array_Aggregate): Do not set Warnings_Off on the temporary created when in-place expansion is not possible. Tested on x86_64-pc-linux-gnu, committed on master.

[COMMITTED] ada: Enable Support_Atomic_Primitives on PPC Linux

From: Johannes Kliemann gcc/ada/ * libgnat/system-linux-ppc.ads: Add Support_Atomic_Primitives. * libgnat/s-atopri__32.ads: Add 32 bit version of s-atopri.ads. * Makefile.rtl: Use s-atopro__32.ads for ppc-linux. Tested on x86_64-pc-linux-gnu, committed on master. --- g

[COMMITTED] ada: usage.adb: document -gnatyD switch

From: Ghjuvan Lacambre -gnatyD was documented in the user guide but not in `gnat --help-ada`. gcc/ada/ * usage.adb (Usage): Document -gnatyD. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/usage.adb | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/ada/usage.ad

[COMMITTED] ada: Document examples of No_Dependence restriction for code generation

From: Eric Botcazou gcc/ada/ * doc/gnat_rm/standard_and_implementation_defined_restrictions.rst (No_Dependence): Give examples of new No_Dependence restrictions. * gnat_rm.texi: Regenerate. Tested on x86_64-pc-linux-gnu, committed on master. --- ...nd_implementation_de

[COMMITTED] ada: Apply range checks to preanalyzed aggregate expressions

From: Piotr Trojanek When preanalyzing expressions in GNATprove mode, e.g. Pre/Post contracts, we apply checks, because these expressions will never be expanded. This didn't happen for aggregate expressions, most likely because of an oversight. gcc/ada/ * sem_util.adb (Aggregate_Constra

[COMMITTED] ada: Spurious error analyzing 'old or 'result in class-wide conditions

From: Javier Miranda gcc/ada/ * sem_attr.adb (Analyze_Attribute_Old_Result): When preanalyzing a class-wide condition, search in the scopes stack for the subprogram that has the condition. This is required because returning the current scope causes reporti

[COMMITTED] ada: Build invariant procedure while freezing in GNATprove mode

From: Piotr Trojanek Invariant procedure bodies are created either by expansion of freezing nodes (but only in ordinary compilation mode) or at the end of package private declarations (but not for with private types in the type derivation chain). In GNATprove mode we didn't create invariant proc

[COMMITTED] ada: Spurious error on function returning CPP type

From: Javier Miranda gcc/ada/ * exp_ch6.adb (Needs_BIP_Alloc_Form): Return False for functions with foreign convention since we never use build-in-place for such functions. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/exp_ch6.adb | 7 ++- 1 file

[COMMITTED] ada: Use accumulator type in expansion of 'Reduce attribute

From: Eric Botcazou The current expansion of the 'Reduce attribute uses the resolution type of the expression for the accumulator. Now this type can be unresolved or set to a universal type, for example if it is itself the prefix of the 'Image attribute, and this may yield a spurious type mismatc

[COMMITTED] ada: Adjust semantics and implementation of storage models

From: Eric Botcazou This makes the following adjustments to the semantics and implementation of storage models in the compiler: 1. By-copy semantics in subprogram calls: when an object accessed with a nonnative storage model is passed as an actual parameter in a call to a subprogram,

[COMMITTED] ada: Fix internal error on chain of predicated record types

From: Eric Botcazou The preanalysis of a predicate set on one of the record types was causing premature freezing of another record type. gcc/ada/ * sem_ch13.adb: Add with and use clauses for Expander. (Resolve_Aspect_Expressions) : Emulate a bona-fide preanalysis setup b

Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]

Tejas Belagod writes: >> + { >> +int i; >> +int nelts = vector_cst_encoded_nelts (v); >> +int first_el = 0; >> + >> +for (i = first_el; i < nelts; i += step) >> + if (VECTOR_CST_ENCODED_ELT (v, i) != VECTOR_CST_ENCODED_ELT (v, > first_el)) > > I think this should use !operand

[COMMITTED] ada: Follow-up improvement to implementation of storage models

From: Eric Botcazou It avoids to recreate an actual subtype for an explicit dereference. gcc/ada/ * sem_util.adb (Get_Actual_Subtype): For an explicit dereference, return the Actual_Designated_Subtype if it is present. (Get_Actual_Subtype_If_Available): Likewise. Tested

[COMMITTED] ada: Add "gnat --help-ada" text for new switches.

From: Steve Baird The output generated by "gnat --help-ada" should include descriptions for the newly added -gnatw_s and -gnatw_S switches". gcc/ada/ * usage.adb: Generate output text describing the -gnatw_s switch (and the corresponding -gnatw_S switch). Tested on x86_64-pc-li

[COMMITTED] ada: Update proof of runtime units

From: Yannick Moy Following changes in GNATprove, proofs need to be amended. gcc/ada/ * libgnat/s-aridou.adb (Lemma_Div_Pow2): Add assertion. * libgnat/s-arit32.adb (Lemma_Abs_Div_Commutation): Simplify. * libgnat/s-expmod.adb (Lemma_Exp_Mod): Add assertions. (Le

[COMMITTED] ada: Fix internal error on 'Image applied to array component

From: Eric Botcazou This happens because the array component depends on a discriminant. gcc/ada/ * exp_imgv.adb (Rewrite_Object_Image): If the prefix is a component that depends on a discriminant, create an actual subtype for it. Tested on x86_64-pc-linux-gnu, committed on mast

[COMMITTED] ada: Fix crash on iterated component in expression function

From: Eric Botcazou The problem is that the freeze node generated for the type of a static subexpression present in the expression function is incorrectly placed inside instead of outside the function. gcc/ada/ * freeze.adb (Freeze_Expression): When the freezing is to be done ou

[patch,avr] PR105753: Fix ICE in add_clobbers.

This patch removes the superfluous parallel in [u]divmod patterns in the AVR backend. Effect of extra parallel is that add_clobbers reaches gcc_unreachable() because the clobbers for [u]divmod are missing. The parallel around the parts of an insn pattern is implicit if it has multiple parts like

[committed] libstdc++: Do not use pthread_mutex_clocklock with ThreadSanitizer

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- As noted in https://github.com/llvm/llvm-project/issues/62623 there are no tsan interceptors for some of the new POSIX-1:202x APIs added by https://austingroupbugs.net/view.php?id=1216 so tsan gives false positive warnings for try_lock_for on ti

[committed] libstdc++: Require tzdb support for chrono::zoned_time printer test

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * testsuite/libstdc++-prettyprinters/chrono.cc: Only test printer for chrono::zoned_time for cx11 ABI and tzdb effective target. --- libstdc++-v3/testsuite/libstdc++-prettyprinters/chrono.cc | 3

[committed] libstdc++: Add assertion to debug_allocator test

Tested x86_64-linux. Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * testsuite/ext/debug_allocator/check_deallocate_null.cc: Add assertion to ensure expected exception is throw. --- .../testsuite/ext/debug_allocator/check_deallocate_null.cc | 3 ++- 1 file changed, 2 ins

Re: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

pan2...@intel.com writes: > diff --git a/gcc/rtl-ssa/accesses.h b/gcc/rtl-ssa/accesses.h > index c5180b9308a..38b4d6160c2 100644 > --- a/gcc/rtl-ssa/accesses.h > +++ b/gcc/rtl-ssa/accesses.h > @@ -254,7 +254,7 @@ private: >unsigned int m_spare : 2; > >// The value returned by the accessor

[committed 1/3] libstdc++: Stop using _GLIBCXX_USE_C99_COMPLEX_TR1 in

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- The _GLIBCXX_USE_C99_COMPLEX_TR1 macro (and the comments about it in acinclude.m4 and config.h) are misleading when it is also used for , not only . It is also wrong, because the configure checks for TR1 use -std=c++98 and a target might define

[committed 3/3] libstdc++: Stop using TR1 macros in and

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- As with the two commits before this, the _GLIBCXX_USE_C99_CTYPE_TR1 and _GLIBCXX_USE_C99_FENV_TR1 macros are misleading when they are also used for and , not only for TR1 headers. It is also wrong, because the configure checks for TR1 use -std=

[committed 2/3] libstdc++: Stop using _GLIBCXX_USE_C99_STDINT_TR1 in

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- The _GLIBCXX_USE_C99_STDINT_TR1 macro (and the comments about it in acinclude.m4 and config.h) are misleading when it is also used for , not only . It is also wrong, because the configure checks for TR1 use -std=c++98 and a target might define u

[PATCH V10] VECT: Add decrement IV support in Loop Vectorizer

From: Ju-Zhe Zhong This patch implement decrement IV for length approach in loop control. Address comment from kewen that incorporate the implementation inside "vect_set_loop_controls_directly" instead of a standalone function. Address comment from Richard using MIN_EXPR to handle these 3 follo

Re: [PATCH] Add auto-resizing capability to irange's [PR109695]

On 5/15/23 20:14, Aldy Hernandez wrote: On 5/15/23 17:07, Aldy Hernandez wrote: On 5/15/23 12:42, Jakub Jelinek wrote: On Mon, May 15, 2023 at 12:35:23PM +0200, Aldy Hernandez wrote: gcc/ChangeLog: PR tree-optimization/109695 * value-range.cc (irange::operator=): Resize range.    

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. I have sent V10: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618718.html I can't combine implementation Case 2 and Case 3, Case 2 each control (len) are coming from same rgc. But Case 3 each control (len) are coming coming from different rgc. Can you help me with that ? Also,

Re: [PATCH 0/7] openmp: OpenMP 5.1 loop transformation directives

Hi Jakub, On 15.05.23 12:19, Jakub Jelinek wrote: On Fri, Mar 24, 2023 at 04:30:38PM +0100, Frederik Harwath wrote: this patch series implements the OpenMP 5.1 "unroll" and "tile" constructs. It includes changes to the C,C++, and Fortran front end for parsing the new constructs and a new middl

[PATCH V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics

From: Juzhe-Zhong This patch is adding rounding mode operand and FRM_REGNUM dependency into floating-point instructions. The floating-point instructions we added FRM and rounding mode operand: 1. vfadd/vfsub 2. vfwadd/vfwsub 3. vfmul 4. vfdiv 5. vfwmul 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac 7. vfs

[PATCH V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics

From: Juzhe-Zhong This patch is adding rounding mode operand and FRM_REGNUM dependency into floating-point instructions. The floating-point instructions we added FRM and rounding mode operand: 1. vfadd/vfsub 2. vfwadd/vfwsub 3. vfmul 4. vfdiv 5. vfwmul 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac 7. vfs

[PATCH V11] VECT: Add decrement IV support in Loop Vectorizer

From: Ju-Zhe Zhong This patch implement decrement IV for length approach in loop control. Address comment from kewen that incorporate the implementation inside "vect_set_loop_controls_directly" instead of a standalone function. Address comment from Richard using MIN_EXPR to handle these 3 follo

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard and Richi. I am so sorry for sending you garbage patches (My mistake, sending RISC-V patches to you). I finally realize that Case 2 and Case 3 are totally the same sequence! I have combined them into single function called "vect_adjust_loop_lens_control" I have sent V11 patch: https:

[PATCH] aarch64: Allow moves after tied-register intrinsics (2nd edition)

I missed these two in g:4ff89f10ca0d41f9cfa76 because I was testing on a system that didn't support big-endian compilation. Testing on aarch64_be-elf shows no other related failures (although the overall results are worse than for little-endian). Tested on aarch64_be-elf & pushed. Richard gcc/t

Re: [PATCH 0/7] openmp: OpenMP 5.1 loop transformation directives

On Tue, May 16, 2023 at 11:45:16AM +0200, Frederik Harwath wrote: > The place where different compilers implement the loop transformations > was discussed in an OpenMP loop transformation meeting last year. Two > compilers (another one and GCC with this patch series) transformed the loops > in the

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. Forget about V10 patch. Just go directly V11 patch. I am so sorry that I send V10 since I originally did not notice Case 2 and Case 3 are totally the same. I apologize for that. I have reviewed V11 patch twice, it seems that this patch is much more reasonable and better understanding

Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]

From: Richard Sandiford Date: Tuesday, May 16, 2023 at 2:15 PM To: Tejas Belagod Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab] Tejas Belagod writes: >> + { >> +int i; >> +int nelts = vector_cst_encoded_nelts (v); >> +int first_el = 0; >>

Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]

Tejas Belagod writes: >>> + { >>> + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val, >>> + bitsize_int (step * BITS_PER_UNIT), >>> + bitsize_int ((16 - step) * BITS_PER_UNIT)); >>> + >>> + return gimple_build_assign (f.lhs, b); >>> +

RE: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

Thanks Richard Sandiford for review. Yes, currently the class access_info will be extended from 8 bytes to 12 bytes, which is missed in the table. With the adjustment as you suggested it will be 8 bytes but unfortunately the change of m_kind may trigger some ICE in some test case(s). I will ta

Re: [PATCH] rtl: AArch64: New RTL for ABD

Sorry for the slow reply. Oluwatamilore Adebayo writes: > From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001 > From: oluade01 > Date: Fri, 14 Apr 2023 15:10:07 +0100 > Subject: [PATCH 2/4] AArch64: New RTL for ABD > > This patch adds new RTL and tests for sabd and uabd > > PR

Re: [PATCH v4 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

On 29/04/23 5:03 am, Jeff Law wrote: > > > On 4/28/23 16:42, Hans-Peter Nilsson wrote: >> On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote: >> >>> Hello All: >>> >>> This new version of patch 4 use improve ree pass for rs6000 target using >>> defined ABI interfaces. >>> Bootstrapped an

[GCC12 backport] arm: MVE testsuite and backend bugfixes

Hi all, We've recently sent up a lot of patches overhauling the testsuite of the Arm MVE backend. With these changes, we've also identified and fixed a number of bugs (some backend bugs and many to do with the polymorphism of intrinsics in MVE the header file). These would all be relevant to

Re: [PATCH] RFC: New compact syntax for insn and insn_split in Machine Descriptions

On 24/04/2023 09:33, Richard Sandiford via Gcc-patches wrote: Richard Sandiford writes: Tamar Christina writes: Hi All, This patch adds support for a compact syntax for specifying constraints in instruction patterns. Credit for the idea goes to Richard Earnshaw. I am sending up this RFC to

Remove stale Autoconf checks for Perl

Hi! OK to push the attached "Remove stale Autoconf checks for Perl"? For avoidance of doubt, there still exist a few instances of Perl usage in the GCC build process (like, when 'contrib/make_sunver.pl' is used), but those always directly invoke 'perl'. As this, apparently, is working fine, I'm

Support parallel testing in libgomp: fallback Perl 'flock' [PR66005]

Hi! On 2023-05-05T10:59:31+0200, I wrote: > On 2023-05-05T10:55:41+0200, I wrote: >> [Putting Bernhard, Honza, Segher in CC, as they are eager to test this, >> based on recent comments on IRC.] ;-P >> First, establish the parallel testing infrastructure -- while still >> hard-coding the number

[PATCH] OpenMP: Array shaping operator and strided "target update" for C

Following the similar support for C++ and Fortran, here is the C implementation for the OpenMP 5.0 array-shaping operator, and for strided and rectangular updates for "target update" directives. Much of the implementation is shared with the previously-posted C++ support: https://gcc.gnu.org/pip

Re: [PATCH v5 1/4] rs6000: Enable REE pass by default

Hi! On Tue, May 16, 2023 at 11:45:28AM +0530, Ajit Agarwal wrote: > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -12455,8 +12455,8 @@ Attempt to remove redundant extension instructions. > This is especially > helpful for the x86-64 architecture, which implicitly zero-extends in 64

Re: [PATCH] configure: Implement --enable-host-pie

Ping. On Tue, May 09, 2023 at 03:41:58PM -0400, Marek Polacek via Gcc-patches wrote: > [ This is my third attempt to add this configure option. The first > version was approved but it came too late in the development cycle. > The second version was also approved, but I had to revert it: >

[committed] RISC-V: Fix wrong select_kind in riscv_compute_multilib

Seems like I screw up bare-metal toolchian multi lib selection during finxing linux multi-lib selction... gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix wrong select_kind... --- gcc/common/config/riscv/riscv-common.cc | 6 +++--- 1 file changed

[PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits

From: Pan Li We are running out of the machine_mode(8 bits) in RISC-V backend. Thus we would like to extend the machine_mode bit size from 8 to 16 bits. However, it is sensitive to extend the memory size in common structure like tree or rtx. This patch would like to extend the machine_mode bits t

[PATCH] configure: Implement --enable-host-bind-now

As promised in the --enable-host-pie patch, this patch adds another configure option, --enable-host-bind-now, which adds -z now when linking the compiler executables in order to extend hardening. BIND_NOW with RELRO allows the GOT to be marked RO; this prevents GOT modification attacks. This opti

[PATCH] c++: desig init in presence of list ctor [PR109871]

add_list_candidates has logic to reject designated initialization of a non-aggregate type, but this is inadvertendly being suppressed if the type has a list constructor due to the order of case analysis, which in the below testcase leads to us incorrectly treating the list initializer as an ordinar

RE: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

Update the PATCH v4 (I am sorry, missed the v4 in subject) as below with x86 bootstrap test passed. https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618742.html Pan -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Tuesday, May 16, 2023 8:17 PM To: Ric

Re: [PATCH] c++: desig init in presence of list ctor [PR109871]

On 5/16/23 11:38, Patrick Palka wrote: add_list_candidates has logic to reject designated initialization of a non-aggregate type, but this is inadvertendly being suppressed if the type has a list constructor due to the order of case analysis, which in the below testcase leads to us incorrectly tr

[committed gcc13 backport] RISCV: Inline subword atomic ops

On 5/15/23 21:32, Jeff Law wrote: On 5/9/23 10:01, Patrick O'Neill wrote: Ping. OK for backporting.  Sorry for the delay. jeff Committed. Thanks, Patrick

[committed] rs6000: Enable REE pass by default

rs6000: Enable REE pass by default Add ree pass as a default pass for rs6000 target for O2 and above. 2023-05-16 Ajit Kumar Agarwal gcc/ChangeLog: * common/config/rs6000/rs6000-common.cc: Add REE pass as a default rs6000 target pass for O2 and above. * doc/invoke.texi

[PATCH] libstdc++: Disable embedded tzdata for all 16-bit targets

Tested powerpc64le-linux. Builds OK for avr too. Roger, does this work for xstormy16? -- >8 -- libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Extend logic for avr and msp430 to all 16-bit targets. * configure: Regenerate. --- libstdc++-v3/acinclude.m4 |

[committed] libstdc++: Disable cacheline alignment for DJGPP [PR109741]

Tested powerpc64le-linux. Builds OK on djgpp too. Pushed to trunk. -- >8 -- DJGPP (and maybe other targets) uses MAX_OFILE_ALIGNMENT=16 which means that globals (and static objects) can't have alignment greater than 16. This causes an error for the locks defined in src/c++11/shared_ptr.cc becaus

[PATCH] c++: -Wdangling-reference not suppressed in template [PR109774]

In check_return_expr, we suppress the -Wdangling-reference warning when we're sure it would be a false positive. It wasn't working in a template, though, because the suppress_warning call was never reached. Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk and 13.2? PR c++/1097

[PATCH] c++: Don't try to initialize zero width bitfields in zero initialization [PR109868]

Hi! My GCC 12 change to avoid removing zero-sized bitfields as they are important for ABI and are needed for layout compatibility traits apparently causes zero sized bitfields to be initialized in the IL, which at least in 13+ results in ICEs in the ranger which is upset about zero precision types

Re: [PATCH] c++: -Wdangling-reference not suppressed in template [PR109774]

On 5/16/23 15:13, Marek Polacek wrote: In check_return_expr, we suppress the -Wdangling-reference warning when we're sure it would be a false positive. It wasn't working in a template, though, because the suppress_warning call was never reached. Bootstrapped/regtested on x86_64-pc-linux-gnu, ok

Re: [PATCH] c++: Don't try to initialize zero width bitfields in zero initialization [PR109868]

On 5/16/23 15:34, Jakub Jelinek wrote: Hi! My GCC 12 change to avoid removing zero-sized bitfields as they are important for ABI and are needed for layout compatibility traits apparently causes zero sized bitfields to be initialized in the IL, which at least in 13+ results in ICEs in the ranger

Re: [PATCH] s390: Implement TARGET_ATOMIC_ALIGN_FOR_MODE

On 5/16/23 08:43, Stefan Schulze Frielinghaus wrote: > So far atomic objects are aligned according to their default alignment. > For 128 bit scalar types like int128 or long double this results in an > 8 byte alignment which is wrong and must be 16 byte. > > libstdc++ already computes a correct al

Re: [PATCH] configure: Implement --enable-host-pie

Hi Marek, > On 16 May 2023, at 16:29, Marek Polacek via Gcc-patches > wrote: > > Ping. I’m trying this on Darwin (since I have a local patch to do this for modern [darwin20+] versions, which do not allow non-PIE) I think you are missing a hunk to deal with Ada. thanks for the patch Iain >

Re: [PATCH] aarch64: Add SVE instruction types

Hi, Kyrill. It makes sense. I could add the classification to a different attribute as you did and keep it in aarch64 as well. I took the same approach, gleaning over several optimization guides for Arm processors supporting SVE and figuring out the smallest number of types that could cover m

RISC-V Test Errors and Failures

A few of us were talking about test-related issues in the patchwork meeting this morning. I bumped to trunk and did a full rebuild, I'm getting the following (it's in riscv-systems-ci/riscv-gnu-toolchain). This is about what I remember seeing last time I ran the tests, which was a week or so ago

[committed] c: Remove restrictions on declarations in 'for' loops for C2X

C2X removes a restriction that the only declarations in the declaration part of a 'for' loop are declarations of objects with storage class auto or register. Implement this change, making the diagnostics into pedwarn_c11 calls instead of errors (as usual for features added in a new standard versio

Re: RISC-V Test Errors and Failures

On 5/16/23 16:06, Palmer Dabbelt wrote: A few of us were talking about test-related issues in the patchwork meeting this morning.  I bumped to trunk and did a full rebuild, I'm getting the following (it's in riscv-systems-ci/riscv-gnu-toolchain).  This is about what I remember seeing last time

  1   2   >