We would like users to explicitly set that, so that implication rule
won't screw anything up or unexpect -mabi, that's kind of the
conclusion of most RISC-V GCC maintainers (Palmer/Jim Willsom/me).
Also the behavior is there for years, we don't want to make surprise
to user for the behavior change
Hi!
On 2014-11-04T10:31:37-0800, Mike Stump wrote:
> On Nov 4, 2014, at 4:13 AM, Thomas Schwinge wrote:
>> On Wed, 15 Oct 2014 17:46:48 +0200, I wrote:
>>> [...]
>>>
>>> Am I on the right track with the following?
>>
>> Nobody commented, which also means nobody disagreed
>
> :-)
>
>> OK to commi
Hi Fei,
Sorry for the late reply, I've been busy with moving these days :(.
Thanks for working on it. I would prefer removing the extra pass for popretz if
possible ... I will test your patches ASAP.
BR,
Sinan
--
Sender:Fei Gao
Sent
pan2...@intel.com writes:
> From: Pan Li
>
> We are running out of the machine_mode(8 bits) in RISC-V backend. Thus
> we would like to extend the machine mode bit size from 8 to 16 bits.
> However, it is sensitive to extend the memory size in common structure
> like tree or rtx. This patch would l
Hi!
The cleanup is done, now turn ourselves to the changes proper re PR91884
"libgomp testsuite: (not) using a specific driver for C++, Fortran":
On 2014-11-04T10:31:37-0800, Mike Stump wrote:
> On Nov 4, 2014, at 4:13 AM, Thomas Schwinge wrote:
>> On Wed, 15 Oct 2014 17:46:48 +0200, I wrote:
>
Hi!
On 2023-05-12T10:27:29+0200, I wrote:
> The cleanup is done, now turn ourselves to the changes proper re PR91884
> "libgomp testsuite: (not) using a specific driver for C++, Fortran":
>
> On 2014-11-04T10:31:37-0800, Mike Stump wrote:
>> On Nov 4, 2014, at 4:13 AM, Thomas Schwinge wrote:
>>>
WTF?
../../gcc/common/config/riscv/riscv-common.cc: In function 'const char*
riscv_select_multilib_by_abi(const std::string&, const std::string&, const
riscv_subset_list*, const switchstr*, int, const
std::vector&)':
../../gcc/common/config/riscv/riscv-common.cc:1599:22: error: unused parameter
>> After update local codebase to the trunk. I realize there is one more fail
>> in RV32.
>> After this patch, all fails of RVV are cleaned up.
>> Thanks.
But only because we build vmv-imm with autovec-preference=scalable. With
fixed-vlmax
it still does not work because I messed up the rebase a
Hi, Kito and Jiawei
I have noticed several comments are not accurate or no longer valid(e.g. only
for zc 0.5) and they need an update or improvement.
> +
>> +namespace {
>> +
>> +/*
>> + 1. preprocessing:
>> + 1.1. if there is no push rtx, then just return. e.g.
>> + (note 5 1 22 2 [bb 2] NOTE_INS
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi):
Drop unused parameter.
(riscv_select_multilib): Ditto.
(riscv_compute_multilib): Update call site of
riscv_select_multilib_by_abi and riscv_select_multilib_by_abi.
---
gcc/
Apologize for that...
fixed on top of trunk:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=7a7f6b26259d22115ee4813ce130622ad1073d16
On Fri, May 12, 2023 at 4:36 PM Andreas Schwab wrote:
>
> WTF?
>
> ../../gcc/common/config/riscv/riscv-common.cc: In function 'const char*
> riscv_select_multilib_
> ISTR there were no sufficient comments in the code explaining why
> rewrite_expr_tree_parallel_for_fma is better by design. In fact ...
>
> >
> > >
> > > > if (!reassoc_insert_powi_p
> > > > - && ops.length () > 3
> > > > + && len > 3
>
Before implementing Zcmp, I did some optimizations and restructures to
save-restore.
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a5b2a3bff8152aa34408d8ce40add82f4d22ff87
https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=60524be1e3929d83e15fceac6e2aa053c8a6fb20
https://gcc.gnu.org/git/?p=gcc.git;
Zcmp can share the same logic as save-restore in stack allocation:
pre-allocation
by cm.push, step 1 and step 2.
please be noted cm.push pushes ra, s0-s11 in reverse order than what
save-restore does.
So adaption has been done in .cfi directives in my patch.
gcc/ChangeLog:
* config/ris
On 2023-05-12 16:12 Sinan wrote:
>
>Hi Fei,
>Sorry for the late reply, I've been busy with moving these days :(.
>Thanks for working on it. I would prefer removing the extra pass for popretz
>if possible ... I will test your patches ASAP.
>BR,
>Sinan
hi Sinan
I posted V2 based on Kito's comme
vec_init is auto-vectorization pattern.
The test is not loop since using vector type is easier to test the patterns.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-12 16:53
To: Li, Pan2; Kito Cheng; juzhe.zh...@rivai.ai
CC: gcc-patches@gcc.gnu.org; pal...@dabbelt.com; jeffreya...@gmail.co
Hi!
On 2022-12-19T21:40:07+0100, Thomas Schwinge wrote:
> As I have reported to Nvidia in 2022-12-01 'NVIDIA Incident Report (3891704):
> ptxas: Duplicate declaration error: "cannot be resolved by a '.static'"',
> 'ptxas' has an inscrutable error mode for duplicate declarations:
>
> ptxas sof
This patch adds the binary_widen_opt_n shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_widen_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (binary_widen_opt_n): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc
This patch adds the binary_imm32 shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_imm32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_imm32): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 27 +
Factorize vqshluq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn): Add vqshlu.
(supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S.
(VQSHLUQ_M_N, VQSHLUQ_N): New.
* config/arm/mve.md (mve_vqshluq_n_s
This patch adds the binary_lshift_unsigned shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc
(binary_lshift_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h
(binary_lshift_unsigned): New.
---
gcc/config/arm
Implement vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-
Implement vqdmullbq, vqdmulltq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vqdmullbq, vqdmulltq): New.
* config/arm/arm-mve-builtins-base.def (vqdmullbq, vqdmulltq):
New.
* config/arm/arm-m
Factorize vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
builtins so that they use the same parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVHAxQ)
(MVE_VRMLxLDAVHAxQ_P): New.
(mve_insn): Add vrmlaldavha, vrml
Implement vbrsrq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vbrsrq): New.
* config/arm/arm-mve-builtins-base.def (vbrsrq): New.
* config/arm/arm-mve-builtins-base.h (vbrsrq): New.
* config
Factorize vqdmullbq, vqdmulltq builtins so that they use the same
parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VQDMULLxQ, MVE_VQDMULLxQ_M)
(MVE_VQDMULLxQ_M_N, MVE_VQDMULLxQ_N): New.
(mve_insn): Add vqdmullb, vqdmullt.
Factorize vrbsrq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
(mve_insn): Add vbrsr.
* config/arm/mve.md (mve_vbrsrq_n_f): Rename into ...
(@mve_q_n_f):
This patch adds the vpsel shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (vpsel): New.
* config/arm/arm-mve-builtins-shapes.h (vpsel): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 39 +++
gcc/confi
Factorize vsliq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn>): Add vsli.
* config/arm/mve.md (mve_vsliq_n_): Rename into ...
(@mve_q_n_): ... this.
(mve_vsliq_m_n_): Rename into ...
Implement vsliq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vsliq): New.
* config/arm/arm-mve-builtins-base.def (vsliq): New.
* config/arm/arm-mve-builtins-base.h (vsliq): New.
* config/arm
Factorize vmvnq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn): Add vmvn.
* config/arm/mve.md (mve_vmvnq_n_): Rename into ...
(@mve_q_n_): ... this.
(mve_vmvnq_m_): Rename into ...
This patch adds the ternary_opt_n shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_opt_n): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 30 ++
Implement vqshluq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vqshluq): New.
* config/arm/arm-mve-builtins-base.def (vqshluq): New.
* config/arm/arm-mve-builtins-base.h (vqshluq): New.
* co
This patch adds the ternary_rshift shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_rshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_rshift): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 38 +++
Factorize vpselq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of
gen_mve_vpselq.
* config/arm/iterators.md (MVE_VPSELQ_F): New.
(mve_insn): Add vpsel.
This patch adds the mvn shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (mvn): New.
* config/arm/arm-mve-builtins-shapes.h (mvn): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 49 +++
gcc/config/arm/
Implement vmvnq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc
(FUNCTION_WITH_RTX_M_N_NO_F): New.
(vmvnq): New.
* config/arm/arm-mve-builtins-base.def (vmvnq): New.
* config/arm/arm-mve
This patch adds the ternary_lshift shape description.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_lshift): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 38 +++
Implement vfmaq, vfmasq, vfmsq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.def (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-built
Implement vpselq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vpselq): New.
* config/arm/arm-mve-builtins-base.def (vpselq): New.
* config/arm/arm-mve-builtins-base.h (vpselq): New.
* config
Factorize vsriq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (mve_insn): Add vsri.
* config/arm/mve.md (mve_vsriq_n_): Rename into ...
(@mve_q_n_): .,. this.
(mve_vsriq_m_n_): Rename into ...
Factorize vmvnq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_FP_M_BINARY): Add VFMAQ_M_F,
VFMSQ_M_F.
(MVE_FP_M_N_BINARY): Add VFMAQ_M_N_F, VFMASQ_M_N_F.
(MVE_VFMxQ_F, MVE_VFMAxQ_N_F): New.
Implement vsriq using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vsriq): New.
* config/arm/arm-mve-builtins-base.def (vsriq): New.
* config/arm/arm-mve-builtins-base.h (vsriq): New.
* config/arm
speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.
gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 12, 2023 10:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/26] arm: [MVE intrinsics] add binary_widen_opt_n shape
>
> This patch
On Thursday 11 May 2023 at 21:52:22 +0100, Jonathan Wakely wrote:
> On Thu, 11 May 2023 at 13:42, Jonathan Wakely wrote:
>
> >
> >
> > On Thu, 11 May 2023 at 13:19, Mike Crowe wrote:
> >
> >> However, ...
> >>
> >> > > diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4
> >> > > i
speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.
gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
On Fri, 12 May 2023 at 11:30, Mike Crowe wrote:
> On Thursday 11 May 2023 at 21:52:22 +0100, Jonathan Wakely wrote:
> > On Thu, 11 May 2023 at 13:42, Jonathan Wakely
> wrote:
> >
> > >
> > >
> > > On Thu, 11 May 2023 at 13:19, Mike Crowe wrote:
> > >
> > >> However, ...
> > >>
> > >> > > diff -
On 5/12/23 12:17, Kyrylo Tkachov wrote:
-Original Message-
From: Christophe Lyon
Sent: Friday, May 12, 2023 10:39 AM
To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
Richard Earnshaw ; Richard Sandiford
Cc: Christophe Lyon
Subject: [PATCH 01/26] arm: [MVE intrinsics] add binary_wide
From: Juzhe-Zhong
Consider this following case:
typedef int64_t vnx32di __attribute__ ((vector_size (256)));
__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
vnx32di v
= {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
a, b, a, b, a, b
juzhe.zh...@rivai.ai writes:
> From: Ju-Zhe Zhong
>
> 1. Fix document description according Jeff && Richard.
> 2. Add LOOP_VINFO_USING_SELECT_VL_P for single rgroup.
> 3. Add LOOP_VINFO_USING_SLP_ADJUSTED_LEN_P for SLP multiple rgroup.
>
> Fix bugs for V5 after testing:
> https://gcc.gnu.org/piper
Thanks Richard for comments. In previous, I am not sure it is reasonable to let
everywhere consume the same macro in rtl.h (As the includes you mentioned).
Thus, make a conservative change in PATCH v1.
I will address the comments and try to align the bit size to the one and the
only one macro s
Hello Jeff:
On 29/04/23 3:40 am, Jeff Law wrote:
>
>
> On 4/20/23 15:03, Ajit Agarwal wrote:
>
>>
>> Currently I support AND with const1_rtx. This is what is equivalent to zero
>> extension instruction in power instruction set. When you specify many other
>> constants and Could you please sp
"Li, Pan2 via Gcc-patches" writes:
> Thanks Richard for comments. In previous, I am not sure it is reasonable to
> let everywhere consume the same macro in rtl.h (As the includes you
> mentioned). Thus, make a conservative change in PATCH v1.
>
> I will address the comments and try to align the
"juzhe.zhong" writes:
> Thanks Richard.
> I will do that as you suggested. I have a question for the first patch. How
> to
> enable decrement IV？ Should I add a target hook or something to let target
> decide whether enable decrement IV？
At the moment, the only other targets that use IFN_LOAD_L
The following adds another variant of address difference simplification.
The utility ptr_difference_const only handles constant differences
(we also cannot code generate anything else), so exposing a possible
POINTER_PLUS_EXPR in the match and computing the difference on the
base only makes it poss
Never minder. When preparing the PR, I am keeping ask myself that is everywhere
about machine code bit size updated? Thus would like to align the bit size to
one macro, to avoid developers (perhaps myself in future) suffering such kind
of concern.
Will try to move the machine mode to machmode.h
This patch adds support for running constructors and destructors for
static (file-scope) aggregates for C++ objects which are marked with
"declare target" directives on OpenMP offload targets.
At present, space is allocated on the target for such aggregates, but
nothing ever constructs them proper
Hi,
I think I tackled all of your comments, let me know if I missed something.
gcc/ChangeLog:
2023-05-12 Andre Vieira
Joel Hutton
* tree-vect-patterns.cc (vect_gimple_build): New Function.
(vect_recog_widen_op_pattern): Refactor to use code_helper.
* t
I have dealt with, I think..., most of your comments. There's quite a
few changes, I think it's all a bit simpler now. I made some other
changes to the costing in tree-inline.cc and gimple-range-op.cc in which
I try to preserve the same behaviour as we had with the tree codes
before. Also added
Moved the 'changes' from this patch back to the second so it's all just
about removing code that we no longer use. I don't really know why Joel
formatted the patches this way, but I thought I'd keep it as is for now.
cover letter:
This patch removes the old widen plus/minus tree codes which ha
I noticed only after the fact that the new testcase template/function2.C
(from r14-708-gc3afdb8ba8f183) is just a subset of ext/visibility/anon8.C,
so let's get rid of it.
PR c++/83258
gcc/testsuite/ChangeLog:
* g++.dg/ext/visibility/anon8.C: Mention PR83258.
* g++.dg/tem
This rewrites the testcase for PR109752 to make it simpler and more
robust (i.e. no longer dependent on r13-4035-gc41bbfcaf9d6ef).
PR c++/109752
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/concepts-pr109752.C: Rename to ...
* g++.dg/cpp2a/concepts-complete4.C: ... this. Rewr
Hi,
PR 108007 is another manifestation where we rely on DCE to clean-up
after IPA-SRA and if the user explicitely switches DCE off, IPA-SRA
can leave behind statements which are fed uninitialized values and
trap, even though their results are themselves never used.
I have already fixed this for u
Long standing issue but as top-level 'asm' statement were rare, it did not show
up.
However, the fix for PR108969 in commit r14-321-g9a41d2cdbcd added code
+#elif defined(_GLIBCXX_SYMVER_GNU)
+ __extension__ __asm (".globl _ZSt21ios_base_library_initv");
q
libstdc++-v3/include/std/iostream. Thi
The following also covers TARGET_MEM_REF when decomposing stores from
CTORs to supported elementwise operations. This avoids spilling
and cleans up after vector lowering which doesn't touch loads or
stores. It also mimics what we already do for loads.
Bootstrapped and tested on x86_64-unknown-li
Hi,
in general LGTM, just minor nits and comments.
> - void set_len_and_policy (rtx len, bool force_vlmax = false)
> -{
> - bool vlmax_p = force_vlmax;
> - gcc_assert (has_dest);
> + void set_len_and_policy (rtx len, bool force_vlmax = false, bool ta_p =
> true,
> +
On Fri, 12 May 2023, Tobias Burnus wrote:
> Long standing issue but as top-level 'asm' statement were rare, it did not
> show up.
> However, the fix for PR108969 in commit r14-321-g9a41d2cdbcd added code
>
> +#elif defined(_GLIBCXX_SYMVER_GNU)
> + __extension__ __asm (".globl _ZSt21ios_base_libr
On Fri, 12 May 2023, Andre Vieira (lists) wrote:
> Hi,
>
> I think I tackled all of your comments, let me know if I missed something.
This first and the last patch look good to me now. Let me comment on the
second.
Thanks,
Richard.
>
> gcc/ChangeLog:
>
> 2023-05-12 Andre Vieira
>
"juzhe.zhong" writes:
> Hi, Richard. For "can iterate more than once", is it correct use the
> condition
> "LOOP_LENS ().length >1".
No, that says whether any LOAD_LENs or STORE_LENs operate on multiple
vectors, rather than just single vectors.
I meant: whether the vector loop body might
On Fri, 12 May 2023, Andre Vieira (lists) wrote:
> I have dealt with, I think..., most of your comments. There's quite a few
> changes, I think it's all a bit simpler now. I made some other changes to the
> costing in tree-inline.cc and gimple-range-op.cc in which I try to preserve
> the same beha
V4 Changes:
- Use different approach of V3.
- Rewrite local_eliminate_vsetvl_insn to unify the optimization
flow.
- Also improve few more case.
Off list discussed and reviewed by Ju-Zhe.
---
This issue happens is because we are currently very conservative in
opti
Convert vlmul and policy to human readable string, some example below:
Before:
[VALID,Demand
field={1(VL),0(DEMAND_NONZERO_AVL),1(SEW),0(DEMAND_GE_SEW),1(LMUL),0(RATIO),0(TAIL_POLICY),0(MASK_POLICY)}
AVL=(reg:DI 0 zero)
SEW=16,VLMUL=3,RATIO=2,TAIL_POLICY=1,MASK_POLICY=1]
^
> emit_merge_op can not be wrapped into binop since mask position is
> different in pattern.
>
> I prefer merge op in different wrapper.
Yes, I didn't mean literally the same but that things already
become a bit confusing with all the different variants and bool
arguments or code duplication with
Hi Julian, hi all,
(I have not (yet) looked at the patch/testcase in depth - and I prefer
that someone knowledgeable with C++ constructors comments. However:)
Regarding only nvptx - and the testcase on nvptx:
On 12.05.23 14:02, Julian Brown wrote:
The approach taken is to generate a set of con
Tested x86_64-linux. Pushed to trunk.
-- >8 --
These #ifdef checks should have been removed in r9-2029-g612c9c702e2c9e
when the u16string_view and u32string_view aliases were changed to be
defined unconditionally.
libstdc++-v3/ChangeLog:
* testsuite/21_strings/basic_string_view/typedefs
Tested x86_64-linux. Pushed to trunk.
-- >8 --
This should have been done in r9-2028-g8ba7f29e3dd064 when
std::shared_mutex was changed to be defined without depending on
_GLIBCXX_USE_C99_STDINT_TR1.
libstdc++-v3/ChangeLog:
* testsuite/experimental/feat-cxx14.cc: Remove dependency on
Tested x86_64-linux. Pushed to trunk.
-- >8 --
This should have been removed in r9-2029-g612c9c702e2c9e when the
char16_t and char32_t specializations of std::codecvt were changed to be
defined unconditionally.
libstdc++-v3/ChangeLog:
* testsuite/22_locale/locale/cons/unicode.cc: Remove
> From: Hans-Peter Nilsson
> Date: Thu, 11 May 2023 17:05:40 +0200
> Next, I'll turn around completely, and try defaulting to
> -fsplit-wide-types-early, which sounds more promising. :)
> I don't like throwing defaults around randomly, but trying
> out a promising idea this way is easy.
Absolute
On 12/05/2023 14:28, Richard Biener wrote:
On Fri, 12 May 2023, Andre Vieira (lists) wrote:
I have dealt with, I think..., most of your comments. There's quite a few
changes, I think it's all a bit simpler now. I made some other changes to the
costing in tree-inline.cc and gimple-range-op.cc
Richard Biener writes:
> On Fri, 12 May 2023, Andre Vieira (lists) wrote:
>
>> I have dealt with, I think..., most of your comments. There's quite a few
>> changes, I think it's all a bit simpler now. I made some other changes to the
>> costing in tree-inline.cc and gimple-range-op.cc in which I t
> From: Hans-Peter Nilsson
> Date: Fri, 12 May 2023 15:53:49 +0200
> Anyway, Roger mentioned that the clobbers emitted by the
> lower-subreg passes were apparently damaging, so I'll try
> this out "for fun", on the assumption that they're actually
> unnecessary. I don't think actually removing t
Hi H-P,
This patch should now already be on trunk:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d8a6945c6ea22efa4d5e42fe1922d2
b27953c8cd
Many thanks to Jeff for the review/approval.
There have been no reported adverse effects so far.
Please let me/us know if this has helped CRIS.
Cheers,
Roger
On Thu, 11 May 2023 at 08:08, Uros Bizjak wrote:
>
> On Thu, May 11, 2023 at 12:04 AM H.J. Lu wrote:
> >
> > On Wed, May 10, 2023 at 2:17 AM Uros Bizjak wrote:
> > >
> > > On Tue, May 9, 2023 at 10:58 AM Ard Biesheuvel wrote:
> > > >
> > > > The small and medium PIC code models generate profili
On Tue, Feb 14, 2023 at 16:50:27 -0500, Jason Merrill wrote:
> I notice that the actual flags are all -fdep-*, though some of them are
> -fdeps-* here, and the internal variables all seem to be fdeps_*. I
> lean toward harmonizing on "deps", I think.
Done.
> I don't love the three separate opt
On Mon, Feb 13, 2023 at 10:53:17 -0500, Jason Merrill wrote:
> On 1/25/23 13:06, Ben Boeckel wrote:
> > Unicode does not support such values because they are unrepresentable in
> > UTF-16.
> >
> > libcpp/
> >
> > * charset.cc: Reject encodings of codepoints above 0x10.
> > UTF-16 does
On Mon, Feb 13, 2023 at 13:33:50 -0500, Jason Merrill wrote:
> Both this and the mapper dependency patch seem to cause most of the
> modules testcases to crash; please remember to run the regression tests
> (https://gcc.gnu.org/contribute.html#testing)
Fixed for v6. `cpp_get_deps` can return `NU
From: Juzhe-Zhong
Address comment from Robin.
Consider this following case:
typedef int64_t vnx32di __attribute__ ((vector_size (256)));
__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
vnx32di v
= {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
Summary: The old linear scan logic called free while searching the list
of frames. The atomic fast path finds the frame quickly, but forgot the
free call. This patches adds the missing free. Bugzilla #109685.
See:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617245.html
Best
Thomas
two minor comments:
> + void add_ta_policy_operand (enum tail_policy vta)
> + void add_ma_policy_operand (enum mask_policy vma)
You could just named as add_policy_operand since the arugment type is
already sufficient to distinguish.
> @@ -84,40 +92,52 @@ public:
> add_input_operand (gen_i
From: Juzhe-Zhong
Address comments from Kito.
Consider this following case:
typedef int64_t vnx32di __attribute__ ((vector_size (256)));
__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
vnx32di v
= {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b,
From: Pan Li
We are running out of the machine_mode(8 bits) in RISC-V backend. Thus
we would like to extend the machine_mode bit size from 8 to 16 bits.
However, it is sensitive to extend the memory size in common structure
like tree or rtx. This patch would like to extend the machine_mode bits
t
From: Juzhe-Zhong
Patch V3 fail testcase
V4 all pass
Address kito's comment
Consider this following case:
typedef int64_t vnx32di __attribute__ ((vector_size (256)));
__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
vnx32di v
= {a, b, a, b, a, b, a, b, a, b,
Address comments.
V4 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618375.html
Regresion PASSED.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-12 23:19
To: juzhe.zhong
CC: gcc-patches; palmer; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Using merge approa
Hello Patrick,
On Wed, May 03 2023, Patrick Palka via Gcc-patches wrote:
>
[...]
>
> Subject: [PATCH] c++: potentiality of templated memfn call [PR109480]
>
> Here we're incorrectly deeming the templated call a.g() inside b's
> initializer as potentially constant, despite g being non-constexpr,
>
> +/* Get the mask for merge approach.
> +
> + Consider such following case:
> + {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b}
> + To merge "a", the mask should be 1010
> + To merge "b", the mask should be 0101
> +*/
> +rtx
> +rvv_builder::get_merge_mask_bitfield (unsig
Remove mulv2si emulated sequence for TARGET_SSE2 and enable
only native PMULLD instruction for TARGET_SSE4_1. Ideally, the
vectorization for TARGET_SSE2 should depend on more precise cost
estimation (the PR contains patch for ix86_multiplication_cost),
but even with patched cost function the runti
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
We never need to use std::make_unsigned in std::char_traits
and std::char_traits because guarantees to provide
the types we need, since r9-2028-g8ba7f29e3dd064.
Similarly, experimental::source_location can just assume uint_least32_t
is defined
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
Since r9-2028-g8ba7f29e3dd064 we've defined most of
unconditionally, including uint_least32_t. This means that all of
can be defined unconditionally, which means that std::shuffle
and std::ranges::shuffle can be too.
libstdc++-v3/ChangeLog:
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
Since r9-2028-g8ba7f29e3dd064 we've defined most of
unconditionally, so we can do the same for most of the std::atomic
aliases such as std::atomic_int_least32_t.
The only aliases that need to depend on _GLIBCXX_USE_C99_STDINT_TR1 are
the ones
1 - 100 of 126 matches
Mail list logo
