[PATCH v3] libgfortran: Replace mutex with rwlock

This patch try to introduce the rwlock and split the read/write to unit_root tree and unit_cache with rwlock instead of the mutex to increase CPU efficiency. In the get_gfc_unit function, the percentage to step into the insert_unit function is around 30%, in most instances, we can get the unit in t

Re: [PATCH v2] expansion: make layout of x_shift*cost[][][] more efficient

On Tue, Apr 18, 2023 at 10:51 PM Vineet Gupta wrote: > > when debugging expmed.[ch] for PR/108987 saw that some of the cost arrays have > less than ideal layout as follows: > >x_shift*cost[0..63][speed][modes] > > We would want speed to be first index since a typical compile will have > that f

[PATCH] [i386] Support type _Float16/__bf16 independent of SSE2.

-Jakub's comments-- That said, these fundamental types whose presence/absence depends on ISA flags are quite problematic IMHO, as they are incompatible with the target attribute/pragmas. Whether they are available or not available depends on whether in this case SSE2 is enabled during c

[PATCH] rtl-optimization/109237 - speedup bb_is_just_return

For the testcase bb_is_just_return is on top of the profile, changing it to walk BB insns backwards puts it off the profile. That's because in the forward walk you have to process possibly many debug insns but in a backward walk you very likely run into control insns first. This is a fixed versio

Re: [PATCH] LoongArch: fix MUSL_DYNAMIC_LINKER

在 2023/4/17 下午2:51, 樊鹏 写道: Yes, https://wiki.musl-libc.org/guidelines-for-distributions.html, "Multilib/multi-arch" section of this introduces it. Hi,  fanpeng: I agree with ruoyao, add this link to the commit message. I have no problem with other. Thanks! -Original Messages- F

Re: [PATCH] Introduce VIRTUAL_REGISTER_P and VIRTUAL_REGISTER_NUM_P predicates

On Wed, Apr 19, 2023 at 08:53:42AM +0200, Uros Bizjak wrote: > On Tue, Apr 18, 2023 at 7:20 PM Jakub Jelinek wrote: > > > > On Mon, Apr 17, 2023 at 11:27:28PM +0200, Uros Bizjak via Gcc-patches wrote: > > > --- a/gcc/rtl.h > > > +++ b/gcc/rtl.h > > > @@ -1972,6 +1972,13 @@ set_regno_raw (rtx x, un

[committed] testsuite: Fix up pr109524.C for -std=c++23 [PR109524]

On Mon, Apr 17, 2023 at 08:41:38AM +, Richard Biener via Gcc-patches wrote: > * g++.dg/pr109524.C: New testcase. This testcase was reduced such that it isn't valid C++23, so with my usual testing with GXX_TESTSUITE_STDS=98,11,14,17,20,2b it fails: FAIL: g++.dg/pr109524.C -std=gnu++2b (t

[PATCH] LoongArch: fix MUSL_DYNAMIC_LINKER

The system based on musl has no '/lib64', so change it. https://wiki.musl-libc.org/guidelines-for-distributions.html, "Multilib/multi-arch" section of this introduces it. gcc/ * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER: Redefine.) Signed-off-by: Peng Fan Suggested-by: Xi Ruoyao

[PATCH][committed] aarch64: PR target/108840 Simplify register shift RTX costs and eliminate shift amount masking

Hi all, In this PR we fail to eliminate explicit &31 operations for variable shifts such as in: void bar (int x[3], int y) { x[0] <<= (y & 31); x[1] <<= (y & 31); x[2] <<= (y & 31); } This is rejected by RTX costs that end up giving too high a cost for: (set (reg:SI 96) (ashift:SI (reg

Re: [aarch64] Use wzr/xzr for assigning vector element to 0

On Tue, 31 Jan 2023 at 11:51, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Mon, 23 Jan 2023 at 22:26, Richard Sandiford > > wrote: > >> > >> Prathamesh Kulkarni writes: > >> > On Wed, 18 Jan 2023 at 19:59, Richard Sandiford > >> > wrote: > >> >> > >> >> Prathamesh Kulkarni

RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization

Hi Richard, Do you have any idea about this? I leverage git gcc-commit-mklog, it will generate something as below. It looks no text after colon. I am not sure if I need to add something by myself. gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): <=

RE: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Passed the X86 bootstrap and regression tests. Pan -Original Message- From: Li, Pan2 Sent: Wednesday, April 19, 2023 11:21 AM To: gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang ; Li, Pan2 Subject: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) sho

[PATCH] tree-vect-patterns: Improve __builtin_{clz,ctz,ffs}ll vectorization [PR109011]

Hi! For __builtin_popcountll tree-vect-patterns.cc has vect_recog_popcount_pattern, which improves the vectorized code. Without that the vectorization is always multi-type vectorization in the loop (at least int and long long types) where we emit two .POPCOUNT calls with long long arguments and in

RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization

On Wed, 19 Apr 2023, Li, Pan2 wrote: > Hi Richard, > > Do you have any idea about this? I leverage git gcc-commit-mklog, it > will generate something as below. It looks no text after colon. I am not > sure if I need to add something by myself. Well, you need to add a description of your change

Re: [PATCH] tree-vect-patterns: Improve __builtin_{clz,ctz,ffs}ll vectorization [PR109011]

On Wed, 19 Apr 2023, Jakub Jelinek wrote: > Hi! > > For __builtin_popcountll tree-vect-patterns.cc has > vect_recog_popcount_pattern, which improves the vectorized code. > Without that the vectorization is always multi-type vectorization > in the loop (at least int and long long types) where we e

[PATCH] c: Avoid -Wenum-int-mismatch warning for redeclaration of builtin acc_on_device [PR107041]

Hi! The new -Wenum-int-mismatch warning triggers with -Wsystem-headers in , for obvious reasons the builtin acc_on_device uses int type argument rather than enum which isn't defined yet when the builtin is created, while the OpenACC spec requires it to have acc_device_t enum argument. The header

[PATCH v3] RISC-V: Align IOR optimization MODE_CLASS condition to AND.

From: Pan Li This patch aligned the MODE_CLASS condition of the IOR to the AND. Then more MODE_CLASS besides SCALAR_INT can able to perform the optimization A | (~A) -> -1 similar to AND operator. For example as below sample code. vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size

RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization

Thank you for information. Updated the v3 version as below. https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616154.html Pan -Original Message- From: Richard Biener Sent: Wednesday, April 19, 2023 4:52 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@s

Re: [match.pd] [SVE] Add pattern to transform svrev(svrev(v)) --> v

On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni wrote: > > On Tue, 11 Apr 2023 at 14:17, Richard Biener > wrote: > > > > On Wed, Apr 5, 2023 at 10:39 AM Prathamesh Kulkarni via Gcc-patches > > wrote: > > > > > > Hi, > > > For the following test: > > > > > > svint32_t f(svint32_t v) > > > { >

[PATCH][committed] aarch64: Delete __builtin_aarch64_neg* builtins and their use

Hi all, I don't think we need to keep the __builtin_aarch64_neg* builtins around. They are only used once in the vnegh_f16 intrinsic in arm_fp16.h and I AFAICT it was added this way only for the sake of orthogonality in https://gcc.gnu.org/g:d7f33f07d88984cbe769047e3d07fc21067fbba9 We already use

Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Hi Pan: >rtx expand (function_expander &e) const override diff --git > a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index > 0ecca98f20c..6819363b9ff 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred

[PATCH] Transform more gmp/mpfr uses to use RAII

The following picks up the coccinelle generated patch from Bernhard, leaving out the fortran frontend parts and fixing up the rest. In particular both gmp.h and mpfr.h contain macros like #define mpfr_inf_p(_x) ((_x)->_mpfr_exp == __MPFR_EXP_INF) for which I add operator-> overloads to the a

Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Since vms pattern has one more tail policy + avl_type operand, wheras pred_mov (vmset.m/vmclr.m) only has avl_type operand. GCC recognize (lt:(reg v) (reg v)) and lower it into (const_vector:0), then map into pred_mov pattern (when both pred_mov and vms pattern has tail policy + avl_type operand).

Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

HI JuZhe: Thanks for explaining! Hi Pan: I think that would be helpful if JuZhe's explaining that could be written into the commit log. > gcc/ChangeLog: > >* config/riscv/riscv-v.cc (emit_pred_op): >* config/riscv/riscv-vector-builtins-bases.cc: >* config/riscv/vector.

[PATCH] Simplify gimple_assign_load

The following simplifies and outlines gimple_assign_load. In particular it is not necessary to get at the base of the possibly loaded expression but just handle the case of a single handled component wrapping a non-memory operand. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.

[PATCH v8] RISC-V: Add the 'zfa' extension, version 0.2.

This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commits/zfb https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da The binutils-gdb for 'Zfa' extension: https://github.com/a4lg/binutils-gdb/commit

Re: [PATCH] i386: Add new pattern for zero-extend cmov

On Wed, Apr 19, 2023 at 1:33 AM Andrew Pinski via Gcc-patches wrote: > > After a phiopt change, I got a failure of cmov9.c. > The RTL IR has zero_extend on the outside of > the if_then_else rather than on the side. Both > ways are considered canonical as mentioned in > PR 66588. > > This fixes the

Pushed: [PATCH] LoongArch: Improve GAR store for va_list

On Tue, 2023-04-18 at 20:03 +0800, Lulu Cheng wrote: > > 在 2023/4/18 下午7:48, Xi Ruoyao 写道: > > On Tue, 2023-04-18 at 19:21 +0800, Lulu Cheng wrote: > > > 在 2023/4/18 下午5:27, Xi Ruoyao 写道: > > > > On Mon, 2023-04-10 at 17:45 +0800, Lulu Cheng wrote: > > > > > Sorry, it's my question. I still have s

Pushed: [GCC14 PATCH] LoongArch: Improve cpymemsi expansion [PR109465]

On Wed, 2023-04-19 at 11:03 +0800, Lulu Cheng wrote: /* snip */ > > +loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT > > length, > > +  HOST_WIDE_INT delta) > >   { > > -  HOST_WIDE_INT offset, delta; > > -  unsigned HOST_WIDE_INT bits; > > +  HOST_WIDE

[PATCH] Avoid repeated forwarder_block_p calls in CFG cleanup

CFG cleanup maintains BB_FORWARDER_BLOCK and uses FORWARDER_BLOCK_P to check that apart from two places which use forwarder_block_p in outgoing_edges_match alongside many BB_FORWARDER_BLOCK uses. The following adjusts those. Bootstrapped and tested on x86_64-unknown-linux-gnu, I verified cc1files

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Sure thing. For Changlog, I consider it was generated automatically in previous. LOL. Pan -Original Message- From: Kito Cheng Sent: Wednesday, April 19, 2023 5:46 PM To: juzhe.zh...@rivai.ai Cc: Li, Pan2 ; gcc-patches ; Kito.cheng ; Wang, Yanzhang Subject: Re: Re: [PATCH] RISC-V: All

[PATCH] RISC-V: Fix bug of PR109535

From: Ju-Zhe Zhong PR 109535 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function. (pass_vsetvl::cleanup_insns): Fix bug. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr109535.C: New test. * gcc.target/riscv/rvv/

[PATCH] RISC-V: Fix bug of PR109535

From: Ju-Zhe Zhong Testcase coming from Kito. Co-authored-by: kito-cheng Co-authored-by: kito-cheng PR 109535 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function. (pass_vsetvl::cleanup_insns): Fix bug. gcc/testsuite/ChangeLog:

RE: [PATCH 2/3]middle-end match.pd: simplify debug dump checks

> -Original Message- > From: Richard Biener > Sent: Tuesday, April 18, 2023 11:48 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; rguent...@suse.de; > j...@ventanamicro.com > Subject: Re: [PATCH 2/3]middle-end match.pd: simplify debug dump checks > > On Tue, Apr 18, 2023 at

Re: Re: [PATCH] RISC-V: Fix bug reported by PR109535

Thanks Jeff. Address Jeff's comment and resend fix patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616170.html This patch also added a testcase coming from Kito (Kito reduced google/highway testcase from over 10W lines codes into 100 lines codes!!!). juzhe.zh...@rivai.ai From: J

Re: [match.pd] [SVE] Add pattern to transform svrev(svrev(v)) --> v

On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni wrote: > > On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni > wrote: > > > > On Tue, 11 Apr 2023 at 14:17, Richard Biener > > wrote: > > > > > > On Wed, Apr 5, 2023 at 10:39 AM Prathamesh Kulkarni via Gcc-patches > > > wrote: > > > > > > >

Re: [PATCH 3/3]middle-end RFC - match.pd: automatically partition *-match.cc files.

On Tue, Apr 18, 2023 at 12:23 PM Tamar Christina via Gcc-patches wrote: > > Hi All, > > Following on from Richi's RFC[1] this is another attempt to split up match.pd > into multiple gimple-match and generic-match files. This version is fully > automated and requires no human intervention. > > Fir

[PATCH v2] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

From: Pan Li This patch try to adjust the RISC-V Vector RTL for the generic shortcut optimization for RVV integer compare. It includes compare operator eq, ne, ltu, lt, leu, le, gtu, gt, geu and ge. Assume we have below test code. vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Update the Patch v2 for more detail information for clarification. Please help to review continuously. https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html Pan -Original Message- From: Li, Pan2 Sent: Wednesday, April 19, 2023 6:33 PM To: Kito Cheng ; juzhe.zh...@rivai.ai Cc

[PATCH] Remove odd code from gimple_can_merge_blocks_p

The following removes a special case to not merge a block with only a non-local label. We have a restriction of non-local labels to be the first statement (and label) in a block, but otherwise nothing, if the last stmt of A is a non-local label then it will be still the first statement of the comb

[PATCH 1/4] Avoid non-unified nodes on the topological sorting for PTA solving

Since we do not update successor edges when merging nodes we have to deal with this in the users. The following avoids putting those on the topo order vector. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-structalias.cc (topo_visit): Look at the real des

[PATCH 2/4] Remove senseless store in do_sd_constraint

Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-structalias.cc (do_sd_constraint): Do not write to the LHS varinfo solution member. --- gcc/tree-ssa-structalias.cc | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/gcc/tree-ssa-struct

[PATCH 3/4] Fix do_sd_constraint escape special casing

The following fixes the escape special casing to test the proper variable IDs. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-structalias.cc (do_sd_constraint): Fixup escape special casing. --- gcc/tree-ssa-structalias.cc | 2 +- 1 file changed, 1 inserti

[PATCH 4/4] Remove special-cased edges when solving copies

The following makes sure to remove the copy edges we ignore or need to special-case only once. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-structalias.cc (solve_graph): Remove self-copy edges, remove edges from escaped after special-casing them. --- gc

Re: [match.pd] [SVE] Add pattern to transform svrev(svrev(v)) --> v

On Wed, 19 Apr 2023 at 16:17, Richard Biener wrote: > > On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni > wrote: > > > > On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni > > wrote: > > > > > > On Tue, 11 Apr 2023 at 14:17, Richard Biener > > > wrote: > > > > > > > > On Wed, Apr 5, 2023 a

Re: [PATCH] RISC-V: Support chunk 128

Could you add more description? maybe like this: RISC-V has provide different VLEN configuration by different ISA extension like `zve32x`, `zve64x` and `v` zve32x just guarantee the minimal VLEN is 32 bits, zve64x guarantee the minimal VLEN is 64 bits, and v guarantee the minimal VLEN is 128 bits

Re: [PATCH] Transform more gmp/mpfr uses to use RAII

On Wed, 19 Apr 2023 at 10:36, Richard Biener wrote: > > The following picks up the coccinelle generated patch from Bernhard, > leaving out the fortran frontend parts and fixing up the rest. > In particular both gmp.h and mpfr.h contain macros like > #define mpfr_inf_p(_x) ((_x)->_mpfr_exp ==

Re: [PATCH] Fix pointer sharing in Value_Range constructor.

On 4/18/23 18:40, Aldy Hernandez wrote: I will push this when a final round of testing finishes on x86-64 Linux. gcc/ChangeLog: * value-range.h (Value_Range::Value_Range): Avoid pointer sharing. --- gcc/value-range.h | 13 - 1 file changed, 12 insertions(+), 1 deletion(

[PATCH 04/10] RISC-V: Support chunk 128

From: Juzhe-Zhong RISC-V has provide different VLEN configuration by different ISA extension like `zve32x`, `zve64x` and `v` zve32x just guarantee the minimal VLEN is 32 bits, zve64x guarantee the minimal VLEN is 64 bits, and v guarantee the minimal VLEN is 128 bits, Current status (without this

Re: [match.pd] [SVE] Add pattern to transform svrev(svrev(v)) --> v

On Wed, Apr 19, 2023 at 2:20 PM Prathamesh Kulkarni wrote: > > On Wed, 19 Apr 2023 at 16:17, Richard Biener > wrote: > > > > On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni > > wrote: > > > > > > On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni > > > wrote: > > > > > > > > On Tue, 11 Apr

[PATCH] RISC-V: Support 128 bit vector chunk

From: Juzhe-Zhong RISC-V has provide different VLEN configuration by different ISA extension like `zve32x`, `zve64x` and `v` zve32x just guarantee the minimal VLEN is 32 bits, zve64x guarantee the minimal VLEN is 64 bits, and v guarantee the minimal VLEN is 128 bits, Current status (without this

Re: [PATCH v3] libgfortran: Replace mutex with rwlock

On 19 April 2023 09:06:28 CEST, Lipeng Zhu via Fortran wrote: >+#ifdef __GTHREAD_RWLOCK_INIT >+#define RWLOCK_DEBUG_ADD(rwlock) do { \ >+aio_rwlock_debug *n; \ >+n = malloc (sizeof(aio_rwlock_debug));\ My malloc can fail. >+n->prev = TAIL_RW

[PATCH] RISC-V: Add tuple type vget/vset intrinsics

From: Juzhe-Zhong gcc/ChangeLog: * config/riscv/genrvv-type-indexer.cc (valid_type): Adapt for tuple type support. (inttype): Ditto. (floattype): Ditto. (main): Ditto. * config/riscv/riscv-vector-builtins-bases.cc: Ditto. * config/riscv/riscv-vect

[PATCH 1/2] Split out solve_add_graph_edge

Split out a worker with all the special-casings when adding a graph edge during solving. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-structalias.cc (solve_add_graph_edge): New function, split out from ... (do_sd_constraint): ... here. --- gcc/t

[PATCH 2/2] Use solve_add_graph_edge in more places

The following makes sure to use solve_add_graph_edge and honoring special-cases, especially edges from escaped, in the remaining places the solver adds edges. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-structalias.cc (do_ds_constraint): Use solve_add_g

[PATCH] Docs, OpenMP: Small fixes to internal OMP_FOR doc

Hi Sandra, the OMP_FOR documentation says that the loop index variable must be signed and it does not list "!=" in the allowed conditional expressions. But there is nothing that would automatically cast an unsigned variable to signed or that converts the "!=" as you can see from the dump for thi

[wwwdocs] gcc-13: Add release note for RISC-V

--- htdocs/gcc-13/changes.html | 31 ++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index f6941534..5427f805 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -636,9 +63

Re: [wwwdocs] gcc-13: Add release note for RISC-V

LGTM。 juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-04-19 21:53 To: gcc-patches; kito.cheng; palmer; juzhe.zhong; jeffreyalaw CC: Kito Cheng Subject: [wwwdocs] gcc-13: Add release note for RISC-V --- htdocs/gcc-13/changes.html | 31 ++- 1 file changed, 30 insertio

Re: [wwwdocs] gcc-13: Add release note for RISC-V

On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote: --- htdocs/gcc-13/changes.html | 31 ++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index f6941534..5427f805 100644 --- a/

[PATCH][committed] aarch64: Factorise widening add/sub high-half expanders with iterators

Hi all, I noticed these define_expand are almost identical modulo some string substitutions. This patch compresses them together with a couple of code iterators. No functional change intended. Bootstrapped and tested on aarch64-none-linux-gnu. Pushing to trunk. Thanks, Kyrill gcc/ChangeLog:

Re: [PATCH v3] libgfortran: Replace mutex with rwlock

On Wed, 19 Apr 2023 at 14:51, Bernhard Reutner-Fischer wrote: > > On 19 April 2023 09:06:28 CEST, Lipeng Zhu via Fortran > wrote: > > >+#ifdef __GTHREAD_RWLOCK_INIT > >+#define RWLOCK_DEBUG_ADD(rwlock) do { \ > >+aio_rwlock_debug *n; \ > >+n = malloc

[PATCH] i386: Emit compares between high registers and memory

Following code: typedef __SIZE_TYPE__ size_t; struct S1s { char pad1; char val; short pad2; }; extern char ts[256]; _Bool foo (struct S1s a, size_t i) { return (ts[i] > a.val); } compiles with -O2 to: movl%edi, %eax movsbl %ah, %edi cmpb%dil, ts(%rsi)

Re: [wwwdocs] gcc-13: Add release note for RISC-V

> On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote: > > --- > > htdocs/gcc-13/changes.html | 31 ++- > > 1 file changed, 30 insertions(+), 1 deletion(-) > > > > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html > > index f6941534.

Re: [PATCH] testsuite: fix scan-tree-dump patterns [PR83904, PR100297]

On Wed, 19 Apr 2023 at 03:03, Jerry D via Fortran wrote: > > On 4/18/23 12:39 PM, Harald Anlauf via Fortran wrote: > > Dear all, > > > > the attached patch adjusts the scan-tree-dump patterns of the > > reported testcases which likely were run in a location such > > that a path in an error message

Re: [PATCH] RISC-V: Support 128 bit vector chunk

Committed to trunk, thanks! On Wed, Apr 19, 2023 at 8:34 PM wrote: > > From: Juzhe-Zhong > > RISC-V has provide different VLEN configuration by different ISA > extension like `zve32x`, `zve64x` and `v` > zve32x just guarantee the minimal VLEN is 32 bits, > zve64x guarantee the minimal VLEN is 64

Re: [PATCH v3] RISC-V: Align IOR optimization MODE_CLASS condition to AND.

Committed, thanks :) On Wed, Apr 19, 2023 at 5:19 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch aligned the MODE_CLASS condition of the IOR to the AND. Then > more MODE_CLASS besides SCALAR_INT can able to perform the optimization > A | (~A) -> -1 similar to AND operator. For

[13 PATCH RFA] c++: fix 'unsigned __int128_t' semantics [PR108099]

When I was backporting the earlier 108099 patch I finally saw your comments on the PR about the meaning of this pattern with the patch being wrong (and a regression from 11). This fixes that regression; fixing the broader issues can wait. Tested x86_64-pc-linux-gnu, OK for 13.1 or wait for 13.2?

Re: [13 PATCH RFA] c++: fix 'unsigned __int128_t' semantics [PR108099]

On Wed, Apr 19, 2023 at 11:20:09AM -0400, Jason Merrill wrote: > When I was backporting the earlier 108099 patch I finally saw your comments on > the PR about the meaning of this pattern with the patch being wrong (and a > regression from 11). This fixes that regression; fixing the broader issues

[PATCH] c++: bad ggc_free in try_class_unification [PR109556]

Aside from correcting how try_class_unification copies multi-dimensional 'targs', r13-377-g3e948d645bc908 also made it ggc_free this copy as an optimization. But this is potentially wrong since the call to unify within might've captured the args in persistent memory such as the satisfaction cache

[PATCH] recog.cc: Correct comments referring to parameter match_len

I'll commit this as obvious, so it doesn't trick anyone else anymore. -- >8 -- * recog.cc (peep2_attempt, peep2_update_life): Correct head-comment description of parameter match_len. --- gcc/recog.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/recog.

Re: [PATCH] Docs, OpenMP: Small fixes to internal OMP_FOR doc

On 4/19/23 07:51, Frederik Harwath wrote: Hi Sandra, the OMP_FOR documentation says that the loop index variable must be signed and it does not list "!=" in the allowed conditional expressions. But there is nothing that would automatically cast an unsigned variable to signed or that converts th

Re: [PATCH] c++: bad ggc_free in try_class_unification [PR109556]

On Wed, 19 Apr 2023, Patrick Palka wrote: > Aside from correcting how try_class_unification copies multi-dimensional > 'targs', r13-377-g3e948d645bc908 also made it ggc_free this copy as an > optimization. But this is potentially wrong since the call to unify > within might've captured the args i

[PATCH v2] Leveraging the use of STP instruction for vec_duplicate

The backend pattern for storing a pair of identical values in 32 and 64-bit modes with the machine instruction STP was missing, and multiple instructions were needed to reproduce this behavior as a result of failed RTL pattern match in the combine pass. For the test case: typedef long long v2di _

Re: [PATCH] testsuite: fix scan-tree-dump patterns [PR83904, PR100297]

On 4/19/23 17:14, Bernhard Reutner-Fischer via Gcc-patches wrote: On Wed, 19 Apr 2023 at 03:03, Jerry D via Fortran wrote: On 4/18/23 12:39 PM, Harald Anlauf via Fortran wrote: Dear all, the attached patch adjusts the scan-tree-dump patterns of the reported testcases which likely were run in

[PATCH 0/3] RISC-V: Basic enable RVV auto-vectorizaiton

From: Ju-Zhe Zhong PATCH 1: Add compile option for RVV auto-vectorization. PATCH 2: Enable basic RVV auto-vectorization. PATCH 3: Add sanity testcases. *** BLURB HERE *** Ju-Zhe Zhong (3): RISC-V: Add auto-vectorization compile option for RVV RISC-V: Enable basic auto-vectorization for RVV

[PATCH 1/3] RISC-V: Add auto-vectorization compile option for RVV

From: Ju-Zhe Zhong This patch is adding 2 compile option for RVV auto-vectorization. 1. -param=riscv-autovec-preference= This option is to specify the auto-vectorization approach for RVV. Currently, we only support scalable and fixed-vlmax. - scalable means VLA auto-vectorization.

[PATCH 2/3] RISC-V: Enable basic auto-vectorization for RVV

From: Ju-Zhe Zhong This patch enables auto-vectorization accurately according to '-march' And add len_load/len_store pattern. For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): Ena

[PATCH 0/3] RISC-V: Basic enable RVV auto-vectorizaiton

From: Ju-Zhe Zhong PATCH 1: Add compile option for RVV auto-vectorization. PATCH 2: Enable basic RVV auto-vectorization. PATCH 3: Add sanity testcases. *** BLURB HERE *** Ju-Zhe Zhong (3): RISC-V: Add auto-vectorization compile option for RVV RISC-V: Enable basic auto-vectorization for RVV

[PATCH 2/3] RISC-V: Enable basic auto-vectorization for RVV

From: Ju-Zhe Zhong This patch enables auto-vectorization accurately according to '-march' And add len_load/len_store pattern. For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): Ena

[PATCH 1/3] RISC-V: Add auto-vectorization compile option for RVV

From: Ju-Zhe Zhong This patch is adding 2 compile option for RVV auto-vectorization. 1. -param=riscv-autovec-preference= This option is to specify the auto-vectorization approach for RVV. Currently, we only support scalable and fixed-vlmax. - scalable means VLA auto-vectorization.

[PATCH 3/3] RISC-V: Add sanity testcases for RVV auto-vectorization

From: Ju-Zhe Zhong This patch adds sanity tests for basic enabling auto-vectorization. We should make sure compiler enable auto-vectorization strictly according to '-march' For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization. Since SEW = 64 RVV instructions are illegal ins

[PATCH 3/3] RISC-V: Add sanity testcases for RVV auto-vectorization

From: Ju-Zhe Zhong This patch adds sanity tests for basic enabling auto-vectorization. We should make sure compiler enable auto-vectorization strictly according to '-march' For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization. Since SEW = 64 RVV instructions are illegal ins

[C PATCH - backport 12] Fix ICE related to implicit access attributes for VLA arguments [PR105660]

Ok to cherrypick for 12? It is in GCC 13 and fixes an annoying ICE. Martin Here is a fix for PR105660. Bootstrapped and regression tested on x86-64. Fix ICE related to implicit access attributes for VLA arguments [PR105660] When constructing the specifier string when merging

[PATCH 0/3 V2] RISC-V: Basic enable RVV auto-vectorizaiton

From: Ju-Zhe Zhong PATCH 1: Add compile option for RVV auto-vectorization. PATCH 2: Enable basic RVV auto-vectorization. PATCH 3: Add sanity testcases. *** BLURB HERE *** Ju-Zhe Zhong (3): RISC-V: Add auto-vectorization compile option for RVV RISC-V: Enable basic auto-vectorization for RVV

[PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for RVV

From: Ju-Zhe Zhong This patch enables auto-vectorization accurately according to '-march' And add len_load/len_store pattern. For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): Ena

[PATCH 1/3 V2] RISC-V: Add auto-vectorization compile option for RVV

From: Ju-Zhe Zhong This patch is adding 2 compile option for RVV auto-vectorization. 1. -param=riscv-autovec-preference= This option is to specify the auto-vectorization approach for RVV. Currently, we only support scalable and fixed-vlmax. - scalable means VLA auto-vectorization.

[PATCH 3/3 V2] RISC-V: Add sanity testcases for RVV auto-vectorization

From: Ju-Zhe Zhong This patch adds sanity tests for basic enabling auto-vectorization. We should make sure compiler enable auto-vectorization strictly according to '-march' For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization. Since SEW = 64 RVV instructions are illegal ins

Re: [PATCH] [i386] Support type _Float16/__bf16 independent of SSE2.

LLM, machine learning and AI likes coding with data types that are weird, float16, bf16, 8 bit float and 4 bit floats. Longer term, would be nice to natively support these everywhere. Would be nice to trial run them in the compiler, sort it all out, so that the implementation experience can driv

Re: [PATCH 0/3] RISC-V: Basic enable RVV auto-vectorizaiton

Sorry for sending messy patches. Ignore those messy patches and these following patches are the real patches: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616222.html https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616225.html https://gcc.gnu.org/pipermail/gcc-patches/2023-April/6162

Re: [13 PATCH RFA] c++: fix 'unsigned __int128_t' semantics [PR108099]

On 4/19/23 11:26, Jakub Jelinek wrote: On Wed, Apr 19, 2023 at 11:20:09AM -0400, Jason Merrill wrote: When I was backporting the earlier 108099 patch I finally saw your comments on the PR about the meaning of this pattern with the patch being wrong (and a regression from 11). This fixes that re

Re: [PATCH] c++: bad ggc_free in try_class_unification [PR109556]

On 4/19/23 12:05, Patrick Palka wrote: On Wed, 19 Apr 2023, Patrick Palka wrote: Aside from correcting how try_class_unification copies multi-dimensional 'targs', r13-377-g3e948d645bc908 also made it ggc_free this copy as an optimization. But this is potentially wrong since the call to unify w

Re: [13 PATCH RFA] c++: fix 'unsigned __int128_t' semantics [PR108099]

On Wed, Apr 19, 2023 at 12:48:42PM -0400, Jason Merrill wrote: > On 4/19/23 11:26, Jakub Jelinek wrote: > > On Wed, Apr 19, 2023 at 11:20:09AM -0400, Jason Merrill wrote: > > > When I was backporting the earlier 108099 patch I finally saw your > > > comments on > > > the PR about the meaning of th

Re: [PATCH] c++: bad ggc_free in try_class_unification [PR109556]

On Wed, Apr 19, 2023 at 12:52:50PM -0400, Jason Merrill wrote: > On 4/19/23 12:05, Patrick Palka wrote: > > On Wed, 19 Apr 2023, Patrick Palka wrote: > > > > > Aside from correcting how try_class_unification copies multi-dimensional > > > 'targs', r13-377-g3e948d645bc908 also made it ggc_free this

Re: [PATCH v3] doc: Document order of define_peephole2 scanning

> From: Hans-Peter Nilsson > Date: Wed, 19 Apr 2023 06:06:27 +0200 > > Patch retracted, at least temporarily. My "understanding" > may be clouded by looking at an actual bug. Sigh. Mea culpa. I was looking at the result of one define_peephole2 and thinking it was due to another, and also tric

[PATCH v3 1/4] ree: Default ree pass for O2 and above for rs6000 target.

Hello All: This is the patch-1 for improving ree pass for rs6000 target. Bootstrapped and regtested on powerpc64-linux-gnu. Thanks & Regards Ajit ree: Improve ree pass for rs6000 target. Add ree pass as a default pass for rs6000 target. 2023-04-19 Ajit Kumar Agarwal

[PATCH v3 2/4] ree : Code movement to avoid adding prototype to improve ree pass for rs6000 target.

Hello All: This is the patch-2 to improve ree pass for rs6000 target. Bootstrapped and regtested on powerpc64-gnu-linux. Thanks & Regards Ajit ree: Improve ree pass for rs6000 target. For rs6000 target we see redundant zero and sign extension and done to improve ree pass

[PATCH v3 3/4] ree: Main functionality to Improve ree pass for rs6000 target

Hello All: This is patch-3 to improve ree pass for rs6000 target. Main functionality routines to imprve ree pass. Bootstrapped and regtested on powerpc64-gnu-linux. Thanks & Regards Ajit ree: Improve ree pass for rs6000 target. For rs6000 target we see redundant zero and sign

[PATCH v3 4/4] ree: Using ABI interfaces to improve ree pass for rs6000 target.

Hello All: This is patch-4 to improve ree pass for rs6000 target. Use ABI interfaces support. Bootstrapped and regtested on powerpc64-linux-gnu. Thanks & Regards Ajit ree: Improve ree pass for rs6000 target. For rs6000 target we see redundant zero and sign extension and

[COMMITTED 1/2] gcc: xtensa: add data alignment properties to dynconfig

gcc/ * config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New function. include/ * xtensa-dynconfig.h (xtensa_config_v4): New struct. (XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION) (XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)

[COMMITTED 2/2] gcc: xtensa: add -m[no-]strict-align option

gcc/ * config/xtensa/xtensa-opts.h: New header. * config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as xtensa_strict_align. * config/xtensa/xtensa.cc (xtensa_option_override): When -m[no-]strict-align is not specified in the command line set xtensa_

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