Hi all,
In this PR we fail to eliminate explicit &31 operations for variable shifts
such as in:
void
bar (int x[3], int y)
{
x[0] <<= (y & 31);
x[1] <<= (y & 31);
x[2] <<= (y & 31);
}
This is rejected by RTX costs that end up giving too high a cost for:
(set (reg:SI 96)
(ashift:SI (reg:SI 98)
(subreg:QI (and:SI (reg:SI 99)
(const_int 31 [0x1f])) 0)))
There is code to handle the AND-31 case in rtx costs, but it gets confused by
the subreg.
It's easy enough to fix by looking inside the subreg when costing the
expression.
While doing that I noticed that the ASHIFT case and the other shift-like cases
are almost identical
and we should just merge them. This code will only be used for valid insns
anyway, so the code after this
patch should do the Right Thing (TM) for all such shift cases.
With this patch there are no more "and wn, wn, 31" instructions left in the
testcase.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
PR target/108840
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Merge ASHIFT and
ROTATE, ROTATERT, LSHIFTRT, ASHIFTRT cases. Handle subregs in op1.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pr108840.c: New test.
reg-shift-and.patch
Description: reg-shift-and.patch
