Re: [PATCH] [PR68097] Try to avoid recursing for floats in tree_*_nonnegative_warnv_p.

On Wed, Nov 16, 2022 at 6:38 PM Aldy Hernandez wrote: > > > > On 11/16/22 17:04, Richard Biener wrote: > > On Tue, Nov 15, 2022 at 11:46 AM Aldy Hernandez wrote: > >> > >> > >> > >> On 11/15/22 08:15, Richard Biener wrote: > >>> On Mon, Nov 14, 2022 at 8:05 PM Aldy Hernandez wrote: > >

Re: [PATCH 1/2] symtab: also change RTL decl name

Hi Honza, Ping. Regtests cleanly for c,fortran,c++,ada,d,go,lto,objc,obj-c++ Ok? I'd need this for attribute target_clones for the Fortran FE. thanks, On Wed, 9 Nov 2022 20:02:24 +0100 Bernhard Reutner-Fischer wrote: > We were changing the ASSEMBLER_NAME of the function decl > but not the name

Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector

On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford wrote: > > Tamar Christina writes: > >> -Original Message- > >> From: Hongtao Liu > >> Sent: Tuesday, November 15, 2022 9:37 AM > >> To: Tamar Christina > >> Cc: Richard Sandiford ; Tamar Christina via > >> Gcc-patches ; nd ; > >> rguent

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On Tue, 15 Nov 2022 18:52:41 -0500 Jason Merrill wrote: > On 11/12/22 13:45, Bernhard Reutner-Fischer wrote: > > gcc/cp/ChangeLog: > > > > * decl.cc (start_function): Set the result decl source location to > > the location of the typespec. > > > > --- > > Bootstrapped and regtested on x

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

On Thu, 17 Nov 2022, 06:30 Daniel Krügler via Libstdc++, < libstd...@gcc.gnu.org> wrote: > Am Mi., 16. Nov. 2022 um 22:00 Uhr schrieb Jonathan Wakely via > Libstdc++ : > > > > Tested x86_64-linux. Pushed to trunk. > > > > -- >8 -- > > > > We can use an array instead of a std::vector, and we can av

[PATCH] c++, v3: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Wed, Nov 16, 2022 at 03:26:32PM -0500, Jason Merrill wrote: > On 11/16/22 09:46, Jakub Jelinek wrote: > > On Wed, Nov 16, 2022 at 09:33:27AM -0500, Jason Merrill wrote: > > > > and at that point I fear decl_maybe_constant_var_p will not work > > > > properly. Shall this hunk be moved somewhere

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

Am Do., 17. Nov. 2022 um 10:07 Uhr schrieb Jonathan Wakely : > > > > On Thu, 17 Nov 2022, 06:30 Daniel Krügler via Libstdc++, > wrote: >> >> Am Mi., 16. Nov. 2022 um 22:00 Uhr schrieb Jonathan Wakely via >> Libstdc++ : >> > >> > Tested x86_64-linux. Pushed to trunk. >> > >> > -- >8 -- >> > >> > W

Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector

Hongtao Liu writes: > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford > wrote: >> >> Tamar Christina writes: >> >> -Original Message- >> >> From: Hongtao Liu >> >> Sent: Tuesday, November 15, 2022 9:37 AM >> >> To: Tamar Christina >> >> Cc: Richard Sandiford ; Tamar Christina via >>

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

On Thu, 17 Nov 2022 at 09:25, Daniel Krügler wrote: > Am Do., 17. Nov. 2022 um 10:07 Uhr schrieb Jonathan Wakely > : > > > > > > > > On Thu, 17 Nov 2022, 06:30 Daniel Krügler via Libstdc++, < > libstd...@gcc.gnu.org> wrote: > >> > >> Am Mi., 16. Nov. 2022 um 22:00 Uhr schrieb Jonathan Wakely via

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

On Thu, 17 Nov 2022 at 09:47, Jonathan Wakely wrote: > > > On Thu, 17 Nov 2022 at 09:25, Daniel Krügler > wrote: > >> Am Do., 17. Nov. 2022 um 10:07 Uhr schrieb Jonathan Wakely >> : >> > >> > >> > >> > On Thu, 17 Nov 2022, 06:30 Daniel Krügler via Libstdc++, < >> libstd...@gcc.gnu.org> wrote: >>

[PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

2022-11-17 Yixuan Chen * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. --- gcc/testsuite/gcc.dg/pr25521.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/t

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

Am Do., 17. Nov. 2022 um 10:48 Uhr schrieb Jonathan Wakely : > > > > On Thu, 17 Nov 2022 at 09:47, Jonathan Wakely wrote: >> >> >> >> On Thu, 17 Nov 2022 at 09:25, Daniel Krügler >> wrote: >>> >>> Am Do., 17. Nov. 2022 um 10:07 Uhr schrieb Jonathan Wakely >>> : >>> > >>> > >>> > >>> > On Thu, 17

[PATCH v4] LoongArch: Optimize immediate load.

v1 -> v2: 1. Change the code format. 2. Fix bugs in the code. v2 -> v3: Modifying a code implementation of an undefined behavior. v3 -> v4: Move the part of the immediate number decomposition from expand pass to split pass. Both regression tests and spec2006 passed. The problem mentioned in the

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

On Thu, 17 Nov 2022 at 11:57, Daniel Krügler via Libstdc++ wrote: > > Do you really want me to stop working on the missing time zone support to > > test and commit that change? > > I do not. I was reviewing and hoping to make a useful comment. Looks like someone's crunching to make a stage3 dea

Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector

On Thu, Nov 17, 2022 at 5:39 PM Richard Sandiford wrote: > > Hongtao Liu writes: > > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford > > wrote: > >> > >> Tamar Christina writes: > >> >> -Original Message- > >> >> From: Hongtao Liu > >> >> Sent: Tuesday, November 15, 2022 9:37 AM > >>

Re: [committed] libstdc++: Improve performance of chrono::utc_clock::now()

On Thu, 17 Nov 2022 at 09:57, Daniel Krügler wrote: > Am Do., 17. Nov. 2022 um 10:48 Uhr schrieb Jonathan Wakely < > jwak...@redhat.com>: > > > > > > > > On Thu, 17 Nov 2022 at 09:47, Jonathan Wakely > wrote: > >> > >> > >> > >> On Thu, 17 Nov 2022 at 09:25, Daniel Krügler > wrote: > >>> > >>>

[PATCH v3] Enable shrink wrapping for the RISC-V target.

This commit implements the target macros (TARGET_SHRINK_WRAP_*) that enable separate shrink wrapping for function prologues/epilogues in RISC-V. Tested against SPEC CPU 2017, this change always has a net-positive effect on the dynamic instruction count. See the following table for the breakdown o

Re: [PATCH] Enable shrink wrapping for the RISC-V target.

On Thu, Nov 17, 2022 at 4:09 AM Jeff Law wrote: > > > On 11/16/22 03:26, Manolis Tsamis wrote: > > On Sun, Nov 13, 2022 at 3:33 AM Jeff Law via Gcc-patches > > wrote: > >> > >> On 11/7/22 15:07, Palmer Dabbelt wrote: > >>> On Thu, 03 Nov 2022 15:23:28 PDT (-0700), j...@ventanamicro.com wrote: > >

RE: [PATCH 2/2] aarch64: Add support for widening LDAPR instructions

> -Original Message- > From: Richard Sandiford > Sent: Tuesday, November 15, 2022 6:05 PM > To: Andre Simoes Dias Vieira > Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; > Richard Earnshaw > Subject: Re: [PATCH 2/2] aarch64: Add support for widening LDAPR > instructions > > "Andre Viei

Re: [PATCH] Enable shrink wrapping for the RISC-V target.

v3 committed to master. Thanks! Philipp. On Thu, 17 Nov 2022 at 11:55, Manolis Tsamis wrote: > On Thu, Nov 17, 2022 at 4:09 AM Jeff Law wrote: > > > > > > On 11/16/22 03:26, Manolis Tsamis wrote: > > > On Sun, Nov 13, 2022 at 3:33 AM Jeff Law via Gcc-patches > > > wrote: > > >> > > >> On 11/7/

Re: [PATCHv2, rs6000] Enable have_cbranchcc4 on rs6000

On Thu, Nov 17, 2022 at 1:39 AM HAO CHEN GUI wrote: > Hi, > The patch enables have_cbrnachcc4 which is a flag in ifcvt.cc to > indicate if branch by CC bits is invalid or not. The new expand pattern > "cbranchcc4" is created which intend to match the pattern defined in > "*cbranch", "*cbranch_2

[PATCH v3] c++: Allow module name to be a single letter on Windows

v1 -> v2: Paths without "C:" part can still be absolute if they start with / or \ on Windows. v2 -> v3: Use alternative approach by having platform specific code in module.cc. Truth table for the new expression: c:\foo -> true c:/foo -> true /foo -> true \foo -> true c:foo

Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector

Hongtao Liu writes: > On Thu, Nov 17, 2022 at 5:39 PM Richard Sandiford > wrote: >> >> Hongtao Liu writes: >> > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford >> > wrote: >> >> >> >> Tamar Christina writes: >> >> >> -Original Message- >> >> >> From: Hongtao Liu >> >> >> Sent: Tuesd

Re: [PATCH] RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND

On 11/10/22 14:36, Philipp Tomsich wrote: Add a split for cases where we can use two bclri (or one bclri and an andi) to clear two bits. gcc/ChangeLog: * config/riscv/bitmanip.md (*bclri_nottwobits): New pattern. (*bclridisi_nottwobits): New pattern, handling the sign-bit.

Re: [PATCH v2] match.pd: rewrite select to branchless expression

On 11/11/22 06:00, Michael Collison wrote: Hi Prathamesh, It is my understanding that INTEGRAL_TYPE_P applies to the other integer types you mentioned (chart, short, long). In fact the test function that motivated this match has a mixture of char and short and does not restrict matching.

Re: [PATCH] c++, v3: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On 11/17/22 04:13, Jakub Jelinek wrote: On Wed, Nov 16, 2022 at 03:26:32PM -0500, Jason Merrill wrote: On 11/16/22 09:46, Jakub Jelinek wrote: On Wed, Nov 16, 2022 at 09:33:27AM -0500, Jason Merrill wrote: and at that point I fear decl_maybe_constant_var_p will not work properly. Shall this h

Re: [PATCH] RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND

On Thu, 17 Nov 2022 at 15:30, Jeff Law wrote: > > > On 11/10/22 14:36, Philipp Tomsich wrote: > > Add a split for cases where we can use two bclri (or one bclri and an > > andi) to clear two bits. > > > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md (*bclri_nottwobits): New pattern. > >

Re: [PATCH] RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1"

On 11/8/22 12:55, Philipp Tomsich wrote: Consider creating a polarity-reversed mask from a set-bit (i.e., if the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb, this can be expressed as bexti, followed by an addi of minus-one. To enable the combiner to discover this opportunit

Re: [PATCH] RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND

On 11/17/22 07:43, Philipp Tomsich wrote: On Thu, 17 Nov 2022 at 15:30, Jeff Law wrote: On 11/10/22 14:36, Philipp Tomsich wrote: Add a split for cases where we can use two bclri (or one bclri and an andi) to clear two bits. gcc/ChangeLog: * config/riscv/bitmanip.md (*bclri_nottwob

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On 11/17/22 03:56, Bernhard Reutner-Fischer wrote: On Tue, 15 Nov 2022 18:52:41 -0500 Jason Merrill wrote: On 11/12/22 13:45, Bernhard Reutner-Fischer wrote: gcc/cp/ChangeLog: * decl.cc (start_function): Set the result decl source location to the location of the typespec. --

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On 11/13/22 13:48, Philipp Tomsich wrote: Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." that can be expressed as bexti + bexti + andn. gcc/ChangeLog: * config/riscv/bitmanip.md (*branch_mask_twobits_equals_singlebit): Handle "if ((a & T) == C)"

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 15:58, Jeff Law wrote: > > > On 11/13/22 13:48, Philipp Tomsich wrote: > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > > that can be expressed as bexti + bexti + andn. > > > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md > > (*b

Re: [PATCH] RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1"

Committed to master. Thanks! Philipp. On Thu, 17 Nov 2022 at 15:43, Jeff Law wrote: > > > On 11/8/22 12:55, Philipp Tomsich wrote: > > Consider creating a polarity-reversed mask from a set-bit (i.e., if > > the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb, > > this can be expre

Re: [PATCH] c: fix ICE with -fanalyzer and -Wunused-macros [PR107711]

On Wed, Nov 16, 2022 at 10:05:30PM -0500, David Malcolm wrote: > PR analyzer/107711 reports an ICE since r13-4073-gd8aba860b34203 with > the combination of -fanalyzer and -Wunused-macros. > > The issue is that in c_translation_unit::consider_macro's call to > cpp_create_reader I was passing "ident

Re: [PATCH] RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND

Applied to master. Thanks! Philipp. On Thu, 17 Nov 2022 at 15:30, Jeff Law wrote: > > > On 11/10/22 14:36, Philipp Tomsich wrote: > > Add a split for cases where we can use two bclri (or one bclri and an > > andi) to clear two bits. > > > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md

[PATCH 02/35] arm: fix 'vmsr' spacing and register capitalization

gcc/ChangeLog: * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix 'vmsr' spacing and reg capitalization. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Update test. * gcc.target/arm/mve/intrinsics/vldr

[PATCH 03/35] arm: improve tests and fix vddupq*

gcc/ChangeLog: * config/arm/mve.md (mve_vddupq_u_insn): Fix 'vddup.u' spacing. (mve_vddupq_m_wb_u_insn): Likewise. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : L

[PATCH 04/35] arm: improve tests and fix vdwdupq*

gcc/ChangeLog: * config/arm/mve.md (mve_vdwdupq_m_wb_u_insn): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwd

[PATCH 10/35] arm: improve tests for vabavq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: * gcc.target/arm/mve/intrinsics/vabavq_p_u

[PATCH 05/35] arm: improve vidupq* tests

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewi

[PATCH 06/35] arm: improve tests and fix vdupq*

gcc/ChangeLog: * config/arm/mve.md (mve_vdupq_n_f) (mve_vdupq_n_, mve_vdupq_m_n_) (mve_vdupq_m_n_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likew

[PATCH 35/35] arm: improve tests for vsetq_lane*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewis

[PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk)

Hi all, this is the first patch series about improving the current MVE implementation and testsuite for: - Complete intrinsic implementation and coverage (the list of intrinsics is specified by [1]) - Verifying all instructions supposedly emitted by each intrinsic - Verifying register usage - F

[PATCH 31/35] arm: improve tests for vqrdmlashq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: --- .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 34 ++- .../arm/mve

[PATCH 20/35] arm: improve tests for vfmasq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. --- .../arm/mve/intrinsics/vfmasq_m_n_f16.c | 50 --- .../arm/mve/intrinsics/vfmasq_m_n_f32.c | 50 +

[PATCH 12/35] arm: improve tests and fix vabsq*

gcc/ChangeLog: * config/arm/mve.md (mve_vabsq_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.

[PATCH 11/35] arm: improve tests for vabdq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. * gcc

[PATCH 16/35] arm: Add integer vector overloading of vsubq_x instrinsic

From: Stam Markianos-Wright In the past we had only defined the vsubq_x generic overload of the vsubq_x_* intrinsics for float vector types. This would cause them to fall back to the `__ARM_undef` failure state if they was called through the generic version. This patch simply adds these overload

[PATCH 27/35] arm: improve tests for vqaddq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise

[PATCH 33/35] arm: improve tests and fix vrmlaldavhaq*

gcc/ChangeLog: * config/arm/mve.md (mve_vrmlaldavhq_v4si, mve_vrmlaldavhaq_v4si): Fix spacing vs tabs. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. ---

[PATCH 24/35] arm: improve tests for vmladavaq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Lik

[PATCH 23/35] arm: improve tests for viwdupq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Li

[PATCH 19/35] arm: improve tests and fix vsubq*

gcc/ChangeLog: * config/arm/mve.md (mve_vsubq_n_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.

[PATCH 30/35] arm: improve tests for vqrdmlahq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c

[PATCH 08/35] arm: improve tests for vmin*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.

[PATCH 22/35] arm: improve tests for vhsubq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise

[PATCH 25/35] arm: improve tests and fix vmlaldavaxq*

gcc/ChangeLog: * config/arm/mve.md (mve_vmlaldavaq_) (mve_vmlaldavaxq_s, mve_vmlaldavaxq_p_): Fix spacing vs tabs. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s3

[PATCH 28/35] arm: improve tests for vqdmlahq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Li

[PATCH 18/35] arm: improve tests for vmulq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. * gcc

[PATCH 34/35] arm: improve tests for vrshlq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewis

[PATCH 26/35] arm: improve tests for vmlasq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise

[PATCH 21/35] arm: improve tests for vhaddq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise

[PATCH 32/35] arm: improve tests for vqsubq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: * gcc.target/arm/mve/intrinsics/vq

[PATCH 29/35] arm: improve tests for vqdmul*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: L

[PATCH 09/35] arm: improve tests for vmax*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.

[PATCH 17/35] arm: improve tests and fix vadd*

gcc/ChangeLog: * config/arm/mve.md (mve_vaddlvq_p_v4si) (mve_vaddq_n_, mve_vaddvaq_) (mve_vaddlvaq_v4si, mve_vaddq_n_f) (mve_vaddlvaq_p_v4si, mve_vaddq, mve_vaddq_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vaddlvaq_p_

Re: [PATCH] [range-ops] Implement sqrt.

To go along with whatever magic we're gonna tack along to the range-ops sqrt implementation, here is another revision addressing the VARYING issue you pointed out. A few things... Instead of going through trees, I decided to call do_mpfr_arg1 directly. Let's not go the wide int <-> tree rat hole

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On 11/17/22 08:12, Philipp Tomsich wrote: This serves as an assertion only, as that case is non-sensical and will be optimized away by earlier passes (as "a & C == T" with C and T sharing no bits will always be false). IFAIK the preceding transforms should always clean such a check up, but we

[PATCH 01/35] arm: improve vcreateq* tests

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.

PING^2 [PATCH] testsuite: Windows paths use \ and not /

Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604896.html Ok for trunk? Kind regards, Torbjörn On 2022-11-02 19:16, Torbjorn SVENSSON wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604312.html Ok for trunk? Kind regards, Torbjörn On 2022-10-25

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

Hi Richard, > Can you go into more detail about: > >    Use :option:`-mdirect-extern-access` either in shared libraries or in >    executables, but not in both.  Protected symbols used both in a shared >    library and executable may cause linker errors or fail to work correctly > > If this is LLV

PING^2 [PATCH] cpp/remap: Only override if string matched

Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604898.html Ok for trunk? Kind regards, Torbjörn On 2022-11-02 19:21, Torbjorn SVENSSON wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604062.html Ok for trunk? Kind regards, Torbjörn On 2022-10-20

[PATCH 15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515]

From: Stam Markianos-Wright This patch adds explicit references to other float types to __ARM_mve_typeid in arm_mve.h. Resolves PR 107515: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107515 gcc/ChangeLog: PR 107515 * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types. ---

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 17:39, Jeff Law wrote: > > > On 11/17/22 08:12, Philipp Tomsich wrote: > > > > This serves as an assertion only, as that case is non-sensical and > > will be optimized away by earlier passes (as "a & C == T" with C and T > > sharing no bits will always be false). > > IFAIK t

[PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic

From: Stam Markianos-Wright It was observed that in tests `vaddq_m_n_[s/u][8/16/32].c`, the _Generic resolution would fall back to the `__ARM_undef` failure state. This is a regression since `dc39db873670bea8d8e655444387ceaa53a01a79` and `6bd4ce64eb48a72eca300cb52773e6101d646004`, but it previou

PING^5 [PATCH] testsuite: Verify that module-mapper is available

Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604895.html Ok for trunk? Kind regards, Torbjörn On 2022-11-02 19:13, Torbjorn SVENSSON wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602844.html Ok for trunk? Kind regards, Torbjörn On 2022-10-25

Re: [PATCH] [range-ops] Implement sqrt.

On 11/17/22 17:40, Aldy Hernandez wrote: To go along with whatever magic we're gonna tack along to the range-ops sqrt implementation, here is another revision addressing the VARYING issue you pointed out. A few things... Instead of going through trees, I decided to call do_mpfr_arg1 directly

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

Wilco Dijkstra writes: > Hi Richard, > >> Can you go into more detail about: >> >>Use :option:`-mdirect-extern-access` either in shared libraries or in >>executables, but not in both. Protected symbols used both in a shared >>library and executable may cause linker errors or fail to w

Re: [PATCH] [range-ops] Implement sqrt.

This may be DCE. DOM uses ranger through simplify_using_ranges::fold_cond() to fold the following conditional to false, because we know x_185 is a NAN: x_185 = __builtin_sqrtf (-1.0e+0); if (x_185 ord x_185) I believe we can do that, because there are no user observable effects. But DCE remove

Re: [PATCH] maintainer-scripts/gcc_release: compress xz in parallel

> On 8 Nov 2022, at 07:14, Sam James wrote: > > 1. This should speed up decompression for folks, as parallel xz > creates a different archive which can be decompressed in parallel. > > Note that this different method is enabled by default in a new > xz release coming shortly anyway (>= 5

[COMMITTED] [PR tree-optimization/107732] [range-ops] Handle attempt to abs() negatives.

The threader is creating a scenario where we are trying to solve: [NEGATIVES] = abs(x) While solving this we have an intermediate value of UNDEFINED because we have no positive numbers. But then we try to union the negative pair to the final result by querying the bounds. Since neither

[COMMITTED] Fix PR 107734: valgrind errors with sbitmap in match.pd

From: Andrew Pinski sbitmap is a simple bitmap and the memory allocated is not cleared on creation; you have to clear it or set it to all ones before using it. This is unlike bitmap which is a sparse bitmap and the entries are cleared as created. The code added in r13-4044-gdc95e1e9702f2f missed

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich wrote: > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > that can be expressed as bexti + bexti + andn. Can't you also handle if ((a & twobits) == 0) case doing a similar thing. That is: two bexti + and and then com

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, Nov 17, 2022 at 10:25 AM Andrew Pinski wrote: > > On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich > wrote: > > > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > > that can be expressed as bexti + bexti + andn. > > Can't you also handle if ((a & twobits) =

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

Am I wrong to worry that this will increase dynamic instruction count when used in a loop? The obvious code is more efficient when the constant loads can be hoisted out of a loop. Or does the cost model account for this somehow? On Sun, Nov 13, 2022 at 12:50 PM Philipp Tomsich wrote: > > Use Z

[PATCH] c++: constinit on pointer to function [PR104066]

[dcl.constinit]: "The constinit specifier shall be applied only to a declaration of a variable with static or thread storage duration." Thus, this ought to be OK: constinit void (*p)() = nullptr; but the error message I introduced when implementing constinit was not looking at funcdecl_p, so t

Re: [PATCH] c++, v3: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 09:42:18AM -0500, Jason Merrill wrote: > > --- gcc/cp/constexpr.cc.jj 2022-11-17 08:48:30.530357181 +0100 > > +++ gcc/cp/constexpr.cc 2022-11-17 09:56:50.479522863 +0100 > > @@ -7098,7 +7098,8 @@ cxx_eval_constant_expression (const cons > > && (TREE_STATIC (r) >

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > Am I wrong to worry that this will increase dynamic instruction count > when used in a loop? The obvious code is more efficient when the > constant loads can be hoisted out of a loop. Or does the cost model > account for this somehow? Wit

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, Nov 17, 2022 at 10:52 AM Philipp Tomsich wrote: > > On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > > > Am I wrong to worry that this will increase dynamic instruction count > > when used in a loop? The obvious code is more efficient when the > > constant loads can be hoisted ou

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 19:28, Andrew Pinski wrote: > > On Thu, Nov 17, 2022 at 10:25 AM Andrew Pinski wrote: > > > > On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich > > wrote: > > > > > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) > > > ..." > > > that can be expre

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > So... is the optimization wrong? Are we not allowed to substitute > that NAN if we know it's gonna happen? Should we also allow F F F F F > in the test? Or something else? This seems like the usual ambiguity about what transformation

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 19:56, Andrew Waterman wrote: > > On Thu, Nov 17, 2022 at 10:52 AM Philipp Tomsich > wrote: > > > > On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > > > > > Am I wrong to worry that this will increase dynamic instruction count > > > when used in a loop? The obviou

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On Thu, 17 Nov 2022 09:53:32 -0500 Jason Merrill wrote: > On 11/17/22 03:56, Bernhard Reutner-Fischer wrote: > > On Tue, 15 Nov 2022 18:52:41 -0500 > > Jason Merrill wrote: > > > >> On 11/12/22 13:45, Bernhard Reutner-Fischer wrote: > >>> gcc/cp/ChangeLog: > >>> > >>> * decl.cc (start_fun

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, Nov 17, 2022 at 06:59:45PM +, Joseph Myers wrote: > On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > > > So... is the optimization wrong? Are we not allowed to substitute > > that NAN if we know it's gonna happen? Should we also allow F F F F F > > in the test? Or someth

Re: [PATCH v2] tree-object-size: Support strndup and strdup

Ping! On 2022-11-04 08:48, Siddhesh Poyarekar wrote: Use string length of input to strdup to determine the usable size of the resulting object. Avoid doing the same for strndup since there's a chance that the input may be too large, resulting in an unnecessary overhead or worse, the input may n

Re: [Patch Arm] Fix PR 92999

On Fri, Nov 11, 2022 at 9:50 PM Ramana Radhakrishnan wrote: > > On Thu, Nov 10, 2022 at 7:46 PM Ramana Radhakrishnan > wrote: > > > > On Thu, Nov 10, 2022 at 6:03 PM Richard Earnshaw > > wrote: > > > > > > > > > > > > On 10/11/2022 17:21, Richard Earnshaw via Gcc-patches wrote: > > > > > > > > >

Re: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via Gcc-patches wrote: > > Hi, > > This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When > an exception is taken and "0xb5" instruction is encounter during runtime > stack-unwinding, we use effective vsp as modifier in po

[PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 07:42:40PM +0100, Jakub Jelinek via Gcc-patches wrote: > I thought for older C++ this is to catch > void > foo () > { > constexpr int a = ({ static constexpr int b = 2; b; }); > } > and for C++23 the only 3 spots that diagnose those. > But perhaps for C++20 or older we can

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, 17 Nov 2022, Jakub Jelinek via Gcc-patches wrote: > On Thu, Nov 17, 2022 at 06:59:45PM +, Joseph Myers wrote: > > On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > > > > > So... is the optimization wrong? Are we not allowed to substitute > > > that NAN if we know it's gonn

[PATCH] Fortran: reject NULL actual argument without explicit interface [PR107576]

Dear all, one cannot pass a NULL actual argument to a procedure without an explicit interface. This is detected and reported by NAG and Intel. (Cray accepts this silently, and some other brands ICE.) The testcase by Gerhard even tricked gfortran into inconsistent behavior which could lead to an

  1   2   >