Committed, thanks !
On Sun, Nov 6, 2022 at 1:57 AM wrote:
>
> From: Ju-Zhe Zhong
>
> This patch support RVV scalable register spilling.
> prologue && epilogue handling pick up prototype from Monk Chiang
> .
> Co-authored-by: Monk Chiang
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc
Hi,
When assigning a struct parameter to another variable, or loading a
memory block to a struct var (especially for return value),
Now, "block move" would be used during expand the assignment. And
the "block move" may use a type/mode different from the mode which
is accessing the var. e.g. on ppc
Hi Gerald,
On 10.11.22 20:24, Gerald Pfeifer wrote:
On Thu, 10 Nov 2022, Martin Liška wrote:
We noticed we'll need the old /install to be available for redirect.
Gerald, can you please put it somewhere under /install-prev, or
something similar?
I'm afraid I am confused now. Based on your orig
On 11/11/22 09:40, Tobias Burnus wrote:
> However, others might have different ideas. Note that this was discussed in
> the thread "Links to web pages are broken."
Yes, please discuss this further in the aforementioned thread.
I do support the Richi's idea about using a new URL for the new Sphin
On Thu, Nov 10, 2022 at 08:20:06PM +0100, Jakub Jelinek via Gcc-patches wrote:
> This made me think about it some more and I'll need to play around with it
> some more, perhaps the right thing is similarly to what I've attached for
> division to handle special cases upfront and call frange_arithmet
From: Lili Cui
Hi Hontao,
This patch is to enable 256 move by pieces for ALDERLAKE and AVX2.
Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
OK for master?
gcc/Changelog:
* config/i386/x86-tune.def
(X86_TUNE_AVX256_MOVE_BY_PIECES): Add alderlake and avx2.
Hi!
Here is the floating point division fold_range implementation,
as I wrote in the last mail, we could outline some of the common parts
into static methods with descriptive names and share them between
foperator_div and foperator_mult.
Bootstrapped/regtested on top of the earlier version of the
On 11.11.22 09:50, Martin Liška wrote:
I do support the Richi's idea about using a new URL for the new Sphinx
documentation
while keeping the older Texinfo documentation under /onlinedocs and /install
If we do so and those become then static files: Can we put some
disclaimer at the top of all
On Fri, 11 Nov 2022, Jiufu Guo wrote:
> Hi,
>
> When assigning a struct parameter to another variable, or loading a
> memory block to a struct var (especially for return value),
> Now, "block move" would be used during expand the assignment. And
> the "block move" may use a type/mode different fr
On 11/10/22 20:20, Jakub Jelinek wrote:
On Thu, Nov 10, 2022 at 03:50:47PM +0100, Aldy Hernandez wrote:
@@ -1908,6 +1910,123 @@ class foperator_minus : public range_ope
}
} fop_minus;
+/* Wrapper around frange_arithmetics, that computes the result
+ if inexact rounded to both direct
On Fri, Nov 11, 2022 at 09:52:53AM +0100, Jakub Jelinek via Gcc-patches wrote:
> Ok, here is the patch rewritten in the foperator_div style, with special
> cases handled first and then the ordinary cases without problematic cases.
> I guess if/once we have a plugin testing infrastructure, we could
On 11/11/22 11:01, Jakub Jelinek wrote:
On Fri, Nov 11, 2022 at 09:52:53AM +0100, Jakub Jelinek via Gcc-patches wrote:
Ok, here is the patch rewritten in the foperator_div style, with special
cases handled first and then the ordinary cases without problematic cases.
I guess if/once we have a
On Fri, Nov 11, 2022 at 10:12 AM Tobias Burnus wrote:
>
> On 11.11.22 09:50, Martin Liška wrote:
> > I do support the Richi's idea about using a new URL for the new Sphinx
> > documentation
> > while keeping the older Texinfo documentation under /onlinedocs and /install
>
> If we do so and those
Hi all,
This patch adds codegen for FEAT_CSSC from the 2022 Architecture extensions.
It fits various existing optabs in GCC quite well.
There are instructions for scalar signed/unsigned min/max, abs, ctz, popcount.
We have expanders for these already, so they are wired up to emit single-insn
patte
On 11/11/22 11:18, Richard Biener wrote:
> On Fri, Nov 11, 2022 at 10:12 AM Tobias Burnus
> wrote:
>>
>> On 11.11.22 09:50, Martin Liška wrote:
>>> I do support the Richi's idea about using a new URL for the new Sphinx
>>> documentation
>>> while keeping the older Texinfo documentation under /on
Hi Richard,
On 11.11.22 11:18, Richard Bienr wrote:
Note I think we can "remove" the install/ and onlinedocs/ _landing_ pages
(index.html) but we should keep the actual content pages so old links keep
working. We can also replace the landing pages with a pointer to the new
documentation (or pl
On Fri, Nov 11, 2022 at 11:01:38AM +0100, Aldy Hernandez wrote:
> > I've tried following, but it suffers from various issues:
> > 1) we don't handle __builtin_signbit (whatever) == 0 (or != 0) as guarantee
> > that in the guarded code whatever has signbit 0 or 1
>
> We have a range-op entry fo
On Fri, Nov 11, 2022 at 11:12:01AM +0100, Aldy Hernandez wrote:
> > --- gcc/range-op-float.cc.jj2022-11-11 10:13:30.879410560 +0100
> > +++ gcc/range-op-float.cc 2022-11-11 10:55:57.602617289 +0100
> > @@ -1911,7 +1911,125 @@ class foperator_minus : public range_ope
> > } fop_minus;
> >
On 11/11/22 11:47, Jakub Jelinek wrote:
On Fri, Nov 11, 2022 at 11:01:38AM +0100, Aldy Hernandez wrote:
I've tried following, but it suffers from various issues:
1) we don't handle __builtin_signbit (whatever) == 0 (or != 0) as guarantee
that in the guarded code whatever has signbit 0 or
Hi,
Below is a patch to fix std::string in constexpr contexts on Clang. This
was originally fixed in the commits attached to PR103295, but a later
commit 98a0d72a seems to have mistakenly undone this.
Tested on x86_64-linux. Verified using clang-14 and clang-15 that the
fix works. I haven't added
On Wed, Nov 09, 2022 at 04:43:56PM +0100, Aldy Hernandez wrote:
> On Wed, Nov 9, 2022 at 3:58 PM Jakub Jelinek wrote:
> >
> > On Wed, Nov 09, 2022 at 10:02:46AM +0100, Aldy Hernandez wrote:
> > > We can implement the op[12]_range entries for plus and minus in terms
> > > of each other. These are
Hi,
This patch adds support for Cortex-A715 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 CPU.
Hi,
This patch adds support for Cortex-X1C CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X1C CPU.
*
Noticed that the documentation build can stuck on a machine with
many cores (160) and I identified a real sphinx problem:
https://github.com/sphinx-doc/sphinx/issues/10969
Note the parallel can help just for some manuals and it is not critical
for us.
ChangeLog:
* doc/Makefile: Disable -
Hi Prathamesh,
It is my understanding that INTEGRAL_TYPE_P applies to the other integer
types you mentioned (chart, short, long). In fact the test function that
motivated this match has a mixture of char and short and does not
restrict matching.
On 11/11/22 02:44, Prathamesh Kulkarni wrote:
gcc/testsuite ChangeLog:
2022-11-11 Oria Chen
* gcc/testsuite/gcc.dg/pr25521.c: Add compile option
"-msmall-data-limit=0" to avoid using .srodata section.
---
gcc/testsuite/gcc.dg/pr25521.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/p
LGTM,and I think it would be better to have a test example.
> From: zengxiao
>
> This patch makes R_RISCV_SUB6 conforms to riscv abi standard.
> R_RISCV_SUB6 only the lower 6 bits of the code are valid.
> The proposed specification which can be found in 8.5. Relocations of,
> https://github.c
Hi Srinath,
> -Original Message-
> From: Srinath Parvathaneni
> Sent: Friday, November 11, 2022 12:11 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Kyrylo Tkachov
>
> Subject: [PATCH][GCC] aarch64: Add support for Cortex-X1C CPU.
>
> Hi,
>
> This patch adds support for Cor
Apart from that, do not use leading .rst names in toctree.
ChangeLog:
* doc/indices-and-tables.rst: Rename Indexes to Indices.
gcc/jit/ChangeLog:
* doc/cp/index.rst: Remove trailing .rst in toctree.
* doc/cp/intro/index.rst: Likewise.
* doc/cp/topics/index.rst: L
The following enhances copy propagation of constants to also see
through simple operations like conversions but also operations with
otherwise constant operands. That's required to fulfill the promise
/* Copy propagation also copy-propagates constants, this is necessary
to forward
This is a series of patches to improve recognition of popcount and
clz/ctz idioms, along with some related fixes.
- Patches 1 and 8 are independent fixes or improvements.
- Patch 4 is a dependency of patch 5, as it improves the robustness of a
test that would otherwise begin failing.
- Patches 2
This prevents a null dereference error when outputing debug information
following an early exit from number_of_iterations_exit_assumptions.
gcc/ChangeLog:
* tree-ssa-loop-niter.cc (number_of_iterations_exit_assumptions):
Move at_stmt assignment.
--
diff --git a/gcc/tree-ssa-lo
Similarly to other manuals, we should include the page
in HTML builder.
What Ada folks think about it?
Thanks,
Martin
gcc/ada/ChangeLog:
* doc/gnat-style/index.rst: Add Indicies and Tables.
* doc/gnat_rm/index.rst: Likewise.
* doc/gnat_ugn/index.rst: Likewise.
*
On Mon, Oct 10, 2022 at 5:36 PM Gaius Mulley via Gcc-patches
wrote:
>
>
>
> This patch set contains the non machine generated changes found in /
> for example the language die and documentation changes. It also
> contains the changes to the top level build Makefile infastructure
> and the install
gcc/ChangeLog:
* tree-ssa-loop-niter.c (ssa_defined_by_minus_one_stmt_p): Move
(number_of_iterations_popcount): Move, and remove separate prototype.
--
diff --git a/gcc/tree-ssa-loop-niter.cc b/gcc/tree-ssa-loop-niter.cc
index
cdbb924216243ebcabe6c695698a4aee71882c49..c23643fd
Use bit-CCP to calculate bitmasks for all integer operators, instead
of the half-assed job we were doing with just a handful of operators.
This sets us up nicely for tracking known-one bitmasks in the next
release, as all we'll have to do is just store them in the irange.
All in all, this series
This patch adds a tree code to range_operator in order to known which
tree code to pass into bit-CCP.
Up to now range-ops has been free of tree details, with the exception
of the div entries which use a tree code to differentiate between
them. This is still the goal going forward, but this is a s
There is no need for a special tree code in the *DIV_EXPR entries, as
the parent class has one.
gcc/ChangeLog:
* range-op.cc (class operator_div): Remove tree code.
(operator_div::wi_op_overflows): Handle EXACT_DIV_EXPR as
TRUNC_DIV_EXPR.
---
gcc/range-op.cc | 21 ++--
All the work for keeping the maybe nonzero masks up to date is being
done by the bit-CCP code now. Any bitmask inherent in the range that
range-ops may have calculated has no extra information, so the
intersection is unnecessary.
gcc/ChangeLog:
* range-op.cc (update_known_bitmask): Avoid
Remove some specialized fold_range methods that were merely setting
maybe nonzero masks, as these are now subsumed by the generic version.
gcc/ChangeLog:
* range-op.cc (operator_mult::fold_range): Remove.
(operator_div::fold_range): Remove.
(operator_bitwise_and): Remove.
On Mon, Oct 10, 2022 at 5:34 PM Gaius Mulley via Gcc-patches
wrote:
>
>
>
> The makefile fragment for modula2 which builds the gm2 driver and cc1gm2.
>
>
> --8<--8<--8<--8<--8<--8<
> diff -ruw /dev/null gcc-git-devel-modula2/gcc/m2/Make-lang.in
> ---
This includes various changes to improve clarity, and to enable the code
to be more similar to the clz and ctz idiom recognition added in
subsequent patches.
We create new number_of_iterations_bitcount function, which will be used
to call the other bit-counting recognition functions added in subse
On Mon, Oct 10, 2022 at 5:32 PM Gaius Mulley via Gcc-patches
wrote:
>
>
> Here are the latest modula-2 front end patches for review.
> The status of the patches and their contents are also contained at:
>
>https://splendidisolation.ddns.net/public/modula2/patchsummary.html
>
> where they are a
On Tue, Jul 26, 2022 at 1:18 PM Richard Biener via Gcc-patches
wrote:
>
> The following improves on the fix for PR105142 which restricted the
> expression lookup used for maybe_fold_comparisons_from_match_pd to
> avoid picking up flow-sensitive info for use in places where guarding
> conditions do
Add support for AArch64 LSE and LSE2 to libatomic. Disable outline atomics,
and use LSE ifuncs for 1-8 byte atomics and LSE2 ifuncs for 16-byte atomics.
On Neoverse V1, 16-byte atomics are ~4x faster due to avoiding locks.
Note this is safe since we swap all 16-byte atomics using the same ifunc,
On 11/11/22 12:50, Jakub Jelinek wrote:
On Wed, Nov 09, 2022 at 04:43:56PM +0100, Aldy Hernandez wrote:
On Wed, Nov 9, 2022 at 3:58 PM Jakub Jelinek wrote:
On Wed, Nov 09, 2022 at 10:02:46AM +0100, Aldy Hernandez wrote:
We can implement the op[12]_range entries for plus and minus in terms
Hi Srinath,
> -Original Message-
> From: Srinath Parvathaneni
> Sent: Friday, November 11, 2022 11:58 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Kyrylo Tkachov
>
> Subject: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
>
> Hi,
>
> This patch adds support for Co
On 11/11/22 11:01, Jakub Jelinek wrote:
On Fri, Nov 11, 2022 at 09:52:53AM +0100, Jakub Jelinek via Gcc-patches wrote:
Ok, here is the patch rewritten in the foperator_div style, with special
cases handled first and then the ordinary cases without problematic cases.
I guess if/once we have a
Hi,
>
> ...can we use expand_vec_perm_const here? It will try the constant
> expansion first, which is the preferred order. It also has a few variations
> up
> its sleeve.
>
We can, however it this function seems to be incorrectly assuming it can always
Convert the input mode to a QI vector
The following fixes a wrongly typed variable causing an ICE.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/107554
* tree-ssa-strlen.cc (strlen_pass::count_nonzero_bytes):
Use unsigned HOST_WIDE_INT type for the strlen.
* gcc.dg/
Hi,
> This name might cause confusion with the SVE iterators, where FULL means
> "every bit of the register is used". How about something like VMOVE
> instead?
>
> With this change, I guess VALL_F16 represents "The set of all modes for
> which the vld1 intrinsics are provided" and VMOVE or what
Hi,
> > --- a/gcc/config/aarch64/aarch64-simd.md
> > +++ b/gcc/config/aarch64/aarch64-simd.md
> > @@ -4259,7 +4259,7 @@ (define_insn
> "*aarch64_get_lane_zero_extend"
> > ;; Extracting lane zero is split into a simple move when it is
> > between SIMD ;; registers or a store.
> > (define_insn_an
Hi All,
While writing a patch series I started getting incorrect codegen out from
VEC_PERM on partial struct types.
It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS
implementation has a slight bug in it. The hook only checked for SIMD to
Partial but never Partial to
Hi All,
The current i386 implementation of the TARGET_CAN_CHANGE_MODE_CLASS is currently
not useful before re-alloc.
In particular before regalloc optimization passes query the hook using ALL_REGS,
but because of the
if (MAYBE_FLOAT_CLASS_P (regclass))
return false;
The hook returns fal
Add a new option -mdirect-extern-access similar to other targets. This removes
GOT indirections on external symbols with -fPIE, resulting in significantly
better code quality. With -fPIC it only affects protected symbols, allowing
for more efficient shared libraries which can be linked with stand
On 11/11/22 09:22, Aldy Hernandez wrote:
A return of false means the operation is not handled, similar to what
the default operators defined at the top of range-op*.cc do. The
caller (gori?) is free to disregard the range altogether. In practice
this means VARYING, so you're getting the
Hi,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Friday, November 11, 2022 2:24 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
>
> Hi Srinath,
>
> > -Original Message---
Hi,
This patch adds support for Cortex-X3 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X3 CPU.
* c
This patch adds TR11 to the history of OpenMP releases – and it does an
update of the implementation status.
OK?
Tobias
PS: The implementation-status changes were lying around in that file for
a while. I think both the GCC 13 release notes and this file needs some
update for more recent chan
On Fri, Nov 11, 2022 at 4:34 AM Martin Liška wrote:
>
> Noticed that the documentation build can stuck on a machine with
> many cores (160) and I identified a real sphinx problem:
> https://github.com/sphinx-doc/sphinx/issues/10969
>
> Note the parallel can help just for some manuals and it is not
I was processing the transitive inferred ranges in fold_stmt when it was
the final statement in the block. the substitute_and_fold engine
actually does a bit of work before calling fold_stmt. this patch moves
the check to pre_fold_stmt instead so it gets done before the final
statement in the
The prologue/epilogue pass allows the prologue sequence
to contain jumps. The sequence is then partitioned into
basic blocks using find_many_sub_basic_blocks.
This patch treats epilogues in the same way. It's needed for
a follow-on aarch64 patch that adds conditional code to both
the prologue an
Arm's SME adds a new processor mode called streaming mode.
This mode enables some new (matrix-oriented) instructions and
disables several existing groups of instructions, such as most
Advanced SIMD vector instructions and a much smaller set of SVE
instructions. It can also change the current vecto
Epilogues for sibling calls are generated using the
sibcall_epilogue pattern. One disadvantage of this approach
is that the target doesn't know which call the epilogue is for,
even though the code that generates the pattern has the call
to hand.
Although call instructions are currently rtxes, and
We have the following two hooks into the call expansion code:
- TARGET_CALL_ARGS is called for each argument before arguments
are moved into hard registers.
- TARGET_END_CALL_ARGS is called after the end of the call
sequence (specifically, after any return value has been
moved to a pseudo).
Hi!
The following patch on top of Marek's P2448 PR106649 patch
(mainly because that patch implements the previous __cpp_constexpr
feature test macro bump so this can't go in earlier; OT,
P2280R4 doesn't have any feature test macro?) implements this
simple paper.
Ok for trunk if it passes bootstra
On Fri, 11 Nov 2022 at 11:23, Nathaniel Shead via Libstdc++
wrote:
>
> Hi,
>
> Below is a patch to fix std::string in constexpr contexts on Clang. This
> was originally fixed in the commits attached to PR103295, but a later
> commit 98a0d72a seems to have mistakenly undone this.
>
> Tested on x86_
On Mon, 7 Nov 2022 at 13:51, Jonathan Wakely wrote:
>
> On Mon, 7 Nov 2022 at 13:33, LIU Hao wrote:
> >
> > 在 2022-11-07 20:57, Jonathan Wakely 写道:
> > > It would be a lot nicer if playback::context met the C++ Lockable
> > > requirements, and playback::context::compile () could just take a
> > > s
> Similarly to other manuals, we should include the page
> in HTML builder.
>
> What Ada folks think about it?
The latest changes have broken our build of the Ada doc at AdaCore so until
further notice, please do not make any additional changes to the Ada doc while
we review in details all t
Arm's SME has an array called ZA that for inline asm purposes
is effectively a form of special-purpose memory. It doesn't
have an associated storage type and so can't be passed and
returned in normal C/C++ objects.
We'd therefore like "za" in a clobber list to mean that an inline
asm can read fro
We didn't previously use SVE's RDVL instruction, since the CNT*
forms are preferred and provide most of the range. However,
there are some cases that RDVL can handle and CNT* can't,
and using RDVL-like instructions becomes important for SME.
Tested on aarch64-linux-gnu. I plan to apply this soon
Hi all,
This is the 2/2 patch that contains the functional changes needed
for MVE Tail Predicated Low Overhead Loops. See my previous email
for a general introduction of MVE LOLs.
This support is added through the already existing loop-doloop
mechanisms that are used for non-MVE dls/le looping.
Tested x86_64-linux and x86_64-w64-ming32 (via Wine).
Pushed to trunk. This needs to be backported too.
-- >8 --
In commit r9-7381-g91756c4abc1757 I changed filesystem::path to use
std::codecvt for conversions from all wide
strings to UTF-8, instead of using std::codecvt_utf8. This was
done beca
On Fri, 11 Nov 2022, Jonathan Wakely via Libstdc++ wrote:
> On Fri, 11 Nov 2022 at 11:23, Nathaniel Shead via Libstdc++
> wrote:
> >
> > Hi,
> >
> > Below is a patch to fix std::string in constexpr contexts on Clang. This
> > was originally fixed in the commits attached to PR103295, but a later
>
On Fri, 11 Nov 2022 at 17:55, Patrick Palka wrote:
>
> On Fri, 11 Nov 2022, Jonathan Wakely via Libstdc++ wrote:
>
> > On Fri, 11 Nov 2022 at 11:23, Nathaniel Shead via Libstdc++
> > wrote:
> > >
> > > Hi,
> > >
> > > Below is a patch to fix std::string in constexpr contexts on Clang. This
> > >
Currently we represent < and > with a closed interval. So < 3.0 is
represented as [-INF, +3.0]. This means 3.0 is included in the range,
and though not ideal, is conservatively correct. Jakub has found a
couple cases where properly representing < and > would help
optimizations and tests, and thi
On Fri, 11 Nov 2022 at 17:16, Jonathan Wakely wrote:
>
> On Mon, 7 Nov 2022 at 13:51, Jonathan Wakely wrote:
> >
> > On Mon, 7 Nov 2022 at 13:33, LIU Hao wrote:
> > >
> > > 在 2022-11-07 20:57, Jonathan Wakely 写道:
> > > > It would be a lot nicer if playback::context met the C++ Lockable
> > > > requ
The upcoming c[lt]z idiom recognition patch eliminates the need for a
brute force computation of the iteration count of these loops. The test
is intended to verify that ivcanon can determine the loop count when the
condition is given by a chain of constant computations.
We replace the constant ope
The commit r13-3706-gd0a492faa6478c for correcting the result of
__has_attribute(init_priority) causes a bootstrap failure on hppa64-hpux
because it assumes SUPPORTS_INIT_PRIORITY expands to a simple constant,
but on this target SUPPORTS_INIT_PRIORITY is defined as
#define SUPPORTS_INIT_PRIORITY
This recognises patterns of the form:
while (n) { n >>= 1 }
This patch results in improved (but still suboptimal) codegen:
foo (unsigned int b) {
int c = 0;
while (b) {
b >>= 1;
c++;
}
return c;
}
foo:
.LFB11:
.cfi_startproc
cbz w0, .L3
On Wed, Nov 9, 2022 at 1:49 AM Xi Ruoyao wrote:
>
> On Mon, 2022-11-07 at 20:36 -0800, Kevin Lee wrote:
> I "shamelessly copied" your idea in
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605456.html.
> During the review we found an issue.
>
> -fno-fp-int-builtin-inexact does not allo
gcc/ChangeLog:
*
doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst:
Add missing target attributes.
--
diff --git
a/gcc/doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst
b/g
On Fri, Nov 11, 2022 at 10:48 AM Patrick Palka via Gcc-patches
wrote:
>
> The commit r13-3706-gd0a492faa6478c for correcting the result of
> __has_attribute(init_priority) causes a bootstrap failure on hppa64-hpux
> because it assumes SUPPORTS_INIT_PRIORITY expands to a simple constant,
> but on t
This recognises the patterns of the form:
while (n & 1) { n >>= 1 }
Unfortunately there are currently two issues relating to this patch.
Firstly, simplify_using_initial_conditions does not recognise that
(n != 0) and ((n & 1) == 0) implies that ((n >> 1) != 0).
This preconditions arise
This requirement is enforced by a gcc_checking_assert in
record_estimate.
gcc/ChangeLog:
* tree-ssa-loop.h (tree_niter_desc): Update comment.
--
diff --git a/gcc/tree-ssa-loop.h b/gcc/tree-ssa-loop.h
index
6c70f795d171f22b3ed75873fec4920fea75255b..c24215be8822c31a05eaedcf4d3a26db0fea
Passes tests for all languages. Passes lapack tests.
So ready to be installed unless you have any issues. Oh... I should
write some tests..
Aldy
On Fri, Nov 11, 2022, 19:11 Aldy Hernandez wrote:
> Currently we represent < and > with a closed interval. So < 3.0 is
> represented as [-INF, +
Richard Biener writes:
> On Mon, Oct 10, 2022 at 5:36 PM Gaius Mulley via Gcc-patches
> wrote:
>>
>>
>>
>> This patch set contains the non machine generated changes found in /
>> for example the language die and documentation changes. It also
>> contains the changes to the top level build Makef
gcc/
PR target/107645
* config/m68k/predicates.md (symbolic_operand): Return false
when UNSPEC is under the CONST node.
---
Regtested with --enable-checking=all for target=m68k-linux-uclibc, no
new regressions compared to the compiler built without checking.
Ok for master?
This adjusts gimple-ranger::update_stmt (which inform the range engine
that a statement has changed under the covers. I was calculating the
statement using a fur_depend class instead of a fur_stmt. (FUR is Fold
Using Range)
The difference between the 2 is that a fur_depend will reigster any
On Fri, Nov 11, 2022 at 5:03 AM Oria Chen via Gcc-patches
wrote:
>
> gcc/testsuite ChangeLog:
>
> 2022-11-11 Oria Chen
>
> * gcc/testsuite/gcc.dg/pr25521.c: Add compile option
> "-msmall-data-limit=0" to avoid using .srodata section.
I noticed g++.dg/cpp0x/constexpr-rom.C has some sli
On Fri, Nov 11, 2022 at 2:26 AM Kyrylo Tkachov via Gcc-patches
wrote:
>
> Hi all,
>
> This patch adds codegen for FEAT_CSSC from the 2022 Architecture extensions.
> It fits various existing optabs in GCC quite well.
> There are instructions for scalar signed/unsigned min/max, abs, ctz, popcount.
>
Non-const lvalue references can't bind to a temporary, so the
warning should not be emitted if we're initializing something of that
type. I'm not disabling the warning when the function itself returns
a non-const lvalue reference, that would regress at least
const int &r = std::any_cast(std::an
On Fri, 11 Nov 2022 11:56:08 PST (-0800), gcc-patches@gcc.gnu.org wrote:
On Fri, Nov 11, 2022 at 5:03 AM Oria Chen via Gcc-patches
wrote:
gcc/testsuite ChangeLog:
2022-11-11 Oria Chen
* gcc/testsuite/gcc.dg/pr25521.c: Add compile option
"-msmall-data-limit=0" to avoid using .srod
On Tue, 8 Nov 2022, Martin Liška wrote:
> After the migration, people should be able to build (and install) GCC
> even if they miss Sphinx (similar happens now if you miss makeinfo).
My nightly *install* (not build) on amd64-unknown-freebsd12.2 broke
(from what I can tell due to this - it's bee
On 11/11/22 06:30, Jonathan Wakely via Gcc-patches wrote:
As discussed in the PR, this makes it three times faster to construct
iostreams objects.
Tested x86_64-linux. Pushed to trunk.
I haven't yet tried to track down what's going on, but with various
versions of Clang (e.g. clang-15.0.4-1.f
On 11/9/22 8:44 PM, Michael Meissner via Gcc-patches wrote:
> + /* For now, make -mtune=future the same as -mtune=power10. */
> + if (rs6000_tune == PROCESSOR_FUTURE)
> +rs6000_tune = PROCESSOR_POWER10;
This comment matches the code...
> + /* Some future processor. For now, just use powe
On 11/11/22 13:52, Gerald Pfeifer wrote:
On Tue, 8 Nov 2022, Martin Liška wrote:
After the migration, people should be able to build (and install) GCC
even if they miss Sphinx (similar happens now if you miss makeinfo).
My nightly *install* (not build) on amd64-unknown-freebsd12.2 broke
(from
This patch adds a new -Wanalyzer-infinite-recursion warning to
-fanalyzer, which complains about certain cases of infinite recursion.
Specifically, when it detects recursion during its symbolic execution
of the user's code, it compares the state of memory to that at the
previous level of recursion
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r13-3913-g65752c1f7c41c5.
gcc/analyzer/ChangeLog:
* checker-path.h: Split out checker_event and its subclasses to...
* checker-event.h: ...this new header.
Signed-off-by: David Malcolm
---
gcc/anal
> On 8 Nov 2022, at 07:14, Sam James wrote:
>
> 1. This should speed up decompression for folks, as parallel xz
> creates a different archive which can be decompressed in parallel.
>
> Note that this different method is enabled by default in a new
> xz release coming shortly anyway (>= 5
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