Patch 3 extends the regex in some tests which scan the assembler output for
"nop". On MSP430, the nop instruction is an uppercase "NOP".
>From 6ad3780262543c5237e939ac14ac6294a2adc77b Mon Sep 17 00:00:00 2001
From: Jozef Lawrynowicz
Date: Tue, 6 Nov 2018 12:59:58 +
Subject: [PATCH 3/4] [TEST
Patch 4 fixes the calculation of USHRT_MAX in some tests, to prevent integer
overflow for targets where sizeof(short) == sizeof(int). i.e.
-#define USHRT_MAX (SHRT_MAX * 2 + 1)
+#define USHRT_MAX (SHRT_MAX * 2U + 1)
>From 6a6580c486a7705798c5a2c9898f46e7a319976b Mon Sep 17 00:00:00 2001
From:
Hi Richard,
On 11/08/2018 12:09 PM, Richard Biener wrote:
On Thu, Nov 8, 2018 at 12:02 PM Renlin Li wrote:
Hi all,
When allow-store-data-races is enabled, ifcvt would prefer to generated
conditional select and unconditional store to convert certain if statement
into:
_ifc_1 = val
_ifc_2 = A
Hi all,
As a follow up patch described here:
https://gcc.gnu.org/ml/gcc-patches/2018-10/msg02016.html
Mask/predicate type of data could be used as general data.
In sve ISA, we don't have operations which could directly extract element from a
predicate. The default code-gen for such use is in-e
On Wed, Nov 7, 2018 at 5:32 PM Jakub Jelinek wrote:
>
> On Wed, Nov 07, 2018 at 05:05:13PM -0500, Fritz Reese wrote:
>
> --- a/gcc/fortran/options.c
> +++ b/gcc/fortran/options.c
> @@ -32,6 +32,20 @@ along with GCC; see the file COPYING3. If not see
>
> gfc_option_t gfc_option;
>
> +#define _exp
Andi Kleen writes:
Ping!
> From: Andi Kleen
>
> Add builtins/intrinsics for PTWRITE. PTWRITE is a new instruction on Intel
> Gemini Lake/
> Goldmont Plus that allows to write values into the Processor Trace log. This
> allows
> very light weight instrumentation of programs.
>
> The intrinsics
Andi Kleen writes:
Ping!
> From: Andi Kleen
>
> When instrumenting programs using __fentry__ it is often useful
> to instrument the function return too. Traditionally this
> has been done by patching the return address on the stack
> frame on entry. However this is fairly complicated (trace
> f
Hi!
The OpenMP 5.0 specification, https://www.openmp.org/specifications/ ,
has been just released a few minutes ago and to celebrate that, I've merged
gomp-5_0-branch into trunk after bootstrapping/regtesting it on x86_64-linux and
i686-linux.
Because the amount of changes in OpenMP 5.0 is much b
Hi!
This is the gcc/testsuite/ part of the gomp-5_0-branch
merge to trunk I've just committed.
2018-11-08 Jakub Jelinek
* c-c++-common/gomp/atomic-17.c: New test.
* c-c++-common/gomp/atomic-18.c: New test.
* c-c++-common/gomp/atomic-19.c: New test.
* c-c++-comm
Hello!
> From: Andi Kleen
>
> Add builtins/intrinsics for PTWRITE. PTWRITE is a new instruction on Intel
> Gemini Lake/
> Goldmont Plus that allows to write values into the Processor Trace log. This
> allows
> very light weight instrumentation of programs.
>
> The intrinsics are compatible to i
This patch adds support for defining an alias for a CPU name that can
then be used in conjunction with the -mcpu option in the same way that
the primary name can be used. Aliases do not lead to a short-cut of
the feature options; they are literally an alternative name for the
core CPU.
The new en
This is an updated set of patches for the SIMD ABI on aarch64. I have
updated all of them to apply to ToT. The first two have no functional
changes from the last submittal. The last two are a reworking of what
used to be a single patch. I split it up into two parts and reworked
it to address co
This is a resubmission of patch 1 to support the Aarch64 SIMD ABI [1] in
GCC, it does not have any functional changes from the last submit.
The significant difference between the standard ARM ABI and the SIMD ABI
is that in the normal ABI a callee saves only the lower 64 bits of registers
V8-V15,
On 11/8/18 10:19 AM, Renlin Li wrote:
>> Yes, this is the problem. We see from the dump, that r2040 does not
>> conflict with
>> hard reg r1:
>>
>> ;; a2040(r1597,l0) conflicts:
>> ;; total conflict hard regs:
>> ;; conflict hard regs:
> I think you should look for axxx(r2040, ..)?
>
>
This is a patch 2 to support the Aarch64 SIMD ABI [1] in GCC.
It defines the TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN,
TARGET_SIMD_CLONE_ADJUST, and TARGET_SIMD_CLONE_USABLE macros
so that GCC can generate SIMD clones on aarch64.
Steve Ellcey
sell...@cavium.com
2018-11-08 Steve Ellcey
On Thu, Nov 08, 2018 at 12:09:33PM -0500, Fritz Reese wrote:
> I find "expand" a more helpful name than "set_bitflag_1" since it
> describes what the macro does. However, I don't think it makes too
> much of a difference so I'll follow your preference (but I'll use
> SET_BITFLAG2 since then the def
This is a patch 3 to support the Aarch64 SIMD ABI [1] in GCC.
It defines a new target hook targetm.remove_extra_call_preserved_regs
that takes a rtx_insn and will remove registers from the register
set passed in if we know that this call preserves those registers.
Aarch64 SIMD functions preserve s
This is a patch 4 to support the Aarch64 SIMD ABI [1] in GCC.
It defines a new target hook targetm.check_part_clobbered that
takes a rtx_insn and checks to see if it is a call to a function
that may clobber partial registers. It returns true by default,
which results in the current behaviour, but
Define the thread-safe pool resource, using a shared_mutex to allow
multiple threads to concurrently allocate from thread-specific pools.
Define new weak symbols for the pthread_rwlock_t functions, to avoid
making libstdc++.so depend on libpthread.so
* config/abi/pre/gnu.ver: Add new sym
> OK for x86 part (that is only PATCH 1/3). It looks that this part can
> go to mainline as an independent patch from other patches in serie.
Thanks.
Note even 2/3 has a small i386 specific part. Would be good if you
could take a look at that part.
-Andi
On Thu, Nov 08, 2018 at 11:57:13PM +1030, Alan Modra wrote:
> On Wed, Nov 07, 2018 at 07:11:28PM -0600, Segher Boessenkool wrote:
> > On Wed, Nov 07, 2018 at 04:08:26PM +1030, Alan Modra wrote:
> > > There is really no need to define a TLSmode mode iterator that is
> > > identical (since !TARGET_64
On Thu, Nov 8, 2018 at 7:03 PM Andi Kleen wrote:
>
> > OK for x86 part (that is only PATCH 1/3). It looks that this part can
> > go to mainline as an independent patch from other patches in serie.
>
> Thanks.
>
> Note even 2/3 has a small i386 specific part. Would be good if you
> could take a loo
On Thu, 8 Nov 2018 at 12:33, Richard Biener wrote:
>
> On Wed, Nov 7, 2018 at 5:22 PM David Malcolm wrote:
> >
> > This patch ports various fprintf calls in the inlining code to using
> > the dump API, using the %C format code for printing cgraph_node *.
> > I focused on the dump messages that se
Hi Mihail
On 08/11/18 10:02, Ramana Radhakrishnan wrote:
> On 07/11/2018 17:49, Mihail Ionescu wrote:
>> Hi All,
>>
>> This is a backport from trunk for GCC 8 and 7.
>>
>> SVN revision: r264595.
>>
>> Regression tested on arm-none-eabi.
>>
>>
>> gcc/ChangeLog
>>
>> 2018-11-02 Mihail Ionescu
>>
On 11/8/18 8:29 AM, Peter Bergner wrote:
> On 11/8/18 5:48 AM, Richard Biener wrote:
>> Esp. adding conflicts in a loop that says "See which defined values die
>> here."
>> is quite fishy.
>
> ..the original loop is dealing with some of the gory details you never read
> about in academic RA paper
This patch corrects a large number of test suite failures. I'm now down to
about 1100 failures out of over 60k total, from at least 4000 before.
Committed.
paul
ChangeLog:
2018-11-08 Paul Koning
* config/pdp11/constraints.md: Add "Z" series constraints for use
wi
On Thu, 2018-11-08 at 19:38 +0100, Christophe Lyon wrote:
[...snip...]
> Hi,
>
> This patch breaks my builds:
> /tmp/9837775_6.tmpdir/aci-gcc-fsf/sources/gcc-
> fsf/gccsrc/gcc/doc//invoke.texi:14118:
> @option expected braces.
> /tmp/9837775_6.tmpdir/aci-gcc-fsf/sources/gcc-
> fsf/gccsrc/gcc/doc/
[PATCH, rs6000] Disable ASLR in sanitizer on powerpc64.
Cherry pick powerpc64 sanitizer fix from upstream llvm.
See https://reviews.llvm.org/rL346030 and
https://reviews.llvm.org/D52900.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu and
powerpc64-unknown-linux-gnu with no regressions.
Hi Jerry!
Hi all,
The attached patch adds code in read_sf_internal to handle early
termination of reads in the presence of comma's. This is to support
legacy codes which are not standard conforming as far as we can tell.
The additions are executed only if -std=legacy is given at compile tim
On 11/8/18 12:12 PM, Bill Seurer wrote:
> [PATCH, rs6000] Disable ASLR in sanitizer on powerpc64.
>
> Cherry pick powerpc64 sanitizer fix from upstream llvm.
>
> See https://reviews.llvm.org/rL346030 and
> https://reviews.llvm.org/D52900.
>
> Bootstrapped and tested on powerpc64le-unknown-linux-
Hi!
I've noticed this test fails intermittently.
The problem is that it wasn't correct, without the in_reduction
clause this patch adds (or e.g. without #pragma omp atomic) there
is a data race, multiple tasks can update concurrently the same variable.
Tested on x86_64-linux, previously it would
On Sun, Oct 7, 2018 at 12:36 AM Thomas Koenig wrote:
> Hi Janne,
>
> > The error handling functions can be called from a signal handler, so they
> > need to be async-signal-safe.
>
> I didn't know that. How can this happen?
>
Hmm, seems I was imagining things, I can't find anything like that in
Hi,
We recently discovered that GCC is getting lucky with register allocation of
some inline assembly code, despite invalid register constraints. In these
two functions, a "wi" constraint (VSX valid for direct moves) was used for a
temporary that, as written, is further constrained to be an FPR.
On Thu, Nov 08, 2018 at 03:44:44PM +, Sam Tebbs wrote:
> Does your patch fix the incorrect generation of "scvtf s1, s1"? I was
> looking at the issue as well and don't want to do any overlapping work.
I don't know. Well, there are no incorrect code issues I know of at all
now; but you mean th
Hi Jakub,
> The OpenMP 5.0 specification, https://www.openmp.org/specifications/ ,
> has been just released a few minutes ago and to celebrate that, I've merged
> gomp-5_0-branch into trunk after bootstrapping/regtesting it on x86_64-linux
> and
> i686-linux.
this patch series broke the Solaris
On 11/8/18 1:27 AM, Martin Liška wrote:
> Hi.
>
> The GetNumberOfCPUs functionality is only used from Scudo allocator:
> https://llvm.org/docs/ScudoHardenedAllocator.html
>
> The hardening allocator is not used from GCC, thus I recommend to remove
> the function.
>
> Ready for trunk?
> Martin
>
On Thu, Nov 08, 2018 at 09:39:12PM +0100, Rainer Orth wrote:
> I guess this is obvious?
>
> Rainer
>
> --
> -
> Rainer Orth, Center for Biotechnology, Bielefeld University
>
>
> 2018-11-08 Rainer Orth
>
>
On Thu, Nov 08, 2018 at 01:43:29PM -0700, Jeff Law wrote:
> On 11/8/18 1:27 AM, Martin Liška wrote:
> > libsanitizer/ChangeLog:
> >
> > 2018-11-08 Martin Liska
> >
> > PR sanitizer/87892
> > * (all files): Revert upstream r318802.
> Is it causing a build failure or somesuch? ie, why s
On 11/8/18 1:48 PM, Jakub Jelinek wrote:
> On Thu, Nov 08, 2018 at 01:43:29PM -0700, Jeff Law wrote:
>> On 11/8/18 1:27 AM, Martin Liška wrote:
>>> libsanitizer/ChangeLog:
>>>
>>> 2018-11-08 Martin Liska
>>>
>>> PR sanitizer/87892
>>> * (all files): Revert upstream r318802.
>> Is it caus
On Thu, 8 Nov 2018 at 20:09, David Malcolm wrote:
>
> On Thu, 2018-11-08 at 19:38 +0100, Christophe Lyon wrote:
> [...snip...]
>
> > Hi,
> >
> > This patch breaks my builds:
> > /tmp/9837775_6.tmpdir/aci-gcc-fsf/sources/gcc-
> > fsf/gccsrc/gcc/doc//invoke.texi:14118:
> > @option expected braces.
>
This is version 2 of the patch to remove power9 fusion. Is it ok to check into
the trunk?
[gcc]
2018-11-08 Michael Meissner
* config/rs6000/constraints.md (wF constraint): Update constraint
documentation for power8 fusion only.
* config/rs6000/predicates.md (p9_fusion
On Thu, 8 Nov 2018, Richard Biener wrote:
The patch is OK.
Thanks,
Richard.
Thanks. Can you please apply it as I don't have any commit rights ?
The patch can be found in
https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01240.html
Here is a valid gcc/ChangeLog correctly formated where I am ref
On 11/08/2018 04:52 AM, Aldy Hernandez wrote:
get/set_range_info() currently returns the extremes of a range. I have
implemented overloaded variants that return a proper range. In the
future we should use actual ranges throughout, and not depend on range
extremes, as depending on this behavior
On 11/8/18 4:00 AM, Alexandre Oliva wrote:
> When in_a resolves to a register set in the prev_clobber insn, we may
> use the SET_SRC for the compare instead. However, when in_b so
> resolves, we proceed to use the reg with its earlier value. When both
> resolve to the same register and prev_clobb
On 10/20/18 4:18 AM, Romain Geissler wrote:
> Hi,
>
> I would like to raise again the question of supporting -fuse-ld=ldd. A
> patch implementing it was already submitted in
> https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01722.html by Davide
> Italiano. This patch still applies correctly to curre
This patch knocks off another old but trivial documentation bug, PR
36572. There are a couple more like this I'm going to squash too.
-Sandra
2018-11-08 Sandra Loosemore
PR other/36572
gcc/
* doc/invoke.texi (Optimize Options): Clarify default behavior
for -fno-sched-interblock and -fn
On 11/7/18 7:17 PM, Peter Bergner wrote:
> On 11/7/18 11:36 AM, Jeff Law wrote:
>> OK with this change.
>
> Before I commit, how about I add the following test cases to test
> both valid and invalid asm constraints? I think I have the reg
> numbers for the other architectures defined correctly.
On 11/8/18 4:07 PM, Jeff Law wrote:
> On 11/7/18 7:17 PM, Peter Bergner wrote:
>> On 11/7/18 11:36 AM, Jeff Law wrote:
>>> OK with this change.
>>
>> Before I commit, how about I add the following test cases to test
>> both valid and invalid asm constraints? I think I have the reg
>> numbers for t
Hi Fredrik,
Thank you for your submission. Your change looks very good to me, except
for a bunch of minor nits in your proposed ChangeLog entry.
> * gcc/config/mips/mips.c (mips_reorg_process_insns)
> (mips_option_override): Default to working around R5900
> errata only i
Hi!
On Thu, Nov 08, 2018 at 02:18:51PM -0600, Bill Schmidt wrote:
> We recently discovered that GCC is getting lucky with register allocation of
> some inline assembly code, despite invalid register constraints. In these
> two functions, a "wi" constraint (VSX valid for direct moves) was used for
On 11/07/2018 02:28 PM, Jeff Law wrote:
On 10/20/18 6:01 PM, Martin Sebor wrote:
The warning only triggers when the bound is less than or equal
to the length of the constant source string (i.e, when strncpy
truncates). So IIUC, your suggestion would defer folding only
such strncpy calls and
On Mon, 5 Nov 2018 at 19:22, Ramana Radhakrishnan
wrote:
>
> On 26/10/2018 06:04, Prathamesh Kulkarni wrote:
> > Hi,
> > This is a rebased version of patch that adds a pattern to neon.md for
> > implementing division with multiplication by reciprocal using
> > vrecpe/vrecps with -funsafe-math-opti
On Tue, 6 Nov 2018 at 16:04, Richard Biener wrote:
>
> On Mon, Nov 5, 2018 at 3:11 PM Prathamesh Kulkarni
> wrote:
> >
> > On Mon, 5 Nov 2018 at 18:14, Richard Biener
> > wrote:
> > >
> > > On Mon, Nov 5, 2018 at 1:11 PM Prathamesh Kulkarni
> > > wrote:
> > > >
> > > > On Mon, 5 Nov 2018 at 15
Hello!
Attached patch fixes PR87928, where we ICE in ix86_compute_frame_layout in
gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
when __attribute__ ((sysv_abi) is used. When the testcase is compiled,
ix86_cfun_abi () returns SYSV_ABI due to function __attribute__
override,
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