On Mon, Oct 23, 2017 at 09:03:33PM +0200, Uros Bizjak wrote:
> >> As for addcarry/subborrow, the problem is that we expect in the pr67317*
> >> tests that combine is able to notice that the CF setter sets CF to
> >> unconditional 0 and matches the pattern. With the patch I wrote
> >> we end up wit
Hi,
This patch enables VBMI2 isaset option. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
common/config/i386/i386-common.c (OPTION_MASK_I
Hi,
This patch enables VPCOMPRESSB[W] instruction. The doc for isaset and
instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config.gcc (avx512vbmi2intrin.h, avx512vbmi2vlintrin):
On Tue, Oct 24, 2017 at 12:02 AM, Damian Rouson
wrote:
>
>
> On October 23, 2017 at 3:54:22 AM, Richard Biener
> (richard.guent...@gmail.com) wrote:
>
> On Sat, Oct 21, 2017 at 2:26 AM, Damian Rouson
> wrote:
>>
>> Hi Richard,
>>
>> Attached is a revised patch that makes the downloading of Fortra
On Mon, Oct 23, 2017 at 4:03 PM, Pedro Alves wrote:
> On 10/23/2017 02:46 PM, Jason Merrill wrote:
>> On Mon, Oct 23, 2017 at 3:33 AM, Jakub Jelinek wrote:
>>> Hi!
>>>
>>> When -gcolumn-info was added back in February, it was too late in the
>>> release cycle to make it the default, but I think n
Hi,
This patch enables VPEXPANDB[W] instruction. The doc for isaset and
instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config/i386/avx512vbmi2intrin.h (_mm512_mask_expand_epi8
On Mon, Oct 23, 2017 at 6:24 PM, Pedro Alves wrote:
> On 10/23/2017 04:50 PM, David Malcolm wrote:
>
>> FWIW, this one isn't from #pragma poison, it's from:
>> #define abort() fancy_abort (__FILE__, __LINE__, __FUNCTION__)
>>
>> (I messed up the --in-reply-to when posting the patch, but Gerald n
OK.
Igor
> -Original Message-
> From: H.J. Lu [mailto:hjl.to...@gmail.com]
> Sent: Tuesday, October 24, 2017 1:01 AM
> To: Tsimbalist, Igor V
> Cc: Uros Bizjak ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] i386: Don't generate ENDBR if function is only called
> directly
>
> On Mon,
On Mon, Oct 23, 2017 at 7:41 PM, Richard Sandiford
wrote:
> This patch changes TYPE_VECTOR_SUBPARTS to a poly_uint64. The value is
> encoded in the 10-bit precision field and was previously always stored
> as a simple log2 value. The challenge was to use this 10 bits to
> encode the number of el
Thanks Jonathan. I tried, and it does not work, I still get the same error:
Making all in include
mkdir -p ./x86_64-apple-darwin17.0.0/bits/stdc++.h.gch
mkdir -p ./x86_64-apple-darwin17.0.0/bits/stdc++.h.gch
/Users/fx/devel/gcc/ibin/./gcc/xgcc -shared-libgcc
-B/Users/fx/devel/gcc/ibin/./gcc -nost
Hi,
This patch enables VPSHLD instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config/i386/avx512vbmi2intrin.h (_mm512_shldi_epi16,
_m
> The patch that adds poly_int has detailed documentation, but the main
> points are:
>
> * there's no total ordering between poly_ints, so the best we can do
> when comparing them is to ask whether two values *might* or *must*
> be related in a particular way. E.g. if mode A has size 2 + 2X
On Tue, Oct 24, 2017 at 8:51 AM, Jakub Jelinek wrote:
> On Mon, Oct 23, 2017 at 09:03:33PM +0200, Uros Bizjak wrote:
>> >> As for addcarry/subborrow, the problem is that we expect in the pr67317*
>> >> tests that combine is able to notice that the CF setter sets CF to
>> >> unconditional 0 and mat
Was Re: PR82575, lto debugobj references __gnu_lto_slim, ld test liblto-17 fails
On Fri, Oct 20, 2017 at 12:00:04AM +1030, Alan Modra wrote:
> PR lto/82575
> * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
> Make discarded non-local symbols weak and hidden.
The
On Tue, Oct 24, 2017 at 10:39 AM, Tsimbalist, Igor V
wrote:
> OK.
+/* { dg-final { scan-assembler-times "endbr32" 2 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "endbr64" 2 { target { ! ia32 } } } } */
I think we can only check for {\mendbr} in the testcases. There are
already pl
Richard Biener writes:
> On Mon, Oct 23, 2017 at 7:41 PM, Richard Sandiford
> wrote:
>> This patch changes TYPE_VECTOR_SUBPARTS to a poly_uint64. The value is
>> encoded in the 10-bit precision field and was previously always stored
>> as a simple log2 value. The challenge was to use this 10 bi
On 23/10/17 17:36, Dominik Inführ wrote:
> I’ve added your suggestions. I would also like to propose to change the type
> attribute from neon_stp to store_8 and store_16, this seems to be more in
> line with respect to other patterns.
>
> Thanks,
> Dominik
>
> ChangeLog:
> 2017-10-23 Dominik I
On Tue, 24 Oct 2017, Alan Modra wrote:
> Was Re: PR82575, lto debugobj references __gnu_lto_slim, ld test liblto-17
> fails
> On Fri, Oct 20, 2017 at 12:00:04AM +1030, Alan Modra wrote:
> > PR lto/82575
> > * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
> > Make di
Hi!
Poeple from NVidia reported privately unexpected amount of host2dev
transfers for #pragma omp target*.
The code even had comments like:
/* FIXME: Perhaps add some smarts, like if copying
several adjacent fields from host to target, use some
Eric Botcazou writes:
>> The patch that adds poly_int has detailed documentation, but the main
>> points are:
>>
>> * there's no total ordering between poly_ints, so the best we can do
>> when comparing them is to ask whether two values *might* or *must*
>> be related in a particular way. E.
On Tue, Oct 24, 2017 at 11:40 AM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Mon, Oct 23, 2017 at 7:41 PM, Richard Sandiford
>> wrote:
>>> This patch changes TYPE_VECTOR_SUBPARTS to a poly_uint64. The value is
>>> encoded in the 10-bit precision field and was previously always stor
Hi,
This patch enables VPSHRD instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config/i386/avx512vbmi2intrin.h (_mm512_shrdi_epi16,
_m
Attached the patch
> -Original Message-
> From: Koval, Julia
> Sent: Tuesday, October 24, 2017 12:01 PM
> To: GCC Patches
> Cc: Kirill Yukhin
> Subject: [PATCH][i386,AVX] Enable VBMI2 support [5/7]
>
> Hi,
> This patch enables VPSHRD instruction. The doc for isaset and instruction:
> ht
Hi,
This patch enables VPSHRDV instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config/i386/avx512vbmi2intrin.h (_mm512_shrdv_epi16,
_
Hi,
This patch enables VPSHRDV instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config/i386/avx512vbmi2intrin.h (_mm512_shldv_epi16,
_
On 20 Oct 08:20, Shalnov, Sergey wrote:
> I can't propose general solution since TARGET_PREFER256 is AVX512 specific.
> Sorry for misunderstanding.
Okay than. I've checked in your patch into main trunk, thanks!
--
K
> Sergey
>
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [m
Hi,
This patch enables VNNI isaset option. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_
> Yeah. E.g. for ==, the two options would be:
>
> a) must_eq (a, b) -> a == b
>must_ne (a, b) -> a != b
>
>which has the weird property that (a == b) != (!(a != b))
>
> b) must_eq (a, b) -> a == b
>may_ne (a, b)-> a != b
>
>which has the weird property that a can be
On 10/23/2017 06:14 PM, Martin Sebor wrote:
...
> It seems to me that before exposing a new mechanism to control
> the exec charset it would be prudent to a) plug at least the
> biggest holes to make the feature more reliable (in my mind,
> that's at least -Wformat), and b) make sure the pragma int
Hi,
This patch enables VPDPBUSD instruction, also it contains builtins and md
patterns for other VNNI instructions. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Th
> 2017-10-13 Prathamesh Kulkarni
>
> * cgraph.h (set_malloc_flag): Declare.
> * cgraph.c (set_malloc_flag_1): New function.
> (set_malloc_flag): Likewise.
> * ipa-fnsummary.h (ipa_call_summary): Add new field is_return_callee.
> * ipa-fnsummary.c (ipa_call_summary:
Hi,
This patch enables VPDPBUSDS instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
* config/i386/avx512vnniintrin.h (_mm512_dpbu
Hi!
I'd like to ping two patches:
http://gcc.gnu.org/ml/gcc-patches/2017-10/msg00206.html
PR target/82370 - improve V?TImode shifts
H.J., can you please respond whether the
(set_attr "atom_unit" "sishuf")
attribute just on {,v}psrldq and not on {,v}pslldq
was intentional (and if so, why
On Tue, Oct 24, 2017 at 2:33 AM, Uros Bizjak wrote:
> On Tue, Oct 24, 2017 at 10:39 AM, Tsimbalist, Igor V
> wrote:
>> OK.
>
> +/* { dg-final { scan-assembler-times "endbr32" 2 { target ia32 } } } */
> +/* { dg-final { scan-assembler-times "endbr64" 2 { target { ! ia32 } } } } */
>
> I think we c
Hi,
This patch enables VPDPWSSD instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
* config/i386/avx512vnniintrin.h (_mm512_dpwss
Bootstrap GCC with Intel CET by configuring GCC with
--with-build-config="bootstrap-cet bootstrap-debug"
Tested on Linux/i686 and Linux/x86-64.
OK for trunk?
H.J.
---
config/
* bootstrap-cet.mk: New file.
gcc/
* doc/install.texi: Document bootstrap-cet.
---
config/bootstrap-
Richard Biener writes:
> On Tue, Oct 24, 2017 at 11:40 AM, Richard Sandiford
> wrote:
>> Richard Biener writes:
>>> On Mon, Oct 23, 2017 at 7:41 PM, Richard Sandiford
>>> wrote:
This patch changes TYPE_VECTOR_SUBPARTS to a poly_uint64. The value is
encoded in the 10-bit precision fie
Hi,
This patch enables VPDPWSSDS instruction. The doc for isaset and instruction:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
* config/i386/avx512vnniintrin.h (_mm512_dpws
Eric Botcazou writes:
>> Yeah. E.g. for ==, the two options would be:
>>
>> a) must_eq (a, b) -> a == b
>>must_ne (a, b) -> a != b
>>
>>which has the weird property that (a == b) != (!(a != b))
>>
>> b) must_eq (a, b) -> a == b
>>may_ne (a, b)-> a != b
>>
>>which has
On Tue, Oct 24, 2017 at 1:18 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Tue, Oct 24, 2017 at 11:40 AM, Richard Sandiford
>> wrote:
>>> Richard Biener writes:
On Mon, Oct 23, 2017 at 7:41 PM, Richard Sandiford
wrote:
> This patch changes TYPE_VECTOR_SUBPARTS to a
C++17 says these operators should be noexcept (and Clang-Tidy can't
figure out they don't throw otherwise). LFTS doesn't have these
literals, but we'd be able to make them noexcept anyway, just because
we like to do that.
PR libstdc++/82685
* include/experimental/string_view (oper
On Tue, Oct 24, 2017 at 1:23 PM, Richard Sandiford
wrote:
> Eric Botcazou writes:
>>> Yeah. E.g. for ==, the two options would be:
>>>
>>> a) must_eq (a, b) -> a == b
>>>must_ne (a, b) -> a != b
>>>
>>>which has the weird property that (a == b) != (!(a != b))
>>>
>>> b) must_eq (a, b
On 10/19/2017 04:22 PM, Richard Sandiford wrote:
Richard Sandiford writes:
Aldy Hernandez writes:
On Tue, Oct 17, 2017 at 6:05 PM, Richard Sandiford
wrote:
Andrew MacLeod writes:
On 10/17/2017 08:18 AM, Richard Sandiford wrote:
Aldy Hernandez writes:
Hi folks!
Calling print_hex() on a
PLT should be avoided with shadow stack in 32-bit mode if more than 2
parameters are passed in registers since only 2 parameters can be passed
in registers for external function calls via PLT with shadow stack
enabled.
OK for trunk if there is no regressions?
H.J.
---
gcc/
PR target/8178
On Tue, Oct 24, 2017 at 1:14 PM, H.J. Lu wrote:
> Bootstrap GCC with Intel CET by configuring GCC with
>
> --with-build-config="bootstrap-cet bootstrap-debug"
>
> Tested on Linux/i686 and Linux/x86-64.
>
> OK for trunk?
Ok. Do you have a simulator that understands CET yet?
Richard.
> H.J.
> --
On Fri, Oct 20, 2017 at 12:33 PM, Kirill Yukhin wrote:
> Hello Jakub, Uroš, Jakub
> On 04 Oct 21:35, Jakub Jelinek wrote:
>> Hi!
>>
>> The following patch tweaks the TImode vector shifts similarly
>> to the earlier vector shift patch, so that for shifts by immediate
>> we can accept a memory input
On Tue, Oct 24, 2017 at 5:42 AM, Richard Biener
wrote:
> On Tue, Oct 24, 2017 at 1:14 PM, H.J. Lu wrote:
>> Bootstrap GCC with Intel CET by configuring GCC with
>>
>> --with-build-config="bootstrap-cet bootstrap-debug"
>>
>> Tested on Linux/i686 and Linux/x86-64.
>>
>> OK for trunk?
>
> Ok. Do y
Richard Biener writes:
> On Tue, Oct 24, 2017 at 1:23 PM, Richard Sandiford
> wrote:
>> Eric Botcazou writes:
Yeah. E.g. for ==, the two options would be:
a) must_eq (a, b) -> a == b
must_ne (a, b) -> a != b
which has the weird property that (a == b) != (
On Tue, Oct 24, 2017 at 2:48 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Tue, Oct 24, 2017 at 1:23 PM, Richard Sandiford
>> wrote:
>>> Eric Botcazou writes:
> Yeah. E.g. for ==, the two options would be:
>
> a) must_eq (a, b) -> a == b
>must_ne (a, b) ->
This applies 'noexcept' more liberally in our std::basic_string_view,
anywhere that can't actually throw (even if it has a narrow contract).
I've also refactored some members to remove complex conditional
expressions, because they're not needed with C++14 constexpr, we can
just write the code as
The long double compat symbols are producing warnings, this
suppressess them.
* config/locale/gnu/c_locale.cc [_GLIBCXX_LONG_DOUBLE_COMPAT]: Ignore
-Wattribute-alias warnings.
* src/c++11/istream-inst.cc: Likewise.
* src/c++11/locale-inst.cc: Likewise.
* sr
Richard Biener writes:
> On Tue, Oct 24, 2017 at 2:48 PM, Richard Sandiford
> wrote:
>> Richard Biener writes:
>>> On Tue, Oct 24, 2017 at 1:23 PM, Richard Sandiford
>>> wrote:
Eric Botcazou writes:
>> Yeah. E.g. for ==, the two options would be:
>>
>> a) must_eq (a, b) ->
On 24/10/17 11:06 +0200, FX wrote:
Thanks Jonathan. I tried, and it does not work, I still get the same error:
Making all in include
mkdir -p ./x86_64-apple-darwin17.0.0/bits/stdc++.h.gch
mkdir -p ./x86_64-apple-darwin17.0.0/bits/stdc++.h.gch
/Users/fx/devel/gcc/ibin/./gcc/xgcc -shared-libgcc
-
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied.
Richard.
2017-10-24 Richard Biener
PR tree-optimization/82697
* tree-ssa-phiopt.c (cond_store_replacement): Use alias-set
zero for conditional load and unconditional store.
* gcc.dg/torture/pr82697
On Fri, Oct 20, 2017 at 5:53 PM, David Malcolm wrote:
> Design questions:
>
> * The patch introduces a new kind of tree node, currently called
> DECL_WRAPPER_EXPR (although it's used for wrapping constants as well
> as decls). Should wrappers be a new kind of tree node, or should they
> reu
On Fri, Oct 20, 2017 at 3:52 PM, Mukesh Kapoor wrote:
> On 10/20/2017 11:00 AM, Mukesh Kapoor wrote:
>> On 10/20/2017 10:45 AM, Nathan Sidwell wrote:
>>> On 10/20/2017 12:37 PM, Mukesh Kapoor wrote:
This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80955.
Handle user-def
The output of “make -j4” in a build at stage1, where I have just run "rm -rf
x86_64-apple-darwin17.0.0/**/libstdc++-v3”, with the patch applied:
https://gist.github.com/fxcoudert/46f0026c44eb3db2937ac0e92a477338
FX
On 10/18/2017 09:07 AM, Martin Liška wrote:
@@ -1182,7 +1182,13 @@ cxx_eval_builtin_function_call (const constexpr_ctx
*ctx, tree t, tree fun,
{
new_call = build_call_array_loc (EXPR_LOCATION (t), TREE_TYPE (t),
CALL_EXPR_FN (t), nargs
Hello,
On Fri, 22 Sep 2017, Bin.Cheng wrote:
> This is updated patch for loop interchange with review suggestions
> resolved. Changes are:
> 1) It does more light weight checks like rectangle loop nest check
> earlier than before.
> 2) It checks profitability of interchange before data depen
On 10/18/2017 08:47 AM, Martin Liška wrote:
This is first patch that addresses test-suite fallout. All these tests fail in
runtime.
+++ b/gcc/testsuite/g++.dg/missing-return.C
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-Wreturn-type -fdump-tree-optimized" } */
+
+int foo(int a
On 10/18/2017 08:48 AM, Martin Liška wrote:
This is second patch that addresses test-suite fallout. All these tests fail
because -Wreturn-type is
now on by default.
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-diag3.C
-constexpr T g(T t) { return f(t); } // { dg-error "f.int" }
+constexpr T g(T
OK.
On Wed, Oct 18, 2017 at 7:07 AM, Paolo Carlini wrote:
> Hi,
>
> a rather straightforward issue that we didn't notice so far only because in
> all our uses of __is_trivially_constructible either neither type is
> dependent or both are (eg, in library uses). The below handles in the
> obvious w
On Tue, Oct 24, 2017 at 05:44:44AM -0700, H.J. Lu wrote:
> > What I can see from config/atom.md:
> > ;; if palignr or psrldq
> > (define_insn_reservation "atom_sseishft_2" 1
> > (and (eq_attr "cpu" "atom")
> >(and (eq_attr "type" "sseishft")
> > (and (eq_attr "atom_unit" "sis
> On 24 Oct 2017, at 11:40, Richard Earnshaw (lists)
> wrote:
>
> On 23/10/17 17:36, Dominik Inführ wrote:
>> I’ve added your suggestions. I would also like to propose to change the type
>> attribute from neon_stp to store_8 and store_16, this seems to be more in
>> line with respect to other
On 24/10/17 15:54, Dominik Inführ wrote:
>
>> On 24 Oct 2017, at 11:40, Richard Earnshaw (lists)
>> wrote:
>>
>> On 23/10/17 17:36, Dominik Inführ wrote:
>>> I’ve added your suggestions. I would also like to propose to change the
>>> type attribute from neon_stp to store_8 and store_16, this se
On 24/10/17 16:03 +0200, FX wrote:
OK, could you try this, and share the full output?
Attached is the output of “make -j4” in a build at stage1, where I have just run
"rm -rf x86_64-apple-darwin17.0.0/**/libstdc++-v3”, with the patch applied.
FX
There are two commands that create the includ
On 09/29/2017 08:32 AM, Jakub Jelinek wrote:
+ tree b = builtin_decl_explicit (DECL_FUNCTION_CODE (newdecl));
+ if (b)
+ duplicate_one_attribute (&DECL_ATTRIBUTES (b),
+DECL_ATTRIBUTES (newdecl),
+"o
On Fri, Oct 06, 2017 at 01:45:15PM +0100, Tamar Christina wrote:
> Hi All,
>
> this is a respin with the changes suggested. Note that this patch is no 8/8
> in the series.
>
> Regtested on arm-none-eabi, armeb-none-eabi,
> aarch64-none-elf and aarch64_be-none-elf with no issues found.
>
> Ok fo
> Presumably for the i386 and x86_64 multilibs (does it make any
> difference if you do --disable-multlib? It would be easier to debug the
> output if each command was only done once).
Same problem without multilib.
> I can't really do much more by email, somebody with access to one of
> these fa
On Fri, Oct 06, 2017 at 01:45:18PM +0100, Tamar Christina wrote:
> Hi All,
>
> this is a minor respin of the patch with the comments addressed. Note this
> patch is now 7/8 in the series.
>
>
> Regtested on arm-none-eabi, armeb-none-eabi,
> aarch64-none-elf and aarch64_be-none-elf with no issue
On Wed, Sep 13, 2017 at 04:00:24PM +0100, Tamar Christina wrote:
> Hi All,
>
> The inlining of lrint isn't valid in all cases on ILP32 when
> -fno-math-errno is used because an inexact exception is raised in
> certain circumstances.
>
> Instead the restriction is placed such that the integer mode
On Tue, Oct 24, 2017 at 11:06:51AM -0400, Jason Merrill wrote:
> On 09/29/2017 08:32 AM, Jakub Jelinek wrote:
> > + tree b = builtin_decl_explicit (DECL_FUNCTION_CODE (newdecl));
> > + if (b)
> > + duplicate_one_attribute (&DECL_ATTRIBUTES (b),
> > +DEC
My concern with this pragma/attribute and inlining has to do with
strings in one exec charset being propagated into functions that
operate on strings in another charset. E.g., like in the test
case below that's "miscompiled" with your patch -- the first test
for n == 7 is eliminated and the buffe
Uros Bizjak writes:
> On Fri, Oct 13, 2017 at 12:56 PM, Tsimbalist, Igor V
> wrote:
>>> -Original Message-
>>> From: Uros Bizjak [mailto:ubiz...@gmail.com]
>>> Sent: Friday, October 13, 2017 10:02 AM
>>> To: Tsimbalist, Igor V
>>> Cc: gcc-patches@gcc.gnu.org
>>> Subject: Re: 0006-Part-6
OK.
On Fri, Sep 29, 2017 at 4:57 PM, Jakub Jelinek wrote:
> Hi!
>
> The casts added for the C++17 direct enum initialization IMNSHO shouldn't
> trigger -Wuseless-cast warnings.
>
> Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
> trunk?
>
> 2017-09-29 Jakub Jelinek
OK.
On Mon, Oct 9, 2017 at 6:37 AM, Paolo Carlini wrote:
> Hi,
>
> this issue filed by Bernd is sort-of a small follow-up to his c++/71973: the
> C front-end already warns for things like:
>
> int printf;
>
> where we are declaring in the global namespace a built-in. Beyond copying
> over to
Hi Uros,
> Remove dead code, obsoleted by cbranch rewrite years ago.
>
> 2017-10-11 Uros Bizjak
>
> * config/i386/i386.md (*cmp__i387):
> Do not use float_operator operator predicate.
> (*cmp__cc_i387): Ditto.
> * config/i386/predicates.md (float_operator): Remove predicate.
>
>
On 24/10/17 17:14 +0200, FX wrote:
Presumably for the i386 and x86_64 multilibs (does it make any
difference if you do --disable-multlib? It would be easier to debug the
output if each command was only done once).
Same problem without multilib.
OK good, so then test without multilib, because
On 10/24/2017 02:55 AM, Jakub Jelinek wrote:
> Poeple from NVidia reported privately unexpected amount of host2dev
> transfers for #pragma omp target*.
Did they mention which program they were testing?
> The code even had comments like:
>/* FIXME: Perhaps add some smarts, lik
On Tue, Oct 24, 2017 at 08:47:39AM -0700, Cesar Philippidis wrote:
> On 10/24/2017 02:55 AM, Jakub Jelinek wrote:
>
> > Poeple from NVidia reported privately unexpected amount of host2dev
> > transfers for #pragma omp target*.
>
> Did they mention which program they were testing?
No. Just the n
On Tue, Oct 24, 2017 at 5:35 PM, Rainer Orth
wrote:
> Uros Bizjak writes:
>
>> On Fri, Oct 13, 2017 at 12:56 PM, Tsimbalist, Igor V
>> wrote:
-Original Message-
From: Uros Bizjak [mailto:ubiz...@gmail.com]
Sent: Friday, October 13, 2017 10:02 AM
To: Tsimbalist, Igor V
ENDBR must be the first instruction of a function. This patch queues
ENDBR if we need to put the profiling counter call before the prologue
and generate ENDBR before the profiling counter call.
OK for trunk if there is no regressions?
H.J.
---
gcc/
PR target/82699
* config/i386/
On Tue, Oct 24, 2017 at 5:39 PM, Rainer Orth
wrote:
> Hi Uros,
>
>> Remove dead code, obsoleted by cbranch rewrite years ago.
>>
>> 2017-10-11 Uros Bizjak
>>
>> * config/i386/i386.md (*cmp__i387):
>> Do not use float_operator operator predicate.
>> (*cmp__cc_i387): Ditto.
>> * c
On Fri, Aug 04, 2017 at 04:46:09PM +0100, Wilco Dijkstra wrote:
> To fix PR60580 simplify the logic in aarch64_override_options_after_change_1
> ().
> If the frame pointer is enabled, set it to a special value that behaves
> similar
> to frame pointer omission. If we don't do this all leaf func
Richard Biener writes:
> On Tue, Oct 24, 2017 at 1:18 PM, Richard Sandiford
> wrote:
>> Richard Biener writes:
>>> Do you have any numbers on the effect of poly-int on compile-times?
>>> Esp. for example on stage2 build times when stage1 is -O0 -g "optimized"?
>>
>> I've just tried that for an x
Andrew MacLeod writes:
> On 10/19/2017 04:22 PM, Richard Sandiford wrote:
>> Richard Sandiford writes:
>>> Aldy Hernandez writes:
On Tue, Oct 17, 2017 at 6:05 PM, Richard Sandiford
wrote:
> Andrew MacLeod writes:
>> On 10/17/2017 08:18 AM, Richard Sandiford wrote:
>>> Ald
On 10/24/2017 05:33 PM, Martin Sebor wrote:
>>> My concern with this pragma/attribute and inlining has to do with
>>> strings in one exec charset being propagated into functions that
>>> operate on strings in another charset. E.g., like in the test
>>> case below that's "miscompiled" with your pat
James Greenhalgh wrote:
>
> This code is a mess, would macroing your magic number 2 help at all? All the
> double negatives give me a massive headache!
Well we really need to rename flag_omit_frame_pointer to flag_use_frame_pointer
or similar (omit and emit are too similar!). That removes most dou
On Tue, Oct 24, 2017 at 09:04:05AM -0700, H.J. Lu wrote:
> ENDBR must be the first instruction of a function. This patch queues
> ENDBR if we need to put the profiling counter call before the prologue
> and generate ENDBR before the profiling counter call.
>
> OK for trunk if there is no regressi
On Tue, Oct 24, 2017 at 4:46 PM, Jakub Jelinek wrote:
> On Tue, Oct 24, 2017 at 05:44:44AM -0700, H.J. Lu wrote:
>> > What I can see from config/atom.md:
>> > ;; if palignr or psrldq
>> > (define_insn_reservation "atom_sseishft_2" 1
>> > (and (eq_attr "cpu" "atom")
>> >(and (eq_attr "ty
On 10/23/2017 05:14 PM, Jeff Law wrote:
Martin,
I'd like your thoughts on this patch.
One of the things I'm working on is changes that would allow passes that
use dominator walks to trivially perform context sensitive range
analysis as a part of their dominator walk.
As I outlined earlier thi
On Tue, 24 Oct 2017, Jakub Jelinek wrote:
> loop transfering the addresses or firstprivate_int values to the device
> - where we issued mapnum host2dev transfers each just pointer-sized
> when we could have just prepared all the pointers in an array and host2dev
> copy them all together.
Can you p
"H.J. Lu" writes:
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr82699-4.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
> +/* { dg-options "-O2 -fpic -fcf-protection -mcet -pg -mfentry
> -fasynchronous-unwind-tables" } */
> +/* { dg-final { scan-a
tree-ssa-propagate.c provides a fairly generic engine to propagate
values through a lattice while in SSA form. The engine uses two
callbacks to allow passes to provide pass specific handling of
statements and phi nodes.
The callback mechanism served us well in a C world. It is however
somewhat
On Tue, 24 Oct 2017, Jakub Jelinek wrote:
> > Why did you chose the 32KB and 4KB limits? I wonder if that would have
> > any impact on firstprivate_int values. If this proves to be effective,
> > it seems like we should be able to eliminate GOMP_MAP_FIRSTPRIVATE_INT
> > altogether.
>
> The thing i
On Tue, Oct 24, 2017 at 11:33 AM, Jakub Jelinek wrote:
> On Tue, Oct 24, 2017 at 11:06:51AM -0400, Jason Merrill wrote:
>> On 09/29/2017 08:32 AM, Jakub Jelinek wrote:
>> > + tree b = builtin_decl_explicit (DECL_FUNCTION_CODE (newdecl));
>> > + if (b)
>> > + duplicate_one_attribute (
Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns. This corrects the problem, and adds
a zero-extending pattern as well.
gcc/ChangeLog
2017-10-24 Palmer Dabbelt
* config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
* config/ri
On Tue, Oct 24, 2017 at 10:40 AM, Andi Kleen wrote:
> "H.J. Lu" writes:
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/i386/pr82699-4.c
>> @@ -0,0 +1,11 @@
>> +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
>> +/* { dg-options "-O2 -fpic -fcf-protection -mcet -pg -mfentry
>>
Thanks for looking at this Frederic, I don't see your name in the
MAINTAINERS list so I assume I still need approval from one of the
diagnostic message maintainers (Dodji or David) or maybe an Aarch64
maintainer or a global maintainer.
Ping?
Steve Ellcey
sell...@cavium.com
On Sun, 2017-10-08 at
Ping.
Steve Ellcey
On Fri, 2017-10-06 at 14:01 -0700, Steve Ellcey wrote:
> This patch is a follow up to a discussion at:
>
> https://gcc.gnu.org/ml/gcc/2017-06/msg00126.html
>
> For some reason the simd version of fnma in aarch64-simd.md
> is not in the canonical form of having the neg operato
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