Re: [PATCH 2/3] function: Factor out make_*logue_seq

On Wed, May 18, 2016 at 05:13:25PM -0500, Segher Boessenkool wrote: > On Wed, May 18, 2016 at 01:35:16PM -0500, Segher Boessenkool wrote: > > On Wed, May 18, 2016 at 11:20:29AM -0700, H.J. Lu wrote: > > > >> > * function.c (make_split_prologue_seq, make_prologue_seq, > > > >> > make

Backport PR 69400: Invalid 128-bit modulus result

There doesn't seem to have been any fallout from the fix for PR69400 and it applies cleanly to gcc-5-branch. Bootstrapped & regression-tested on x86_64-linux-ngu. OK for gcc 5? Thanks, Richard Backport from mainline: gcc/ 2016-01-26 Richard Sandiford PR tree-optimization/69400

Re: [PATCH 2/3] function: Factor out make_*logue_seq

On Thu, May 19, 2016 at 09:16:26AM +0200, Jakub Jelinek wrote: > On Wed, May 18, 2016 at 05:13:25PM -0500, Segher Boessenkool wrote: > > On Wed, May 18, 2016 at 01:35:16PM -0500, Segher Boessenkool wrote: > > > On Wed, May 18, 2016 at 11:20:29AM -0700, H.J. Lu wrote: > > > > >> > * function

Re: [PATCH 2/3] function: Factor out make_*logue_seq

On Thu, May 19, 2016 at 02:28:15AM -0500, Segher Boessenkool wrote: > The following fixes it, tested on x86_64-linux. Is it okay for trunk? > > (It only happens for targets that have a splitter gated by epilogue_done > for their eh_return pattern). > > > Segher > > > 2016-05-19 Segher Boesse

Re: [PATCH PR69848/partial]Propagate comparison into VEC_COND_EXPR if target supports

On Wed, May 18, 2016 at 5:06 PM, Bin.Cheng wrote: > On Tue, May 17, 2016 at 12:08 PM, Richard Biener > wrote: >> On Mon, May 16, 2016 at 10:09 AM, Bin.Cheng wrote: >>> On Fri, May 13, 2016 at 5:53 PM, Richard Biener >>> wrote: On May 13, 2016 6:02:27 PM GMT+02:00, Bin Cheng wrote: >Hi

Re: [PATCH, PR rtl-optimization/71148] Avoid cleanup_cfg called with invalidated dominance info

On Wed, May 18, 2016 at 6:17 PM, Ilya Enkovich wrote: > Hi, > > This patch resolves PR71148 by releasing dominance info before > cleanup_cfg calls to avoid attempts to fixup invalid dominance > info. > > Dominance info handling in cleanup_cfg looks weird though. It > tries to fix it but can inval

Re: [PATCH 3/3] function: Restructure *logue insertion

On Tue, May 17, 2016 at 01:09:11AM +, Segher Boessenkool wrote: > This patch restructures how the prologues/epilogues are inserted. Sibcalls > that run without prologue are now handled in shrink-wrap.c; it communicates > what is already handled by setting the EDGE_IGNORE flag. The > try_shrin

[PATCH] Fix PR tree-optimization/71170

Hello. Following patch fixes the ICE as it defensively finds the right place where a new STMT should be inserted. Patch bootstraps on x86_64-linux-gnu and no new regression is introduced. Ready for trunk? Thanks, Martin >From de9f966a20cf08721dc8bdb83144b07f72e6cc59 Mon Sep 17 00:00:00 2001 From

Re: Backport PR 69400: Invalid 128-bit modulus result

On Thu, May 19, 2016 at 9:27 AM, Richard Sandiford wrote: > There doesn't seem to have been any fallout from the fix for PR69400 > and it applies cleanly to gcc-5-branch. > > Bootstrapped & regression-tested on x86_64-linux-ngu. OK for gcc 5? Ok. Thanks, Richard. > Thanks, > Richard > > > Back

Re: [PATCH] Fix PR tree-optimization/71170

On Thu, May 19, 2016 at 10:04 AM, Martin Liška wrote: > Hello. > > Following patch fixes the ICE as it defensively finds the right > place where a new STMT should be inserted. > > Patch bootstraps on x86_64-linux-gnu and no new regression is introduced. > > Ready for trunk? @@ -3813,7 +3813,8 @@

Re: [PATCH] Fix PR tree-optimization/71170

Hi Martin, Thanks for the fix. Just to elaborate (as mentioned in PR) At tree-ssa-reassoc.c:3897, we have: stmt: _15 = _4 + c_7(D); oe->op def_stmt: _17 = c_7(D) * 3; : a1_6 = s_5(D) * 2; _1 = (long int) a1_6; x1_8 = _1 + c_7(D); a2_9 = s_5(D) * 4; _2 = (long int) a2_9; a3_11 = s_5(D) * 6; _3

Re: [Patch, ARM] PR71061, length pop* pattern in epilogue correctly

On 13/05/16 14:54, Jiong Wang wrote: For thumb mode, this is causing wrong size calculation and may affect some rtl pass, for example bb-order where copy_bb_p needs accurate insn length info. This have eventually part of the reason for https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00639.html

Re: [PATCH] Fix PR tree-optimization/71170

On Thu, May 19, 2016 at 10:12 AM, Kugan Vivekanandarajah wrote: > Hi Martin, > > Thanks for the fix. Just to elaborate (as mentioned in PR) > > At tree-ssa-reassoc.c:3897, we have: > > stmt: > _15 = _4 + c_7(D); > > oe->op def_stmt: > _17 = c_7(D) * 3; > > > : > a1_6 = s_5(D) * 2; > _1 = (long int

Re: [PATCH] Fix PR tree-optimization/71170

Hi, On 19/05/16 18:21, Richard Biener wrote: > On Thu, May 19, 2016 at 10:12 AM, Kugan Vivekanandarajah > wrote: >> Hi Martin, >> >> Thanks for the fix. Just to elaborate (as mentioned in PR) >> >> At tree-ssa-reassoc.c:3897, we have: >> >> stmt: >> _15 = _4 + c_7(D); >> >> oe->op def_stmt: >> _

Re: [PATCH 2/4] BRIG (HSAIL) frontend: The FE itself.

On Wed, May 18, 2016 at 9:36 PM, David Malcolm wrote: > On Wed, 2016-05-18 at 19:59 +0300, Pekka Jääskeläinen wrote: >> Hi Joseph, >> >> Thanks for the comments. Updated&rebased patch attached. Hopefully I >> didn't miss any diags. > > It looks like the attachment doesn't contain the patch; on un

Re: [PATCH 1/4] BRIG (HSAIL) frontend: configuration file changes and misc

On Wed, May 18, 2016 at 7:58 PM, Pekka Jääskeläinen wrote: > Attached an updated patch (rebased + added .texi docs). Trying again. The file got somehow corrupted in the process. Sorry, Pekka The configuration file changes, documentation updates and other updates. Also, added include/hsa-interfa

[PATCH] Formatting fix for recent libiberty change

Hi! While backporting the recent demangler fix, I've noticed a formatting glitch, which I've committed as obvious. 2016-05-19 Jakub Jelinek PR c++/70498 * cp-demangle.c (d_expression_1): Formatting fix. --- cp-demangle.c (revision 236439) +++ cp-demangle.c (workin

Re: [PATCH] Fix PR tree-optimization/71170

On Thu, May 19, 2016 at 10:26 AM, Kugan wrote: > Hi, > > > On 19/05/16 18:21, Richard Biener wrote: >> On Thu, May 19, 2016 at 10:12 AM, Kugan Vivekanandarajah >> wrote: >>> Hi Martin, >>> >>> Thanks for the fix. Just to elaborate (as mentioned in PR) >>> >>> At tree-ssa-reassoc.c:3897, we have:

Re: [PATCH] Add port for Phoenix-RTOS on ARM platform.

Hi Jakub, For future reference, as per https://gcc.gnu.org/contribute.html the usual practice is to wait for a week or two before pinging a patch... On 17/05/16 09:42, Kuba Sejdak wrote: --- ChangeLog| 6 ++ MAINTAINERS | 1 + configure|

[PING^3][PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

Ping for GCC-7, patch applies cleanly, passed make check for cortex-m0. Might be worth mentioning that this patch has been used in three releases of the GNU ARM embedded toolchain, using GCC versions 4.9 and 5, and no issues have been reported so far. On 25/01/16 17:15, Andre Vieira (lists) wrote

Re: [PATCH 1/3] Encapsulate comp_cost within a class with methods.

On 05/16/2016 03:55 PM, Martin Liška wrote: > On 05/16/2016 12:13 PM, Bin.Cheng wrote: >> Hi Martin, >> Could you please rebase this patch and the profiling one against >> latest trunk? The third patch was applied before these two now. >> >> Thanks, >> bin > > Hello. > > Sending the rebased vers

Re: [PATCH 2/3] Add profiling support for IVOPTS

On 05/17/2016 12:27 AM, Bin.Cheng wrote: >> As profile-guided optimization can provide very useful information >> about basic block frequencies within a loop, following patch set leverages >> that information. It speeds up a single benchmark from upcoming SPECv6 >> suite by 20% (-O2 -profile-genera

Re: [PATCH, PR rtl-optimization/71148] Avoid cleanup_cfg called with invalidated dominance info

On 19 May 09:57, Richard Biener wrote: > On Wed, May 18, 2016 at 6:17 PM, Ilya Enkovich wrote: > > Hi, > > > > This patch resolves PR71148 by releasing dominance info before > > cleanup_cfg calls to avoid attempts to fixup invalid dominance > > info. > > > > Dominance info handling in cleanup_cfg

Re: [Patch V2] Fix SLP PR58135.

On Wed, May 18, 2016 at 5:29 PM, Kumar, Venkataramanan wrote: > Hi Richard, > >> -Original Message- >> From: Richard Biener [mailto:richard.guent...@gmail.com] >> Sent: Tuesday, May 17, 2016 5:40 PM >> To: Kumar, Venkataramanan >> Cc: gcc-patches@gcc.gnu.org >> Subject: Re: [Patch V2] Fix

Re: [PATCH, PR rtl-optimization/71148] Avoid cleanup_cfg called with invalidated dominance info

On Thu, May 19, 2016 at 12:34 PM, Ilya Enkovich wrote: > On 19 May 09:57, Richard Biener wrote: >> On Wed, May 18, 2016 at 6:17 PM, Ilya Enkovich >> wrote: >> > Hi, >> > >> > This patch resolves PR71148 by releasing dominance info before >> > cleanup_cfg calls to avoid attempts to fixup invalid

[PATCH 2/9] Fix leak in tree-ssa-loop-prefetch.c

This fixes memory leak which can be e.g. for 20020122-2.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O2 -fprefetch-loop-arrays. gcc/ChangeLog: 2016-05-18 Martin Liska * tree-ssa-loop-prefetch.c (determine_loop_nest_reuse): Use auto_vec instead of vec. --- gcc/tre

[PATCH 0/9] Remove various memory leaks

Hello. Following patchset removes bunch of memory leaks that are connect to middle-end of the compiler. Each patch contains corresponding ChangeLog entry and link to a source file in our test-suite which suffers from a memory leak. The patchset has been tested in whole on x86_64-linux-gnu and do

[PATCH 3/9] Fix leak in gcc/tree-ssa-reassoc.c.

Leak can be seen e.g. here: gcc reassoc-11.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O2 -fdump-tree-reassoc1 gcc/ChangeLog: 2016-05-18 Martin Liska * tree-ssa-reassoc.c (eliminate_duplicate_pair): Truncate an auto_vec instead of re-creating it. --- gcc/tree-ss

[PATCH 5/9] Fix memory leak in tree-vect-slp.c

Leak can be seen e.g. here: gcc pr68817.f90 -fno-diagnostics-show-caret -fdiagnostics-color=never -O -O3 -ffast-math gcc/ChangeLog: 2016-05-18 Martin Liska * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Release bitmap. --- gcc/tree-vect-slp.c | 5 - 1 file changed

[PATCH 4/9] Fix memory leak in omp-simd-clone.c

Leak can be seen e.g. here: gcc pr68339.c -fno-diagnostics-show-caret -fdiagnostics-color=never --param ggc-min-heapsize=0 --param ggc-min-expand=0 -fopenmp-simd gcc/ChangeLog: 2016-05-18 Martin Liska * omp-simd-clone.c (simd_clone_adjust): Release vector. --- gcc/omp-simd-clone.c |

[PATCH 1/9] Change ENABLE_VALGRIND_CHECKING to ENABLE_VALGRIND_ANNOTATIONS guard.

Following change is very similar to what I did in: https://gcc.gnu.org/ml/gcc-patches/2016-01/msg02103.html It's more logical to encapsulate valgrind annotation magic within a ENABLE_VALGRIND_ANNOTATIONS macro rather than ENABLE_VALGRIND_CHECKING. libcpp/ChangeLog: 2016-05-18 Martin Liska

[PATCH 8/9] Fix memory leak in tree-parloops.c

The leak can be seen here: gcc kernels-counter-vars-function-scope.c -fno-diagnostics-show-caret \ -fdiagnostics-color=never -fopenacc -O2 -fdump-tree-parloops1-all gcc/ChangeLog: 2016-05-18 Martin Liska * tree-parloops.c (oacc_entry_exit_ok): Release a vector. --- gcc/tree-parloops.

[PATCH 7/9] Fix memory leak in tree-if-conv.c

Leak can be seen e.g. here: gcc i386/pr50482.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O3 -msse4 gcc/ChangeLog: 2016-05-18 Martin Liska * tree-if-conv.c (ifcvt_repair_bool_pattern): Utilize auto_vecs. --- gcc/tree-if-conv.c | 4 ++-- 1 file changed, 2 insertions(+), 2

Re: [PATCH 4/9] Fix memory leak in omp-simd-clone.c

On Thu, May 19, 2016 at 12:44:10PM +0200, marxin wrote: > Leak can be seen e.g. here: > gcc pr68339.c -fno-diagnostics-show-caret -fdiagnostics-color=never --param > ggc-min-heapsize=0 --param ggc-min-expand=0 -fopenmp-simd > > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * omp-simd-

[PATCH 9/9] Fix memory leak in tree-vect-stmts.c

The leak can be seen here: gcc pr60823-2.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O2 \ -fopenmp-simd gcc/ChangeLog: 2016-05-18 Martin Liska * tree-vect-stmts.c (vectorizable_simd_clone_call): Utilize auto_vec instead of vec. --- gcc/tree-vect-stmts.c | 21

[PATCH 6/9] Fix memory leak in ipa-pure-const

Leak can be seen e.g. here: gcc i386/mvc6.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O3 gcc/ChangeLog: 2016-05-18 Martin Liska * ipa-pure-const.c (set_function_state): Remove an existing funct_state. (remove_node_data): Do not free it as it's released

Re: [PATCH 5/9] Fix memory leak in tree-vect-slp.c

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > Leak can be seen e.g. here: > gcc pr68817.f90 -fno-diagnostics-show-caret -fdiagnostics-color=never -O -O3 > -ffast-math Ok for trunk and branches. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * tree-vect-slp.c (vect_att

Re: [PATCH 2/9] Fix leak in tree-ssa-loop-prefetch.c

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > This fixes memory leak which can be e.g. for > 20020122-2.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O2 > -fprefetch-loop-arrays. Ok. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * tree-ssa-loop-prefetch.c

Re: [PATCH 7/9] Fix memory leak in tree-if-conv.c

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > Leak can be seen e.g. here: > gcc i386/pr50482.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O3 > -msse4 Ok. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * tree-if-conv.c (ifcvt_repair_bool_pattern): Utilize a

Re: [PATCH 3/9] Fix leak in gcc/tree-ssa-reassoc.c.

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > Leak can be seen e.g. here: > gcc reassoc-11.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O2 > -fdump-tree-reassoc1 Ok. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * tree-ssa-reassoc.c (eliminate_duplicate_p

Re: [PATCH 8/9] Fix memory leak in tree-parloops.c

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > The leak can be seen here: > gcc kernels-counter-vars-function-scope.c -fno-diagnostics-show-caret \ > -fdiagnostics-color=never -fopenacc -O2 -fdump-tree-parloops1-all Ok. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * t

Re: [PATCH 9/9] Fix memory leak in tree-vect-stmts.c

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > The leak can be seen here: > gcc pr60823-2.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O2 \ > -fopenmp-simd Ok. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * tree-vect-stmts.c (vectorizable_simd_clone_call):

Re: [PATCH v3] Take known zero bits into account when checking extraction.

On Mon, May 16, 2016 at 01:09:36PM -0600, Jeff Law wrote: > On 05/11/2016 02:52 AM, Dominik Vogt wrote: > >On Wed, May 11, 2016 at 10:40:11AM +0200, Bernd Schmidt wrote: > >That's what I mentioned somewhere during the discussion. The s390 > >backend just uses COSTS_N_INSNS(1) for AND as well as ZE

Re: [PATCH 6/9] Fix memory leak in ipa-pure-const

On Thu, May 19, 2016 at 12:44 PM, marxin wrote: > Leak can be seen e.g. here: > gcc i386/mvc6.c -fno-diagnostics-show-caret -fdiagnostics-color=never -O3 Ok. Richard. > gcc/ChangeLog: > > 2016-05-18 Martin Liska > > * ipa-pure-const.c (set_function_state): Remove an existing >

[PATCH][AArch64] Remove aarch64_cannot_change_mode_class

Remove aarch64_cannot_change_mode_class as the underlying issue (PR67609) has been resolved. This avoids a few unnecessary lane widening operations like: faddp d18, v18.2d mov d18, v18.d[0] Passes regress, OK for commit? ChangeLog: 2016-05-19 Wilco Dijkstra * gcc/config/aarch

Re: [PATCH 1/3] Encapsulate comp_cost within a class with methods.

On Thu, May 19, 2016 at 11:23 AM, Martin Liška wrote: > On 05/16/2016 03:55 PM, Martin Liška wrote: >> On 05/16/2016 12:13 PM, Bin.Cheng wrote: >>> Hi Martin, >>> Could you please rebase this patch and the profiling one against >>> latest trunk? The third patch was applied before these two now. >

Re: inhibit the sincos optimization when the target has sin and cos instructions

On Wed, 18 May 2016, Cesar Philippidis wrote: > >> +(define_expand "sincossf3" > >> + [(set (match_operand:SF 0 "nvptx_register_operand" "=R") > >> +(unspec:SF [(match_operand:SF 2 "nvptx_register_operand" "R")] > >> + UNSPEC_COS)) > >> + (set (match_operand:SF 1 "nvptx_registe

Re: [PATCH][PR sanitizer/64354] Define __SANITIZE_THREAD__ and __SANITIZE_UNDEFINED__ macros if corresponding switches are enabled.

On 18/05/16 20:36, Jakub Jelinek wrote: On Wed, May 18, 2016 at 08:33:53PM +0300, Maxim Ostapenko wrote: when compiling with -fsanitize=address we define __SANITIZE_ADDRESS__ macros, but we don't do this for -fsanitize=thread and -fsanitize=undefined. Perhaps we should be more symmetric here and

Re: [PATCH][PR sanitizer/64354] Define __SANITIZE_THREAD__ and __SANITIZE_UNDEFINED__ macros if corresponding switches are enabled.

On Thu, May 19, 2016 at 02:48:32PM +0300, Maxim Ostapenko wrote: > On 18/05/16 20:36, Jakub Jelinek wrote: > >On Wed, May 18, 2016 at 08:33:53PM +0300, Maxim Ostapenko wrote: > >>when compiling with -fsanitize=address we define __SANITIZE_ADDRESS__ > >>macros, but we don't do this for -fsanitize=th

Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests.

On 13 May 2016 at 16:47, James Greenhalgh wrote: > On Fri, May 13, 2016 at 04:41:33PM +0200, Christophe Lyon wrote: >> On 13 May 2016 at 16:37, James Greenhalgh wrote: >> > On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote: >> >> 2016-05-02 Christophe Lyon >> >> >> >> * gcc

[PATCH] [ARC] New CPU C-define handler.

This patch refactors how we handle the built-in preprocessor macros and assertions for ARC. OK to apply? Claudiu gcc/ 2016-05-02 Claudiu Zissulescu * config/arc/arc-c.c: New file. * config/arc/arc-c.def: Likewise. * config/arc/t-arc: Likewise. * config.gcc: In

[6, 5, 4.9] demangler backports

Hi! I've backported the fuzzing/exploit fixes for the demangler to 6.x, 5.x and 4.9.x branches. Enhancements etc. I've left out. To 6.x just the first two parts of the first patch, to 5.x the first 3 patches, to 4.9.x all the patches. Jakub 2016-05-19 Jakub Jelinek Backporte

Re: [PATCH] Fix PR tree-optimization/71170

On 19 May 2016 at 18:55, Richard Biener wrote: > On Thu, May 19, 2016 at 10:26 AM, Kugan > wrote: >> Hi, >> >> >> On 19/05/16 18:21, Richard Biener wrote: >>> On Thu, May 19, 2016 at 10:12 AM, Kugan Vivekanandarajah >>> wrote: Hi Martin, Thanks for the fix. Just to elaborate (as m

[PATCH] LTO: display file name if LTO version check fails

Hi. During the compilation of chrome, I've noticed that they utilize 'cc' binary. Because of that, I see LTO version check, but it would be quite useful to see which file is affected. Like: lto1: fatal error: bytecode stream in file 'obj/third_party/icu/source/common/icuuc.cmemory.o' generated

Re: [PATCH] LTO: display file name if LTO version check fails

On Thu, May 19, 2016 at 2:21 PM, Martin Liška wrote: > Hi. > > During the compilation of chrome, I've noticed that they utilize 'cc' binary. > Because of that, I see LTO version check, but it would be quite useful to > see which file is affected. > > Like: > > lto1: fatal error: bytecode stream in

Re: [PATCH] Fix PR tree-optimization/71170

On Thu, May 19, 2016 at 2:18 PM, Kugan Vivekanandarajah wrote: > On 19 May 2016 at 18:55, Richard Biener wrote: >> On Thu, May 19, 2016 at 10:26 AM, Kugan >> wrote: >>> Hi, >>> >>> >>> On 19/05/16 18:21, Richard Biener wrote: On Thu, May 19, 2016 at 10:12 AM, Kugan Vivekanandarajah wr

[PATCH v2] Ensure source_date_epoch is always initialised

gcc/c-family PR preprocessor/71183 * c-common.c (get_source_date_epoch): Move to libcpp/init.c. * c-common.h (get_source_date_epoch): Remove definition, as it is now internal to libcpp/init.c. * c-lex.c (c_lex_with_flags): Remove source_date_epoch ini

Re: [Patch, avr] Include INCOMING_FRAME_SP_OFFSET when printing stack usage

Ping! Regards Senthil Senthil Kumar Selvaraj writes: > Hi, > > This trivial patch adds INCOMING_FRAME_SP_OFFSET to > current_function_static_stack_size, thus fixing the 2 (or 3, for > 3 byte PC devices) byte difference between reported and actual > values when using -fstack-usage. > >

Re: [PATCH 0/3] Support for mandatory tail calls

On Thu, May 19, 2016 at 12:30 AM, Basile Starynkevitch wrote: > On 05/19/2016 12:12 AM, Jeff Law wrote: >> >> On 05/17/2016 04:01 PM, David Malcolm wrote: >>> >>> There have been requests [1] for libgccjit to better support >>> functional programming by supporting the contination-passing style, >>

Re: [PATCH][RFC] Introduce BIT_FIELD_INSERT

On Tue, 17 May 2016, Michael Matz wrote: > Hi, > > On Tue, 17 May 2016, Richard Biener wrote: > > > BIT_INSERT_EXPR > > This. > > > Any preference? Here is an updated patch. Bootstrapped and tested on x86_64-unknown-linux-gnu. I plan to commit this tomorrow if there are no further comments

Re: [PATCH][ARM] PR target/71056: Don't use vectorized builtins when NEON is not available

Ping. https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00842.html Thanks, Kyrill On 11/05/16 15:32, Kyrill Tkachov wrote: Hi all, In this PR a NEON builtin is introduced during SLP vectorisation even when NEON is not available because arm_builtin_vectorized_function is missing an appropriate che

Re: [PATCH][AArch64] Simplify ashl3 expander for SHORT modes

Ping. Thanks, Kyrill On 11/05/16 10:01, Kyrill Tkachov wrote: Ping. https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01651.html Thanks, Kyrill On 27/04/16 15:10, Kyrill Tkachov wrote: Hi all, The ashl3 expander for QI and HI modes is needlessly obfuscated. The 2nd operand predicate accepts non

Re: [PATCH][AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes

Ping. Thanks, Kyrill On 11/05/16 10:00, Kyrill Tkachov wrote: Ping. https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01652.html Thanks, Kyrill On 27/04/16 15:12, Kyrill Tkachov wrote: Hi all, The CC_ZESWP and CC_SESWP are not used anywhere and seem to be a remmant of some old code that was remov

Re: [PATCH][ARM] Fix costing of sign-extending load in rtx costs

Ping. Thanks, Kyrill On 11/05/16 10:00, Kyrill Tkachov wrote: Ping. https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01655.html Thanks, Kyrill On 27/04/16 15:13, Kyrill Tkachov wrote: Hi all, Another costs issue that came out of the investigation for PR 65932 is that sign-extending loads get a

Re: [PATCH][ARM] Use proper output modifier for DImode register in store exclusive patterns

Ping. Thanks, Kyrill On 09/05/16 12:13, Kyrill Tkachov wrote: Hi all, This seems to have fallen through the cracks. Ping. https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00558.html Thanks, Kyrill On 09/03/16 12:56, Kyrill Tkachov wrote: Hi all, I notice that the output code for our store exc

Re: [PATCH 0/3] Support for mandatory tail calls

On Thu, May 19, 2016 at 3:19 PM, Jason Merrill wrote: > On Thu, May 19, 2016 at 12:30 AM, Basile Starynkevitch > wrote: >> On 05/19/2016 12:12 AM, Jeff Law wrote: >>> >>> On 05/17/2016 04:01 PM, David Malcolm wrote: There have been requests [1] for libgccjit to better support funct

Re: [PATCH] c++/71147 - [6 Regression] Flexible array member wrongly rejected in template

On 05/18/2016 09:40 PM, Martin Sebor wrote: The handling of flexible array members whose element type was dependent tried to deal with the case when the element type was not yet completed but it did it wrong. The attached patch corrects the handling by trying to complete the element type first.

Re: [PATCH 0/3] Support for mandatory tail calls

On Thu, May 19, 2016 at 9:28 AM, Richard Biener wrote: > On Thu, May 19, 2016 at 3:19 PM, Jason Merrill wrote: >> On Thu, May 19, 2016 at 12:30 AM, Basile Starynkevitch >> wrote: >>> On 05/19/2016 12:12 AM, Jeff Law wrote: On 05/17/2016 04:01 PM, David Malcolm wrote: > > There

Re: [PATCH][ARM] PR target/71056: Don't use vectorized builtins when NEON is not available

On 11/05/16 15:32, Kyrill Tkachov wrote: > Hi all, > > In this PR a NEON builtin is introduced during SLP vectorisation even when > NEON is not available > because arm_builtin_vectorized_function is missing an appropriate check in > the BSWAP handling code. > > Then during expand when we try to

Re: [PATCH] PR c++/71184: Fix NULL dereference in cp_parser_operator

On 05/18/2016 08:59 PM, David Malcolm wrote: + cp_token *close_token = + cp_parser_require (parser, CPP_CLOSE_SQUARE, RT_CLOSE_SQUARE); + if (close_token) + end_loc = close_token->location; You could combine these into if (cp_token *close_token =

[PATCH] Assuage ICE in VRP with [1, X] + UINT_MAX (PR tree-optimization/71031)

Since Bin's changes to the niter analysis in r231097, we find ourselves in a situation where extract_range_from_binary_expr is given [1, od_5] + UINT_MAX on type unsigned. We combine the lower bounds, which is 1 + UINT_MAX = 0(OVF). We then combine the upper bounds, because the max_op0 is not a co

Re: [PATCH][ARM] Fix costing of sign-extending load in rtx costs

On 27/04/16 15:13, Kyrill Tkachov wrote: > Hi all, > > Another costs issue that came out of the investigation for PR 65932 is that > sign-extending loads get a higher cost than they should in the arm backend. > The problem is that when handling a sign-extend of a MEM we add the cost > of the load_

Re: [PATCH] Assuage ICE in VRP with [1, X] + UINT_MAX (PR tree-optimization/71031)

On Thu, 19 May 2016, Marek Polacek wrote: > Since Bin's changes to the niter analysis in r231097, we find ourselves in > a situation where extract_range_from_binary_expr is given [1, od_5] + UINT_MAX > on type unsigned. We combine the lower bounds, which is 1 + UINT_MAX = > 0(OVF). > We then com

Re: [C++ Patch/RFC] PR 70572 ("[4.9/5/6/7 Regression] ICE on code with decltype (auto) on x86_64-linux-gnu in digest_init_r")

On 05/18/2016 07:13 PM, Paolo Carlini wrote: + error ("cannot declare variable %q+D with function type", decl); I think the error message would be more helpful if it mentioned decltype(auto), maybe "initializer for % has function type, did you forget the %<()%>?", DECL_NAME (decl)

[PATCH] Speed up if-cvt

This avoids re-computing BB predicates. The more interesting job will be to avoid re-computing post dominators (for the whole function) all the time. Bootstrap / regtest running on x86_64-unknown-linux-gnu. Richard. 2016-05-19 Richard Biener * tree-if-conv.c (add_bb_predicate_gimpl

Re: [PR 70646] Store size to inlining predicate conditions

Hi, On Wed, May 18, 2016 at 12:19:11PM +0200, jh wrote: > Dne 2016-05-11 17:45, Martin Jambor napsal: > > Hi, > > > > > > 2016-04-20 Martin Jambor > > > > PR ipa/70646 > > * ipa-inline.h (condition): New field size. > > * ipa-inline-analysis.c (add_condition): New parameter SIZE,

Re: [PATCH][CilkPlus] Allow parenthesized initialization in for-loops

On 05/10/2016 03:28 PM, Ilya Verbin wrote: What about (some_class i { 0 }; some_class < ...; some_class++) and similar syntax? It's allowed, thanks, I missed this in the initial patch. The testsuite coverage is insufficient (nothing e.g. tests templates or #pragma simd). Patch is updated.

[PATCH], PR 71201, Fix xxperm on PowerPC ISA 3.0, add vpermr/xxpermr support

GCC 6.1 added support for the XXPERM instruction for the PowerPC ISA 3.0. The XXPERM instruction is essentially a 4 operand instruction, with only 3 operands in the instruction (the target register overlaps with the first input register). The Power9 hardware has fusion support where if the instru

Re: [PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.

On 18/05/16 16:20, Joseph Myers wrote: On Wed, 18 May 2016, Matthew Wahab wrote: AArch64 follows IEEE-754 but ARM (AArch32) adds restrictions like flush-to-zero that could affect the outcome of a calculation. The result of a float computation on two values immediately promoted from fp16 canno

[PATCH, libstdc++] Add missing atomic-builtins argument to experimental/memory_resource/1.cc

Hi Jonathan, The dg-require-atomic-builtins in experimental/memory_resource/1.cc does not currently work as intended because it is missing its argument. This patch fixes that. ChangeLog entry is as follows: *** libstdc++-v3/ChangeLog *** 2016-05-18 Thomas Preud'homme * testsuite/e

Re: [PATCH] Assuage ICE in VRP with [1, X] + UINT_MAX (PR tree-optimization/71031)

On Thu, May 19, 2016 at 03:54:05PM +0200, Richard Biener wrote: > On Thu, 19 May 2016, Marek Polacek wrote: > > > Since Bin's changes to the niter analysis in r231097, we find ourselves in > > a situation where extract_range_from_binary_expr is given [1, od_5] + > > UINT_MAX > > on type unsigned.

Re: [PATCH][RFC] Introduce BIT_FIELD_INSERT

> Index: trunk/gcc/tree.def > === > *** trunk.orig/gcc/tree.def 2016-05-17 17:19:41.783958489 +0200 > --- trunk/gcc/tree.def2016-05-19 10:23:35.779141973 +0200 > *** DEFTREECODE (ADDR_EXPR, "addr_expr", tcc > ***

[PATCH][wwwdocs] Improve arm and aarch64-related info in readings.html

Hi all, I noticed that we have a readings.html page that has pointers to documentation of various backends that GCC supports. The info on arm seems a bit out of date and somewhat confusing, and there is no entry for aarch64. This patch tries to address that. The arm entry is updated to not men

Re: [PATCH] Assuage ICE in VRP with [1, X] + UINT_MAX (PR tree-optimization/71031)

On May 19, 2016 5:14:24 PM GMT+02:00, Marek Polacek wrote: >On Thu, May 19, 2016 at 03:54:05PM +0200, Richard Biener wrote: >> On Thu, 19 May 2016, Marek Polacek wrote: >> >> > Since Bin's changes to the niter analysis in r231097, we find >ourselves in >> > a situation where extract_range_from_bi

Re: [PATCH], PR 71201, Fix xxperm on PowerPC ISA 3.0, add vpermr/xxpermr support

On Thu, May 19, 2016 at 10:53:41AM -0400, Michael Meissner wrote: > GCC 6.1 added support for the XXPERM instruction for the PowerPC ISA 3.0. The > XXPERM instruction is essentially a 4 operand instruction, with only 3 > operands > in the instruction (the target register overlaps with the first i

Re: C PATCH to add -Wswitch-unreachable (PR c/49859)

Any comments on this patch? Should I pursue the C++ part? On Tue, May 10, 2016 at 08:19:29PM +0200, Marek Polacek wrote: > Over the years, we got several PRs that suggested to add a warning that would > warn about unreachable statements between `switch (cond)' and the first case. > In some cases

Make vectorizer to use max_loop_iterations_int

Hi, this patch makes vect_analyze_loop_2 to give up on loops with low max iteration counts (instead of only considering estimated_stmt_executions_int). This change was eaerlier approved by Richi in stage4 and reverted. I got wrong the testm instead == -1 there was != -1 and thus the regressions. N

Re: C PATCH to add -Wswitch-unreachable (PR c/49859)

Why implement this in the front end rather than at the gimple level? Jason On Tue, May 10, 2016 at 2:19 PM, Marek Polacek wrote: > Over the years, we got several PRs that suggested to add a warning that would > warn about unreachable statements between `switch (cond)' and the first case. > In s

Make do_loop use estimated_num_iterations/expected_num_iterations

Hi, this patch makes doloop_optimize to use the get_estimated_loop_iterations_int/get_max_loop_iterations_int instead of weakter check for const_iter. Bootstrapped/regtested x86_64-linux, OK? Honza * loop-doloop.c (doloop_optimize): Use get_estimated_loop_iterations_int and get_m

Re: [PATCH] Fix PR c++/70822 (bogus error with parenthesized SCOPE_REF)

OK. Jason

Re: [PING][PATCH] New plugin event when evaluating a constexpr call

On 05/06/2016 10:23 AM, Andres Tiraboschi wrote: +static tree +eval_call_plugin_callback (const constexpr_ctx *ctx, tree fun, + bool lval, bool *non_constant_p, bool *overflow_p) This function needs a comment. -static void +void cxx_bind_parameters_in_call (const con

Re: [PATCH, ARM 4/7, ping1] Factor out MOVW/MOVT availability and desirability checks

On Wednesday 18 May 2016 11:47:47 Kyrill Tkachov wrote: > Hi Thomas, Hi Kyrill, Please find below the updated patch and associated ChangeLog entry. *** gcc/ChangeLog *** 2016-05-18 Thomas Preud'homme * config/arm/arm.h (TARGET_USE_MOVT): Check MOVT/MOVW availability with TAR

Re: [PATCH, ARM 5/7, ping1] Add support for MOVT/MOVW to ARMv8-M Baseline

On Wednesday 18 May 2016 12:30:41 Kyrill Tkachov wrote: > Hi Thomas, > > This looks mostly good with a few nits inline. > Please repost with the comments addressed. Updated ChangeLog entries: *** gcc/ChangeLog *** 2016-05-18 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_MOVT):

Re: [PATCH, ARM 7/7, ping1] Enable atomics for ARMv8-M Mainline

Hi Thomas, On 17/05/16 11:15, Thomas Preudhomme wrote: Ping? *** gcc/ChangeLog *** 2015-12-17 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 347b5b0a5cc0bc1e3b5020c8124d968e76

Re: [Patch ARM/AArch64 08/11] Add missing vstX_lane fp16 tests.

On 11/05/16 14:23, Christophe Lyon wrote: 2016-05-02 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Add fp16 tests. Ok. Thanks, Kyrill Change-Id: I64e30bc30a9a9cc5c47eff212e7d745bf3230fe7 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

Hi Christophe, On 11/05/16 14:23, Christophe Lyon wrote: 2016-05-02 Christophe Lyon * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intr

Re: [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

On 13/05/16 16:16, James Greenhalgh wrote: On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote: 2016-05-02 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result): Add poly64x1_t and poly64x2_t cases if supported. * gcc.target/aarc

Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

On 11/05/16 14:24, Christophe Lyon wrote: 2016-05-04 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_

Re: [C++ PATCH] PR c++/69855

On 05/05/2016 09:11 AM, Ville Voutilainen wrote: On 5 May 2016 at 13:36, Paolo Carlini wrote: .. minor nit: the new testcase has a number of trailing blank lines. New patch attached. :) Sorry for the delay. Please use ".diff" for patches so that they are properly recognized as text/x-patc

Re: [PATCH, libgcc/ARM 1/6, ping1] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

Hi Thomas, I'm not very familiar with the libgcc machinery, but I have a comment on an arm.h hunk inline. On 17/05/16 10:58, Thomas Preudhomme wrote: Ping? *** gcc/ChangeLog *** 2015-11-13 Thomas Preud'homme * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to

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